Organic light emitting diode display device and driving method thereof

Abstract

The present disclosure relates to an organic light emitting diode display apparatus and a driving method thereof. An organic light emitting diode display apparatus includes a plurality of pixels arranged in a matrix of a plurality of rows and a plurality of columns, a gate1 line connected to the plurality of pixels of each of the plurality of rows and providing a gate1 voltage to the plurality of pixels of each of the plurality of rows, a gate2 line connected to the plurality of pixels of a portion of the plurality of columns and providing a gate2 voltage of a current row to the plurality of pixels of the portion of the plurality of columns, a gate2 extension line connected to the plurality of pixels of another portion of the plurality of columns and providing a gate2 voltage of an adjacent row to the plurality of pixels of the another portion of the plurality of columns, and a left data line and a right data line disposed in left and right portions of the plurality of pixels of each of the plurality of columns.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0190615, filed on December 29, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to organic light-emitting diode (OLED) display devices, and more specifically, to OLED display devices in which multiple pixels in a row have different sampling periods, and to methods for driving OLED display devices. Background Technology

[0004] With the advancement towards an information society, the demand for display devices for displaying images has increased in various forms. In the field of display devices, the relatively large cathode ray tube (CRT) has been rapidly replaced by flat panel display (FPD) devices, which have a thinner profile, lighter weight, and are suitable for relatively large sizes.

[0005] In FPD devices, organic light-emitting diode (OLED) displays are light-emitting devices and do not include the backlight unit used in non-light-emitting devices such as liquid crystal displays (LCDs). Therefore, OLED displays offer advantages in terms of viewing angle, contrast ratio, and power consumption, making them suitable for a wide range of applications.

[0006] OLED displays show images by supplying data voltages output from data driving units to the pixels of the display panel. As resolution and driving speed increase, the time required to apply the data voltage to each pixel decreases. This reduces the charging time of the data lines.

[0007] To address the aforementioned issues, an OLED display device has been proposed that uses two multiplexer transistors and two data lines to supply data voltage to a pixel column.

[0008] In the aforementioned OLED display device, since two adjacent pixel rows are driven to overlap by a horizontal time period (1H), one data line is floated for that horizontal time period, and the data voltage of the floated data line is distorted due to the change (ripple) in the high-level voltage generated according to the change in the data voltage of the other data line. Therefore, degradation such as crosstalk occurs. Summary of the Invention

[0009] Therefore, this disclosure relates to an organic light-emitting diode display device and a driving method thereof, which substantially eliminates one or more problems caused by the aforementioned limitations and disadvantages.

[0010] The purpose of this disclosure is to provide an organic light-emitting diode (OLED) display device and a method for driving the OLED display device, in which the number of pixels corresponding to floating data lines is reduced due to multiple pixels in a row with different sampling periods, and the distortion and crosstalk of data voltage according to the change (ripple) of high-level voltage are minimized.

[0011] Another object of this disclosure is to provide an organic light-emitting diode (OLED) display device and a method for driving the OLED display device, wherein by arranging the gate2 line and the gate2 extension line in a row and alternately providing two gate2 voltages to multiple pixels in the row, the gate driving unit is simplified, the number of pixels corresponding to floating data lines is reduced, and distortion and crosstalk of data voltages based on changes in high-level voltage (ripple) are minimized.

[0012] Further features and aspects will be set forth in the description which follows, and in part will become apparent from the description, or may be learned by practice of the disclosure provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures particularly pointed out in the written description or those derived therefrom, as well as by the claims and drawings thereof.

[0013] To achieve these and other aspects of this disclosure, as embodied and broadly described herein, an organic light-emitting diode display device includes: a plurality of pixels arranged in a matrix of a plurality of rows and a plurality of columns; a gate1 line connected to a plurality of pixels in each of the plurality of rows and providing a gate1 voltage to the plurality of pixels in each of the plurality of rows; a gate2 line connected to a plurality of pixels in a portion of a plurality of columns and providing a gate2 voltage of the current row to the plurality of pixels in a portion of the plurality of columns; a gate2 extension line connected to a plurality of pixels in another portion of the plurality of columns and providing a gate2 voltage of the adjacent row to the plurality of pixels in another portion of the plurality of columns; and a left data line and a right data line disposed in the left and right portions of the plurality of pixels in each of the plurality of columns.

[0014] In another aspect, a method for driving an organic light-emitting diode display device includes: initializing a plurality of pixels in a plurality of rows according to a gate1 voltage; sampling a plurality of pixels in a portion of a plurality of columns according to a gate2 voltage of the current row; sampling a plurality of pixels in another portion of a plurality of columns according to a gate2 voltage of an adjacent row; and emitting light from the plurality of pixels according to an emission voltage.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0016] The accompanying drawings illustrate various aspects of this disclosure and, together with the description, serve to illustrate the various principles of this disclosure. The drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application.

[0017] In the attached diagram:

[0018] Figure 1 This is a plan view showing an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0019] Figure 2 This is a plan view showing the multiplexer unit and display panel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0020] Figure 3 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0021] Figure 4 This is a view showing the connection between the pixel and gate voltage of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0022] Figure 5 This is a view illustrating multiple signals used in a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0023] Figure 6A This is a view showing the variation of the high-level voltage of an organic light-emitting diode display device according to a comparative example;

[0024] Figure 6B This is a view showing the change of the high-level voltage of an organic light-emitting diode display device according to a first embodiment of the present disclosure;

[0025] Figure 7 This is a view showing the connection between the pixels and the gate voltage of an organic light-emitting diode display device according to a second embodiment of the present disclosure; and

[0026] Figure 8 This is a view showing the connection of the pixel and gate voltage of an organic light-emitting diode display device according to a third embodiment of the present disclosure. Detailed Implementation

[0027] Reference will now be made in detail to various aspects of this disclosure, exemplary embodiments of which are illustrated in the accompanying drawings.

[0028] Figure 1This is a plan view showing an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0029] exist Figure 1 In the first embodiment of the present disclosure, the organic light-emitting diode (OLED) display device 110 includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, a multiplexer unit 150, and a display panel 160.

[0030] The timing control unit 120 uses image signals and multiple timing signals to generate image data, data control signals, and gate control signals. These multiple timing signals include a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal transmitted from an external system such as a graphics card or television system. The image data and data control signals are transmitted to the data drive unit 130, and the gate control signals are transmitted to the gate drive unit 140.

[0031] The data drive unit 130 uses the data control signal and image data transmitted from the timing control unit 120 to generate a data voltage (data signal) and transmits the data voltage to the multiplexer unit 150.

[0032] The gate driving unit 140 uses the gate control signal transmitted from the timing control unit 120 to generate a gate voltage (gate signal) and applies the gate voltage to the gate line GL of the display panel 160.

[0033] The gate driving unit 140 may have an in-board gate (GIP) type that is to be formed in the non-display area NDA of the substrate of the display panel 160 having a gate line GL, a left data line DLL, a right data line DLR, and a pixel P.

[0034] The multiplexer unit 150 selectively applies the data voltage transmitted from the data drive unit 120 to one of the left data line DLL and the right data line DLR of the display panel 160.

[0035] Multiplexer unit 150 is configured to correspond to the long side of display panel 160 and connected to the ends of left data line DLL and right data line DLR. Multiplexer unit 150 includes a first multiplexer transistor and a second multiplexer transistor. The first multiplexer transistor and the second multiplexer transistor can... Figure 2 As shown in the image.

[0036] Display panel 160 uses gate voltage and data voltage to display images. Display panel 160 includes a display area DA for displaying images and a non-display area NDA surrounding the display area DA. Gate drive unit 140 and multiplexer unit 150 are disposed in the non-display area NDA, and multiple pixels P, multiple gate lines GL, multiple left data lines DLL, and multiple right data lines DLR are disposed in the display area DA.

[0037] Each of the multiple pixels P includes multiple subpixels SP. For example, the multiple subpixels SP may include a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb.

[0038] Gate line GL intersects with left data line DLL and right data line DLR to define sub-pixel SP.

[0039] The left data line DLL is set in the left part of each sub-pixel SP, and the right data line DLR is set in the right part of each sub-pixel SP.

[0040] For example, the sub-pixel SP of odd-numbered rows (horizontal pixel lines) HLo can be connected to the gate line GL and the left data line DLL, while the sub-pixel SP of even-numbered rows HLe can be connected to the gate line GL and the right data line DLR.

[0041] The multiplexer unit 150 of the OLED display device 110 will be described with reference to the accompanying drawings.

[0042] Figure 2 This is a plan view showing the multiplexer unit and display panel of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0043] exist Figure 2 In the first embodiment of the OLED display device 110 according to this disclosure, the multiplexer unit 150 includes a first multiplexer transistor Tm1 and a second multiplexer transistor Tm2. The first multiplexer transistor Tm1 and the second multiplexer transistor Tm2 can be positive type transistors.

[0044] The first multiplexer transistor Tm1 switches according to the first multiplexer voltage MUX1, transmitting the data voltage Vdata of the data driving unit 130 to the left data line DLL of the odd-numbered column (vertical pixel line) VLo and the right data line DLR of the even-numbered column VLe of the display panel 160. The second multiplexer transistor Tm2 switches according to the second multiplexer voltage MUX2, transmitting the data voltage Vdata of the data driving unit 130 to the right data line DLR of the odd-numbered column VLo and the left data line DLL of the even-numbered column VLe of the display panel 160.

[0045] For example, the first multiplexer voltage MUX1 and the second multiplexer voltage MUX2 may include square waves with opposite polarities and a horizontal time period (1H) width.

[0046] During a horizontal time interval in which the first multiplexer transistor Tm1 is turned on and the second multiplexer transistor is turned off, the data voltage Vdata of the data driving unit 130 is provided by the multiplexer unit 150 to the sub-pixels SP of the odd-numbered rows HLo through the left data line DLL of the odd-numbered column VLo of the display panel 160, and is provided by the multiplexer unit 150 to the sub-pixels SP of the even-numbered rows HLe through the right data line DLR of the even-numbered column VLe of the display panel 160.

[0047] During a horizontal time interval in which the first multiplexer transistor Tm1 is off and the second multiplexer transistor is on, the data voltage Vdata of the data drive unit 130 is provided by the multiplexer unit 150 to the sub-pixels SP of the even-numbered rows HLe through the right data line DLR of the odd-numbered columns VLo of the display panel 160, and is provided by the multiplexer unit 150 to the sub-pixels SP of the odd-numbered rows HLo through the left data line DLL of the even-numbered columns VLe of the display panel 160.

[0048] During a horizontal time period, the data voltage Vdata is supplied to a sub-pixel SP in one of the odd-numbered rows HLo and even-numbered rows HLe via one of the left data lines DLL and DLR of each column VLo and VLe. During a horizontal time period (where the data voltage Vdata is supplied to a sub-pixel SP in one of the odd-numbered rows HLo and even-numbered rows HLe via the other of the left data lines DLL and DLR of each column VLo and VLe), the data voltage Vdata of the floating data lines in the left data line DLL and right data line DLR is maintained. Therefore, the application time of the data voltage Vdata is obtained for two horizontal time periods, and the charging time of the data voltage Vdata is increased.

[0049] Figure 3 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0050] exist Figure 3 In the first embodiment of the OLED display device according to the present disclosure, the nth sub-pixel SP(n) of the display panel 160 includes a driving transistor Td, a first transistor T1 to a ninth transistor T9, a storage capacitor Cst and a light-emitting diode De, where n is a natural number.

[0051] For example, the driving transistor Td, the first transistor T1 to the ninth transistor T9 can be of positive type.

[0052] The driving transistor Td switches (turns on and off) according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the driving transistor Td is connected to the first electrode of the storage capacitor Cst, the drain electrode of the first transistor T1, and the source electrode of the fifth transistor T5. The source electrode of the driving transistor Td is connected to the drain electrode of the second transistor T2 and the source electrode of the third transistor T3. Furthermore, the drain electrode of the driving transistor Td is connected to the source electrode of the first transistor T1 and the source electrode of the fourth transistor T4.

[0053] The first transistor T1 of the sampling transistor is switched according to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The gate electrode of the first transistor T1 is connected to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor Td and the source electrode of the fourth transistor T4. The drain electrode of the first transistor T1 is connected to the gate electrode of the driving transistor Td, the first electrode of the storage capacitor Cst, and the source electrode of the fifth transistor T5.

[0054] The second transistor T2 of the switching transistor is switched according to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The gate electrode of the second transistor T2 is connected to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The source electrode of the second transistor T2 is connected to the data voltage Vdata of the left data line DLL or the right data line DLR, and the drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor Td and the source electrode of the third transistor T3.

[0055] The third transistor T3, which is the emitter transistor, is switched according to the nth emitter voltage Em(n). The gate electrode of the third transistor T3 is connected to the nth emitter voltage Em(n), the source electrode of the third transistor T3 is connected to the source electrode of the driving transistor Td and the drain electrode of the second transistor T2, and the drain electrode of the third transistor T3 is connected to the source electrode of the seventh transistor T7 and the high-level voltage Vdd.

[0056] The fourth transistor T4 of the emitter transistor is switched according to the nth emitter voltage Em(n). The gate electrode of the fourth transistor T4 is connected to the nth emitter voltage Em(n), the source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor Td and the source electrode of the first transistor T1, and the drain electrode of the fourth transistor T4 is connected to the source electrode of the sixth transistor T6 and the anode of the light-emitting diode De.

[0057] The fifth transistor T5 is switched according to the nth gate1 voltage S1(n). The gate electrode of the fifth transistor T5 is connected to the nth gate1 voltage S1(n), the source electrode of the fifth transistor T5 is connected to the first electrode of the storage capacitor Cst, the gate electrode of the driving transistor Td and the drain electrode of the first transistor T1, and the drain electrode of the fifth transistor T5 is connected to the drain electrode of the sixth transistor T6 and the initial voltage Vini.

[0058] The sixth transistor T6 is switched according to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The gate electrode of the sixth transistor T6 is connected to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The source electrode of the sixth transistor T6 is connected to the drain electrode of the fourth transistor T4 and the anode of the light-emitting diode De. The drain electrode of the sixth transistor T6 is connected to the drain electrode of the fifth transistor T5 and the initial voltage Vini.

[0059] The seventh emitter transistor T7 switches according to the nth emitter voltage Em(n). The gate electrode of the seventh transistor T7 is connected to the nth emitter voltage Em(n), the source electrode of the seventh transistor T7 is connected to the drain electrode of the third transistor T3 and the high-level voltage Vdd, and the drain electrode of the seventh transistor T7 is connected to the source electrode of the eighth transistor T8, the source electrode of the ninth transistor T9 and the second electrode of the storage capacitor Cst.

[0060] The eighth transistor T8 is switched according to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The gate electrode of the eighth transistor T8 is connected to one of the (n-1)th gate2 voltage S2(n-1), the nth gate2 voltage S2(n), and the (n+1)th gate2 voltage S2(n+1). The source electrode of the eighth transistor T8 is connected to the drain electrode of the seventh transistor T7, the source electrode of the ninth transistor T9, and the second electrode of the storage capacitor Cst. The drain electrode of the eighth transistor T8 is connected to the drain electrode of the ninth transistor T9 and the reference voltage Vref.

[0061] The ninth transistor T9 is switched according to the nth gate1 voltage S1(n). The gate electrode of the ninth transistor T9 is connected to the nth gate1 voltage S1(n), the source electrode of the ninth transistor T9 is connected to the drain electrode of the seventh transistor T7, the source electrode of the eighth transistor T8 and the second electrode of the storage capacitor Cst, and the drain electrode of the ninth transistor T9 is connected to the drain electrode of the eighth transistor T8 and the reference voltage Vref.

[0062] The storage capacitor Cst stores the data voltage Vdata, the threshold voltage Vth, and the high-level voltage Vdd. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor Td, the drain electrode of the first transistor T1, and the source electrode of the fifth transistor T5, and the second electrode of the storage capacitor Cst is connected to the drain electrode of the seventh transistor T7, the source electrode of the eighth transistor T8, and the source electrode of the ninth transistor T9.

[0063] The light-emitting diode De is connected between the fourth transistor T4 and the sixth transistor T6 and the low-level voltage Vss, and emits light proportional to the current driving the transistor Td. The anode of the light-emitting diode De is connected to the drain electrode of the fourth transistor T4 and the source electrode of the sixth transistor T6, and the cathode of the light-emitting diode De is connected to the low-level voltage Vss.

[0064] The drain electrode of the driving transistor Td forms the first node N1, the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst form the second node N2, and the second electrode of the storage capacitor Cst forms the third node N3.

[0065] In the OLED display device 110, the light-emitting diode De emits light to display an image based on the operation of the driving transistor Td, the first transistor T1 to the ninth transistor T9, and the storage capacitor Cst. Therefore, the sub-pixel SP is used to compensate for changes in the threshold voltage of the light-emitting diode De based on its usage time or degradation, and the brightness is adjusted by driving the light-emitting diode De according to the duty cycle corresponding to the emission time.

[0066] In the OLED display device 110, by providing different gate2 voltages to multiple pixels in a row, the multiple pixels in a row have different sampling periods.

[0067] Figure 4 This is a view showing the connection of the pixels and gate voltages of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0068] exist Figure 4In the present disclosure, the OLED display device 110 according to the first embodiment includes a gate driving unit 140, a multiplexer unit 150, and a display panel 160.

[0069] The gate driving unit 140 includes a gate1 voltage generating section 142 that generates a plurality of gate1 voltages S1 and a gate2 voltage generating section 144 that generates a plurality of gate2 voltages S2. Each of the gate1 voltage generating section 142 and the gate2 voltage generating section 144 may include a shift register.

[0070] The multiplexer unit 150 includes: a first multiplexer transistor Tm1, which switches according to a first multiplexer voltage MUX1 to transmit the data voltage Vdata of the data driving unit 130 to one of the left data line DLL and the right data line DLR of the display panel 160; and a second multiplexer transistor Tm2, ​​which switches according to a second multiplexer voltage MUX2 to transmit the data voltage Vdata of the data driving unit 130 to the other of the left data line DLL and the right data line DLR of the display panel 160. The first multiplexer transistor Tm1 and the second multiplexer transistor Tm2 can be positive type transistors.

[0071] The display panel 160 includes a plurality of pixels P. The plurality of pixels P can be arranged in a matrix of a plurality of rows HL parallel to the horizontal direction and a plurality of columns VL parallel to the vertical direction.

[0072] For example, multiple pixels P may include 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6, and 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6 may be divided into a first row HL1, a second row HL2, a (n-1)th row HL(n-1) and an nth row HLn and a first column VL1 to a sixth column VL6.

[0073] The left data line DLL and the right data line DLR are respectively set in the left and right parts of each sub-pixel SP, and each sub-pixel SP is connected to one of the left data line DLL and the right data line DLR.

[0074] For example, the sub-pixels SP of odd-numbered rows HL1 and HL(n-1) can be connected to the gate line GL and the left data line DLL, while the sub-pixels SP of even-numbered rows HL2 and HLn can be connected to the gate line GL and the right data line DLR.

[0075] The gate1 line G1L, which transmits the gate1 voltage S1 of the current row, the gate2 line G2L, which transmits the gate2 voltage S2 of the current row, and the gate2 extension line G2EL, which transmits the gate2 voltage S2 of the previous or next row, are set in each of the multiple rows HL. The gate1 line G1L is connected to the sub-pixel SP of the pixel P of the pixel P in each column VL of each row HL, the gate2 line G2L is connected to the sub-pixel SP of the pixel P in the odd column VLo of each row HL, and the gate2 extension line G2EL is connected to the sub-pixel SP of the pixel P in the even column VLe of each row HL.

[0076] For example, the gate1 line G1L for transmitting the first gate1 voltage S1(1) of the current row, the gate2 line G2L for transmitting the first gate2 voltage S2(1) of the current row, and the gate2 extension line G2EL for transmitting the second gate2 voltage S2(2) of the next row are set in the first row HL1, and the gate1 line G1L for transmitting the second gate1 voltage S1(2) of the current row, the gate2 line G2L for transmitting the second gate2 voltage S2(2) of the current row, and the gate2 extension line G2EL for transmitting the first gate2 voltage S2(1) of the previous row are set in the second row HL2.

[0077] The gate1 line G1L that transmits the first gate1 voltage S1(1) of the current row is connected to the sub-pixels SP of the first row HL1, from pixel P11 to pixel P16 (1-1). The gate2 line G2L that transmits the first gate2 voltage S2(1) of the current row is connected to the sub-pixels SP of the first row HL1, from pixel P11 (1-1), from pixel P13 (1-3), to pixel P15 (1-5). The gate2 extension line G2EL that transmits the second gate2 voltage S2(2) of the next row is connected to the sub-pixels SP of the first row HL1, from pixel P12 (1-2), from pixel P14 (1-4), to pixel P16 (1-6).

[0078] The gate1 line G1L transmitting the second gate1 voltage S1(2) of the current row is connected to the sub-pixels SP of the second row HL2, from pixel 2-1 P21 to pixel 2-6 P26. The gate2 line G2L transmitting the second gate2 voltage S2(2) of the current row is connected to the sub-pixels SP of the second row HL2, from pixel 2-1 P21, from pixel 2-3 P23 to pixel 2-5 P25. The gate2 extension line G2EL transmitting the first gate2 voltage S2(1) of the previous row is connected to the sub-pixels SP of the second row HL2, from pixel 2-2 P22, from pixel 2-4 P24 to pixel 2-6 P26.

[0079] Similarly, the gate1 line G1L for transmitting the (n-1)th gate1 voltage S1(n-1) of the current row, the gate2 line G2L for transmitting the (n-1)th gate2 voltage S2(n-1) of the current row, and the gate2 extension line G2EL for transmitting the nth gate2 voltage S2(n) of the next row are set in the (n-1)th row HL(n-1), and the gate1 line G1L for transmitting the nth gate1 voltage S1(n) of the current row, the gate2 line G2L for transmitting the nth gate2 voltage S2(n) of the current row, and the gate2 extension line G2EL for transmitting the (n-1)th gate2 voltage S2(n-1) of the previous row are set in the nth row HLn.

[0080] The gate1 line G1L transmitting the (n-1)th gate1 voltage S1(n-1) of the current row is connected to the sub-pixels SP of pixels P(n-1)1 to P(n-1)6 of the (n-1)th HL(n-1) row. The gate2 line G2L transmitting the (n-1)th gate2 voltage S2(n-1) of the current row is connected to the sub-pixels SP of pixels P(n-1)1, P(n-1)3, and P(n-1)5 of the (n-1)th HL(n-1) row. The voltage transmission also transmits the voltage SP of the nth gate1 voltage of the next row. The gate2 extension line G2EL of the gate2 voltage S2(n) is connected to the sub-pixel SP of the (n-1)-2 pixel P(n-1)2, (n-1)-4 pixel P(n-1)4 and (n-1)-6 pixel P(n-1)6 of the (n-1) row HL(n-1).

[0081] The gate1 line G1L transmitting the nth gate1 voltage S1(n) of the current row is connected to the sub-pixels SP of the (n-1)th pixel Pn1 to the (n-6)th pixel Pn6 of the nth row HLn. The gate2 line G2L transmitting the nth gate2 voltage S2(n) of the current row is connected to the sub-pixels SP of the (n-1)th pixel Pn1, the (n-3)th pixel Pn3, and the (n-5)th pixel Pn5 of the nth row HLn. The gate2 extension line G2EL transmitting the (n-1)th gate2 voltage S2(n-1) of the previous row is connected to the sub-pixels SP of the (n-2)th pixel Pn2, the (n-4)th pixel Pn4, and the (n-6)th pixel Pn6 of the nth row HLn.

[0082] Therefore, the gate1 voltage S1 of the current row is provided to the sub-pixels SP of multiple pixels P in each of the multiple rows HL to perform an initialization period. Furthermore, the gate2 voltage S2 of the current row is provided to the sub-pixels SP of pixels P in the odd-numbered columns VLo of each of the multiple rows HL to perform a sampling period, and the gate2 voltage S2 of the previous or next row is provided to the sub-pixels SP of pixels P in the even-numbered columns VLe of each of the multiple rows HL to perform a sampling period.

[0083] Because the gate2 voltages S2 of different rows have different timing (e.g., a difference of one horizontal time period (1H)), sampling periods are performed in the sub-pixels SP of pixels P in the odd-numbered columns VLo and even-numbered columns VLe of each row in multiple rows HL during different intervals. Therefore, the coupling between data lines DLL and DLR and the power lines is reduced by half, the variation (ripple) of the high-level voltage Vdd of the power lines due to coupling is reduced, and the distortion of the data voltage Vdata due to the variation is reduced.

[0084] The detailed operation of the sub-pixels of the OLED display device 110 will be described with reference to the accompanying drawings.

[0085] Figure 5 This is a view illustrating multiple signals used in a sub-pixel of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0086] After explaining the operation on the nth sub-pixel SP(n) of pixel P in the odd column VLo of row n HLn, the operation on the nth sub-pixel SP(n) of pixel P in the even column VLe of row n HLn will be explained.

[0087] exist Figure 5 In the image, the frames used for displaying the image include a first time period TP1 to a fourth time period TP4. Each of the first time period TP1 and the second time period TP2 can be twice (2H) a horizontal time period 1H in which the data voltage Vdata is applied to a row HL of the display panel 160.

[0088] During the first time period TP1 of the initialization period of the nth sub-pixel SP(n) of pixel P in the odd column VLo of row n HLn, the first multiplexer voltage MUX1 sequentially has a low logic voltage Vl and a high logic voltage Vh, and the second multiplexer voltage MUX2 sequentially has a high logic voltage Vh and a low logic voltage Vl. The nth gate1 voltage S1(n) has a low logic voltage Vl, and the nth gate2 voltage S2(n) and the nth transmit voltage Em(n) have a high logic voltage Vh.

[0089] Therefore, during the first time period TP1, the first multiplexer transistor Tm1 is sequentially turned on and off, while the second multiplexer transistor Tm2 is sequentially turned off and on. The fifth transistor T5 and the ninth transistor T9 of the nth sub-pixel SP(n) of the odd-numbered VLo are turned on, while the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 of the nth sub-pixel SP(n) of the odd-numbered VLo are turned off. The second node voltage Vn2 of the second node N2 becomes the initial voltage Vini, and the third node voltage Vn3 of the third node N3 becomes the reference voltage Vref.

[0090] During the second time period TP2 of the sampling period of the nth sub-pixel SP(n) of pixel P in the odd column VLo of row n HLn, the first multiplexer voltage MUX1 has a low logic voltage Vl and a high logic voltage Vh in sequence, and the second multiplexer voltage MUX2 has a high logic voltage Vh and a low logic voltage Vl in sequence. The nth gate1 voltage S1(n) and the nth transmit voltage Em(n) have a high logic voltage Vh, and the nth gate2 voltage S2(n) has a low logic voltage Vl.

[0091] Therefore, during the second time period TP2, the first multiplexer transistor Tm1 is sequentially turned on and off, while the second multiplexer transistor Tm2 is sequentially turned off and on. The first transistor T1, second transistor T2, sixth transistor T6, and eighth transistor T8 of the nth sub-pixel SP(n) of the odd-numbered VLo are turned on, while the third transistor T3, fourth transistor T4, fifth transistor T5, seventh transistor T7, and ninth transistor T9 of the nth sub-pixel SP(n) of the odd-numbered VLo are turned off. The first node voltage Vn1 of the first node N1 becomes the data voltage Vdata, the second node voltage Vn2 of the second node N2 becomes the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the third node voltage Vn3 of the third node N3 remains at the reference voltage Vref.

[0092] During the third time period TP3 of the holding period of the nth sub-pixel SP(n) of pixel P in the odd column VLo of row n HLn, the first multiplexer voltage MUX1 has a low logic voltage Vl, and the second multiplexer voltage MUX2 has a high logic voltage Vh. The nth gate1 voltage S1(n), the nth gate2 voltage S2(n), and the nth transmit voltage Em(n) all have a high logic voltage Vh.

[0093] Therefore, during the third time period TP3, the first multiplexer transistor Tm1 is turned on, while the second multiplexer transistor Tm2 is turned off. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and ninth transistor T9 of the nth sub-pixel SP(n) of the odd-numbered sequence VLo are turned off. The first node voltage Vn1 of the first node N1 remains at the data voltage Vdata, the second node voltage Vn2 of the second node N2 remains at the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth), and the third node voltage Vn3 of the third node N3 remains at the reference voltage Vref.

[0094] During the fourth time period TP4 of the transmission period of the nth sub-pixel SP(n) of pixel P in the odd column VLo of row n HLn, the first multiplexer voltage MUX1 sequentially has a high logic voltage Vh and a low logic voltage Vl, and the second multiplexer voltage MUX2 sequentially has a low logic voltage Vl and a high logic voltage Vh. The nth gate1 voltage S1(n) and the nth gate2 voltage S2(n) have a high logic voltage Vh, and the nth transmit voltage Em(n) has a low logic voltage Vl.

[0095] Therefore, during the fourth time period TP4, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 of the nth sub-pixel SP(n) of the odd-numbered column VLo are turned off. The first node voltage Vn1 of the first node N1 becomes a high-level voltage Vdd, and the second node voltage Vn2 of the second node N2 becomes a value obtained by adding the difference between the high-level voltage Vdd and the reference voltage Vref (Vdd-Vref) to the sum of the data voltage Vdata and the threshold voltage Vth (Vdata+Vth) (Vdd-Vref+Vdata+Vth).

[0096] Since the current flowing in the driving transistor Td is proportional to the square of the value (-Vref+Vdata) obtained by subtracting the threshold voltage Vth from the gate-source voltage (Vgs=(Vg-Vs)=(Vdd-Vref+Vdata+Vth)-Vdd=Vdata-Vref+Vth), the changes in the high-level voltage Vdd and the threshold voltage Vth are compensated.

[0097] During the first time period TP1 of the initialization period in row n HLn, the sub-pixels SP of odd-numbered columns VLo and even-numbered columns VLe initialize the first and second electrodes of the storage capacitor Cst to the initial voltage Vini and the reference voltage Vref, respectively.

[0098] During the second time period TP2 of the sampling period of the nth row HLn, the sub-pixel SP of the odd column VLo stores the data voltage Vdata of the driving transistor Td and the threshold voltage Vth in the storage capacitor Cst according to the nth gate2 voltage S2(n).

[0099] During the sixth time period TP6, which is different from the second time period TP2, the sub-pixel SP of the even column VLe stores the data voltage Vdata of the driving transistor Td and the threshold voltage Vth in the storage capacitor Cst according to the (n-1)th gate2 voltage S2(n-1).

[0100] The left data lines DLL and DLR of all sub-pixels SP of odd-numbered pixels P and even-numbered pixels P in row n HLn are not simultaneously charged with the data voltage Vdata. Instead, the left data lines DLL and DLR of sub-pixels SP of odd-numbered pixels P and even-numbered pixels P are charged with the data voltage Vdata at different time intervals. Therefore, the coupling between the left data lines DLL and DLR and the electric field lines is reduced, the variation (ripple) of the high-level voltage Vdd of the electric field lines caused by coupling is reduced, and the distortion of the data voltage Vdata caused by the variation is reduced.

[0101] During the fifth time period TP5 of the initialization period in row (n-1) HL(n-1), the sub-pixels SP of odd-numbered columns VLo and even-numbered columns VLe initialize the first and second electrodes of the storage capacitor Cst to the initial voltage Vini and the reference voltage Vref, respectively.

[0102] During the sixth time period TP6 of the sampling period of row (n-1) HL(n-1), the sub-pixel SP of odd column VLo stores the data voltage Vdata of driving transistor Td and the threshold voltage Vth in the storage capacitor Cst according to the (n-1) gate2 voltage S2(n-1).

[0103] During the second time period TP2 of the sampling period of the nth row HLn, which is different from the sixth time period TP6, the sub-pixels SP of the even column VLe store the data voltage Vdata of the driving transistor Td and the threshold voltage Vth in the storage capacitor Cst according to the nth gate2 voltage S2(n).

[0104] The left data lines DLL and DLR of all sub-pixels SP of odd-numbered pixels P and even-numbered pixels P in row (n-1) HL(n-1) will not be charged with the data voltage Vdata simultaneously. Instead, the left data lines DLL and DLR of sub-pixels SP of odd-numbered pixels P and the left data lines DLL and DLR of sub-pixels SP of even-numbered pixels P are charged with the data voltage Vdata at different time periods. Therefore, the coupling between the left data lines DLL and DLR and the electric field lines is reduced, the variation (ripple) of the high-level voltage Vdd of the electric field lines caused by coupling is reduced, and the distortion of the data voltage Vdata caused by the variation is reduced.

[0105] The fifth time period TP5 has a width of two horizontal time periods (2H) and precedes the first time period TP1 by one horizontal time period (1H). The sixth time period TP6 has a width of two horizontal time periods (2H) and precedes the second time period TP2 by one horizontal time period (1H).

[0106] The reduction of the high-level voltage Vdd change in the OLED display device 110 will be explained with reference to the accompanying drawings.

[0107] Figure 6A This is a view showing the variation of the high-level voltage of an organic light-emitting diode display device according to a comparative example. Figure 6B This is a view showing the change of the high-level voltage of an organic light-emitting diode display device according to a first embodiment of the present disclosure.

[0108] According to Figure 6A In a comparative example of an organic light-emitting diode display device (where the sampling period is not divided by columns VL), during the sampling period (where the data voltage Vdata supplied to the odd-numbered columns VLo and even-numbered columns VLe of the next row HL changes from low to high in the rising region RA and from high to low in the falling region FA), a first voltage change RP occurs in the high-level voltage Vdd of the power lines due to the coupling of the left data line DLL and the right data line DLR with the power lines in the next row HL, and due to the change RP of the high-level voltage Vdd, distortion occurs in the floating data voltage Vdata of the left data line DLL and the right data line DLR of the current row HL.

[0109] exist Figure 6BIn the OLED display device 110 according to the first embodiment of the present disclosure, during a sampling period (where the data voltage Vdata of the odd-numbered column VLo supplied to the next row HL changes from low to high in the odd-rising region RAo and from high to low in the odd-falling region FAo) and during another sampling period (where the data voltage Vdata of the even-numbered column VLe supplied to the next row HL changes from low to high in the even-rising region RAe and from high to low in the even-falling region FAe), due to the coupling of the left data line DLL and the right data line DLR with the electric field lines in the next row HL, a change RP occurs in the high-level voltage Vdd of the electric field lines, and due to the change RP of the high-level voltage Vdd, distortion occurs in the floating data voltage Vdata of the left data line DLL and the right data line DLR of the current row HL.

[0110] Since the columns VL associated with coupling are divided into odd and even columns, the number of columns VL associated with coupling is reduced to half. Therefore, the change RP of the high-level voltage Vdd of the OLED display device 110 according to the first embodiment of this disclosure has a second voltage V2 that is smaller than the first voltage V1. (V2) <V1)

[0111] Therefore, compared to the first voltage V1 of the change RP of the high-level voltage Vdd in the comparative example, the distortion of the data voltage Vdata of the current row HL caused by the second voltage V2 of the change RP of the high-level voltage Vdd in the first embodiment is reduced.

[0112] In the OLED display device 110 according to the first embodiment of this disclosure, the gate2 line G2L and the gate2 extension line G2EL are respectively connected to the odd-numbered column VLo and the even-numbered column VLe, and the odd-numbered column VLo and the even-numbered column VLe are driven to have different sampling periods according to the gate2 voltage S2 of the current row and the gate2 voltage S2 of the adjacent row (the previous row or the next row). Therefore, the variation (ripple) of the high-level voltage Vdd is reduced, and the distortion of the data voltage Vdata is minimized, thereby reducing degradation such as crosstalk.

[0113] Furthermore, since the sampling period of the current row is driven by the gate2 voltage of the previous or next row without any additional signal, an additional gate drive unit for generating additional signals is not required. This simplifies the gate drive unit and reduces manufacturing costs.

[0114] In another implementation, the columns of pixels can be divided into odd-numbered pairs and even-numbered pairs.

[0115] Figure 7This is a view illustrating the connection of the pixel and gate voltage of an organic light-emitting diode display device according to a second embodiment of this disclosure. Descriptions of portions identical to those in the first embodiment may be omitted.

[0116] exist Figure 7 In the second embodiment of the present disclosure, the organic light-emitting diode (OLED) display device includes a gate driving unit 240, a multiplexer unit 250, and a display panel 260.

[0117] The gate driving unit 240 includes a gate1 voltage generating section 242 for generating a plurality of gate1 voltages S1 and a gate2 voltage generating section 244 for generating a plurality of gate2 voltages S2. Each of the gate1 voltage generating section 242 and the gate2 voltage generating section 244 may include a shift register.

[0118] The multiplexer unit 250 includes: a first multiplexer transistor Tm1, which switches according to a first multiplexer voltage MUX1 to transmit the data voltage Vdata of the data drive unit to one of the left data line DLL and the right data line DLR of the display panel 260; and a second multiplexer transistor Tm2, ​​which switches according to a second multiplexer voltage MUX2 to transmit the data voltage Vdata of the data drive unit to the other of the left data line DLL and the right data line DLR of the display panel 260. The first multiplexer transistor Tm1 and the second multiplexer transistor Tm2 can be positive type transistors.

[0119] The display panel 260 includes multiple pixels P. The multiple pixels P can be arranged in a matrix of multiple rows HL parallel to the horizontal direction and multiple columns VL parallel to the vertical direction. The multiple columns VL can be divided into multiple column pairs VLP.

[0120] For example, multiple pixels P may include 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6, and 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6 may be divided into a first row HL1, a second row HL2, a (n-1)th row HL(n-1) and an nth row HLn and a first column VL1 to a sixth column VL6.

[0121] The left data line DLL and the right data line DLR are respectively set in the left and right parts of each sub-pixel SP, and each sub-pixel SP is connected to one of the left data line DLL and the right data line DLR.

[0122] For example, the sub-pixels SP of odd-numbered rows HL1 and HL(n-1) can be connected to the gate line GL and the left data line DLL, while the sub-pixels SP of even-numbered rows HL2 and HLn can be connected to the gate line GL and the right data line DLR.

[0123] The gate1 line G1L, which transmits the gate1 voltage S1 of the current row, the gate2 line G2L, which transmits the gate2 voltage S2 of the current row, and the gate2 extension line G2EL, which transmits the gate2 voltage S2 of the previous or next row, are set in each of the multiple rows HL. The gate1 line G1L is connected to the sub-pixel SP of the pixel P of the column VL of each row HL, the gate2 line G2L is connected to the sub-pixel SP of the pixel P of the odd-numbered column pair VLPo of each row HL, and the gate2 extension line G2EL is connected to the sub-pixel SP of the pixel P of the even-numbered column pair VLPe of each row HL.

[0124] For example, the gate1 line G1L for transmitting the first gate1 voltage S1(1) of the current row, the gate2 line G2L for transmitting the first gate2 voltage S2(1) of the current row, and the gate2 extension line G2EL for transmitting the second gate2 voltage S2(2) of the next row are set in the first row HL1, and the gate1 line G1L for transmitting the second gate1 voltage S1(2) of the current row, the gate2 line G2L for transmitting the second gate2 voltage S2(2) of the current row, and the gate2 extension line G2EL for transmitting the first gate2 voltage S2(1) of the previous row are set in the second row HL2.

[0125] The gate1 line G1L transmitting the first gate1 voltage S1(1) of the current row is connected to the sub-pixels SP of the first column pair VLP1 to the first column pair VLP3 to the sixth column pair VL6 of the first row HL1, the gate2 line G2L transmitting the first gate2 voltage S2(1) of the current row is connected to the sub-pixels SP of the first column VL1, the second column VL2, the fifth column VL5 and the sixth column VL6 of the first column pair VLP1 and the third column pair VLP3 of the first row HL1, the gate2 extension line G2EL transmitting the second gate2 voltage S2(2) of the next row is connected to the sub-pixels SP of the first column VL3 and the fourth column VL4 of the second column pair VLP2 of the first row HL1, the gate2 extension line G2EL transmitting the second gate2 voltage S2(2) of the next row is connected to the sub-pixels SP of the first column VL3 and the fourth column VL4 of the second column pair VLP2 of the first row HL1, the gate2 extension line G2EL transmitting the second gate2 voltage S2(2) of the next row.

[0126] The gate1 line G1L transmitting the second gate1 voltage S1(2) of the current row is connected to the sub-pixels SP of the first column VL1 to the sixth column VL6 of the first column pair VLP1 to the third column pair VLP3 of the second row HL2, and the gate2 line G2L transmitting the second gate2 voltage S2(2) of the current row is connected to the sub-pixels SP of the first column VL1, the second column VL2, the fifth column VL5 and the sixth column VL6 of the first column pair VLP1 and the third column pair VLP3 of the second row HL2, and the gate2 extension line G2EL transmitting the first gate2 voltage S2(1) of the previous row is connected to the sub-pixels SP of the second column pair VLP2, the third column VL3 and the fourth column VL4 of the second row HL2, and the second-third pixel P23 and the second-fourth pixel P24 of the third column VL3 and the fourth column VL4 of the second column pair VLP2 of the previous row HL2.

[0127] Similarly, the gate1 line G1L for transmitting the (n-1)th gate1 voltage S1(n-1) of the current row, the gate2 line G2L for transmitting the (n-1)th gate2 voltage S2(n-1) of the current row, and the gate2 extension line G2EL for transmitting the nth gate2 voltage S2(n) of the next row are set in the (n-1)th row HL(n-1), and the gate1 line G1L for transmitting the nth gate1 voltage S1(n) of the current row, the gate2 line G2L for transmitting the nth gate2 voltage S2(n) of the current row, and the gate2 extension line G2EL for transmitting the (n-1)th gate2 voltage S2(n-1) of the previous row are set in the nth row HLn.

[0128] The gate1 line G1L of the (n-1)th gate1 voltage S1(n-1) of the current row is connected to the sub-pixels SP of the (n-1)th row HL(n-1) of the first column of VLP1 to the third column of VLP3, from the first column VL1 to the sixth column VL6. The gate1 line G1L of the (n-1)th gate2 voltage S2(n-1) of the current row is connected to the (n-1)th gate2 voltage S2(n-1) of the current row. The te2 line G2L connects to the sub-pixels SP of the (n-1)-1 pixels P(n-1)1, (n-1)-2 pixels P(n-1)2, (n-1)-5 pixels P(n-1)5, and (n-1)-6 pixels P(n-1)6 of the first column pair VLP1 and the third column pair VLP3 of the (n-1) row HL(n-1). The gate2 extension line G2EL of the next row's nth gate2 voltage S2(n) connects to the sub-pixels SP of the (n-1)-3 pixels P(n-1)3 and (n-1)-4 pixels P(n-1)4 of the third column pair VLP2 and the fourth column pair VL4 of the (n-1) row HL(n-1).

[0129] The gate1 line G1L transmitting the nth gate1 voltage S1(n) of the current row is connected to the sub-pixels SP of the n-1 pixels Pn1 to n-6 pixels Pn6 of the first column pair VLP1 to the third column pair VLP3 of the nth row HLn. The gate2 line G2L transmitting the nth gate2 voltage S2(n) of the current row is connected to the sub-pixels SP of the first column VL1, the second column VL2, the fifth column VL5 and the sixth column VL6 of the first column pair VLP1 and the third column pair VLP3 of the nth row HLn. The gate2 extension line G2EL transmitting the (n-1)th gate2 voltage S2(n-1) of the previous row is connected to the sub-pixels SP of the n-3 pixels Pn3 and the n-4 pixels Pn4 of the third column VL3 and the fourth column VL4 of the second column pair VLP2 of the nth row HLn.

[0130] Therefore, the gate1 voltage S1 of the current row is provided to the sub-pixels SP of the multiple pixels P in each of the multiple rows HL to perform an initialization period. Furthermore, the gate2 voltage S2 of the current row is provided to the sub-pixels SP of the pixels P in the odd-numbered columns of each of the multiple rows HL VLPo to perform a sampling period, and the gate2 voltage S2 of the previous or next row is provided to the sub-pixels SP of the pixels P in the even-numbered columns of each of the multiple rows HL VLPe to perform a sampling period.

[0131] Because the gate2 voltages S2 of different rows have different timing (e.g., the difference between two horizontal time periods (2H)), sampling periods are performed in the sub-pixels SP of the odd-column pairs VLPo and even-column pairs VLPe of each row in multiple rows HL during different intervals. Therefore, the coupling between the data lines DLL and DLR and the power lines is reduced by half, the variation (ripple) of the high-level voltage Vdd of the power lines due to coupling is reduced, and the distortion of the data voltage Vdata due to the variation is reduced.

[0132] Furthermore, since the sampling period of the current row is driven by the gate2 voltage of the previous or next row without any additional signal, an additional gate drive unit for generating additional signals is not required. This simplifies the gate drive unit and reduces manufacturing costs.

[0133] In another implementation, all rows can use the gate2 voltage of the next row to perform a sampling period.

[0134] Figure 8 This is a view showing the connection of the pixel and gate voltage of an organic light-emitting diode display device according to a third embodiment of the present disclosure.

[0135] exist Figure 8 In the present disclosure, the organic light-emitting diode (OLED) display device according to the third embodiment of the present disclosure includes a gate driving unit 340, a multiplexer unit 350, and a display panel 360.

[0136] The gate driving unit 340 includes a gate1 voltage generating section 342 that generates a plurality of gate1 voltages S1 and a gate2 voltage generating section 344 that generates a plurality of gate2 voltages S2. Each of the gate1 voltage generating section 342 and the gate2 voltage generating section 344 may include a shift register.

[0137] The multiplexer unit 350 includes: a first multiplexer transistor Tm1, which switches according to a first multiplexer voltage MUX1 to transmit the data voltage Vdata of the data drive unit to one of the left data line DLL and the right data line DLR of the display panel 360; and a second multiplexer transistor Tm2, ​​which switches according to a second multiplexer voltage MUX2 to transmit the data voltage Vdata of the data drive unit to the other of the left data line DLL and the right data line DLR of the display panel 360. The first multiplexer transistor Tm1 and the second multiplexer transistor Tm2 can be positive type transistors.

[0138] The display panel 360 includes multiple pixels P. The multiple pixels P can be arranged in a matrix of multiple rows HL parallel to the horizontal direction and multiple columns VL parallel to the vertical direction.

[0139] For example, multiple pixels P may include 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6, and 1-1 pixels P11 to 2-6 pixels P26 and (n-1)-1 pixels P(n-1)1 to n-6 pixels Pn6 may be divided into a first row HL1, a second row HL2, a (n-1)th row HL(n-1) and an nth row HLn and a first column VL1 to a sixth column VL6.

[0140] The left data line DLL and the right data line DLR are respectively set in the left and right parts of each sub-pixel SP, and each sub-pixel SP is connected to one of the left data line DLL and the right data line DLR.

[0141] For example, the sub-pixels SP of odd-numbered rows HL1 and HL(n-1) can be connected to the gate line GL and the left data line DLL, while the sub-pixels SP of even-numbered rows HL2 and HLn can be connected to the gate line GL and the right data line DLR.

[0142] The gate1 line G1L, which transmits the gate1 voltage S1 of the current row, the gate2 line G2L, which transmits the gate2 voltage S2 of the current row, and the gate2 extension line G2EL, which transmits the gate2 voltage S2 of the next row, are set in each of the multiple rows HL. The gate1 line G1L is connected to the sub-pixel SP of the pixel P of the pixel P in each column VL of each row HL, the gate2 line G2L is connected to the sub-pixel SP of the pixel P in the odd column VLo of each row HL, and the gate2 extension line G2EL is connected to the sub-pixel SP of the pixel P in the even column VLe of each row HL.

[0143] For example, the gate1 line G1L for transmitting the first gate1 voltage S1(1) of the current row, the gate2 line G2L for transmitting the first gate2 voltage S2(1) of the current row, and the gate2 extension line G2EL for transmitting the second gate2 voltage S2(2) of the next row are set in the first row HL1, and the gate1 line G1L for transmitting the second gate1 voltage S1(2) of the current row, the gate2 line G2L for transmitting the second gate2 voltage S2(2) of the current row, and the gate2 extension line G2EL for transmitting the third gate2 voltage S2(3) of the next row are set in the second row HL2.

[0144] The gate1 line G1L that transmits the first gate1 voltage S1(1) of the current row is connected to the sub-pixels SP of the first row HL1, from pixel P11 to pixel P16 (1-1). The gate2 line G2L that transmits the first gate2 voltage S2(1) of the current row is connected to the sub-pixels SP of the first row HL1, from pixel P11 (1-1), from pixel P13 (1-3), to pixel P15 (1-5). The gate2 extension line G2EL that transmits the second gate2 voltage S2(2) of the next row is connected to the sub-pixels SP of the first row HL1, from pixel P12 (1-2), from pixel P14 (1-4), to pixel P16 (1-6).

[0145] The gate1 line G1L transmitting the second gate1 voltage S1(2) of the current row is connected to the sub-pixels SP of the second row HL2, from pixel 2-1 P21 to pixel 2-6 P26. The gate2 line G2L transmitting the second gate2 voltage S2(2) of the current row is connected to the sub-pixels SP of the second row HL2, from pixel 2-1 P21, from pixel 2-3 P23 to pixel 2-5 P25. The gate2 extension line G2EL transmitting the third gate2 voltage S2(3) of the next row is connected to the sub-pixels SP of the second row HL2, from pixel 2-2 P22, from pixel 2-4 P24 to pixel 2-6 P26.

[0146] Similarly, the gate1 line G1L transmitting the (n-1)th gate1 voltage S1(n-1) of the current row, the gate2 line G2L transmitting the (n-1)th gate2 voltage S2(n-1) of the current row, and the gate2 extension line G2EL transmitting the nth gate2 voltage S2(n) of the next row are set in the (n-1)th row HL(n-1), and the gate1 line G1L transmitting the nth gate1 voltage S1(n) of the current row, the gate2 extension line G2EL transmitting the nth gate2 voltage S2(n) of the next row are set in the (n-1)th row HL(n-1), and the gate1 line G1L transmitting the nth gate1 voltage S1(n) of the current row, the gate2 extension line G2EL transmitting the nth gate2 voltage S2(n) of the next row are set in the (n-1)th row HL(n-1). The gate2 line G2L for transmitting gate2 voltage S2(n) and the gate2 extension line G2EL for transmitting the (n+1)th gate2 voltage S2(n+1) of the next row are set in the nth row HLn, and the gate1 line G1L for transmitting the (n+1)th gate1 voltage S1(n+1) of the current row, the gate2 line G2L for transmitting the (n+1)th gate2 voltage S2(n+1) of the current row and the gate2 extension line G2EL for transmitting the (n+2)th gate2 voltage S2(n+2) of the next row are set in the (n+1)th row HL(n+1).

[0147] The gate1 line G1L transmitting the (n-1)th gate1 voltage S1(n-1) of the current row is connected to the sub-pixels SP of pixels P(n-1)1 to P(n-1)6 of the (n-1)th HL(n-1) row. The gate2 line G2L transmitting the (n-1)th gate2 voltage S2(n-1) of the current row is connected to the sub-pixels SP of pixels P(n-1)1, P(n-1)3, and P(n-1)5 of the (n-1)th HL(n-1) row. The voltage transmission also transmits the voltage SP of the nth gate1 voltage of the next row. The gate2 extension line G2EL of the gate2 voltage S2(n) is connected to the sub-pixel SP of the (n-1)-2 pixel P(n-1)2, (n-1)-4 pixel P(n-1)4 and (n-1)-6 pixel P(n-1)6 of the (n-1) row HL(n-1).

[0148] The gate1 line G1L transmitting the nth gate1 voltage S1(n) of the current row is connected to the sub-pixels SP of the (n-1)th pixel Pn1 to the (n-6)th pixel Pn6 of the nth row HLn. The gate2 line G2L transmitting the nth gate2 voltage S2(n) of the current row is connected to the sub-pixels SP of the (n-1)th pixel Pn1, the (n-3)th pixel Pn3, and the (n-5)th pixel Pn5 of the nth row HLn. The gate2 extension line G2EL transmitting the (n+1)th gate2 voltage S2(n+1) of the next row is connected to the sub-pixels SP of the (n-2)th pixel Pn2, the (n-4)th pixel Pn4, and the (n-6)th pixel Pn6 of the nth row HLn.

[0149] The gate1 line G1L transmitting the (n+1)th gate1 voltage S1(n+1) of the current row is connected to the sub-pixels SP of pixels P(n+1)1 to P(n+1)6 of the (n+1)th row HL(n+1). The gate2 line G2L transmitting the (n+1)th gate2 voltage S2(n+1) of the current row is connected to the sub-pixels SP of the (n+1)th row HL(n+1) of the (n+1)th row HL(n+1). +1)1, (n+1)-3 pixels P(n+1)3 and (n+1)-5 pixels P(n+1)5 are sub-pixels SP, and the gate2 extension line G2EL of the (n+2)th gate2 voltage S2(n+2) of the next row is connected to the sub-pixels SP of the (n+1)th row HL(n+1) ...

[0150] Therefore, the gate1 voltage S1 of the current row is provided to the sub-pixels SP of multiple pixels P in each of the multiple rows HL to perform an initialization period. Furthermore, the gate2 voltage S2 of the current row is provided to the sub-pixels SP of pixels P in the odd-numbered columns VLo of each of the multiple rows HL to perform a sampling period, and the gate2 voltage S2 of the next row is provided to the sub-pixels SP of pixels P in the even-numbered columns VLe of each of the multiple rows HL to perform a sampling period.

[0151] Because the gate2 voltages S2 of different rows have different timing (e.g., a difference of one horizontal time period (1H)), sampling periods are performed in the sub-pixels SP of pixels P in the odd-numbered columns VLo and even-numbered columns VLe of each row in multiple rows HL during different intervals. Therefore, the coupling between data lines DLL and DLR and the power lines is reduced by half, the variation (ripple) of the high-level voltage Vdd of the power lines due to coupling is reduced, and the distortion of the data voltage Vdata due to the variation is reduced.

[0152] Furthermore, since the sampling period based on the gate2 voltage S2 of the next row is executed after the initialization period of the current row ends, the operational stability of the initialization period is improved.

[0153] Furthermore, since the sampling period of the current row is driven by the gate2 voltage of the previous or next row without any additional signal, no additional gate drive unit is required. This simplifies the gate drive unit and reduces manufacturing costs.

[0154] Therefore, in the OLED display device according to this disclosure, since multiple pixels in a row have different sampling periods, the number of pixels corresponding to the floating data line is reduced. Consequently, data voltage distortion caused by high-level voltage variations (ripples) is reduced, and crosstalk is minimized.

[0155] Furthermore, since the gate2 line and its extension are positioned in a single row, and the two gate2 voltages are alternately supplied to multiple pixels in that row, the gate drive unit is simplified, and the number of columns of pixels corresponding to the floating data lines is reduced. Therefore, data voltage distortion caused by variations in the high-level voltage (ripple) is reduced, and crosstalk is minimized.

[0156] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device of this disclosure without departing from the technical concept or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. An organic light-emitting diode (OLED) display device, comprising: Multiple pixels arranged in a matrix with multiple rows and multiple columns; gate1 line, the gate1 line is connected to a plurality of pixels in each of the plurality of rows and provides gate1 voltage to a plurality of pixels in each of the plurality of rows; The gate2 line connects to a plurality of pixels in a portion of the plurality of columns and provides the gate2 voltage of the current row to the plurality of pixels in the portion of the plurality of columns; The gate2 extension line extends from the adjacent row, connects to a plurality of pixels in another part of the plurality of columns, and provides the gate2 voltage of the adjacent row to the plurality of pixels in the other part of the plurality of columns; as well as Left and right data lines are provided, located in the left and right portions of multiple pixels in each of the plurality of columns. The gate1 voltage is provided to multiple pixels in each of the plurality of rows to perform an initialization phase for multiple pixels in all columns of the current row.

2. The display device according to claim 1, wherein, The gate2 line connects to multiple pixels in the odd-numbered columns of the plurality of columns, and The gate2 extension line is connected to multiple pixels in the even-numbered columns of the plurality of columns.

3. The display device according to claim 1, wherein, The plurality of rows includes the (n-1)th row and the nth row, where n is a natural number greater than 1. Specifically, the gate2 line in the (n-1)th row transmits the gate2 voltage to a portion of the plurality of pixels in the (n-1)th row, and the extended gate2 line in the (n-1)th row connects to the gate2 line in the nth row and transmits the gate2 voltage to another portion of the plurality of pixels in the (n-1)th row. Specifically, the gate2 line in the nth row transmits the gate2 voltage to a portion of the plurality of pixels in the nth row, and the gate2 extension line in the nth row is connected to the gate2 line in the (n-1)th row and transmits the gate2 voltage to another portion of the plurality of pixels in the nth row.

4. The display device according to claim 1, wherein, The plurality of rows includes the (n-1)th row, the nth row, and the (n+1)th row, where n is a natural number greater than 1. Wherein, the gate2 line of the (n-1)th row transmits the gate2 voltage of the (n-1)th row, and the extended gate2 line of the (n-1)th row transmits the gate2 voltage of the nth row, and Specifically, the gate2 line in the nth row transmits the gate2 voltage of the nth row, and the extended gate2 line in the nth row transmits the gate2 voltage of the (n+1)th row.

5. The display device according to claim 1, wherein, The gate2 line connects to multiple pixels in the odd-numbered column pairs of the plurality of columns, and The gate2 extension line is connected to multiple pixels of even-numbered column pairs in the plurality of columns.

6. The display device according to claim 1, wherein, The left data line is connected to multiple pixels in the odd-numbered rows of the plurality of rows, and The right data line is connected to multiple pixels in the even-numbered rows of the plurality of rows.

7. The display device according to claim 6 further includes a multiplexer unit connected to the left data line and the right data line. in, The multiplexer unit includes: a first multiplexer transistor connected to the left data line of the odd-numbered columns and the right data line of the even-numbered columns; and a second multiplexer transistor connected to the right data line of the odd-numbered columns and the left data line of the even-numbered columns.

8. The display device according to claim 1, wherein, Each of the plurality of pixels comprises a sub-pixel of a first to a ninth transistor, a storage capacitor, and a light-emitting diode. The first transistor, the second transistor, the sixth transistor, and the eighth transistor switch according to the gate2 voltage. Among them, the third, fourth, and seventh transistors switch according to the emitter voltage, and The fifth transistor and the ninth transistor switch according to the gate1 voltage.

9. A method for driving an organic light-emitting diode display device, comprising: Initialize multiple pixels in multiple rows based on the gate1 voltage; Sample multiple pixels of a portion of multiple columns of the current row based on the gate2 voltage of the current row; Multiple pixels of another portion of the multiple columns of the current row are sampled based on the gate2 voltage of the adjacent rows; as well as The plurality of pixels emit light according to the emission voltage. The gate1 voltage is provided to multiple pixels in each of the plurality of rows to perform an initialization phase for multiple pixels in all columns of the current row.

10. The method according to claim 9, wherein, The gate2 voltage of the current row is provided to multiple pixels in the odd-numbered columns of the plurality of columns, and In this context, the gate2 voltage of the adjacent rows is provided to multiple pixels in the even-numbered columns of the plurality of columns.

11. The method according to claim 9, wherein, The gate2 voltage of the current row is provided to multiple pixels in the odd-numbered column pairs of the plurality of columns, and In this context, the gate2 voltage of the adjacent rows is provided to multiple pixels of even-numbered column pairs in the plurality of columns.

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