Viewing angle switchable display device

Abstract

A view-switching display device includes: a timing control unit that generates image data, a data control signal, and a gate control signal; a data driving unit that generates a data signal; a gate driving unit that generates a gate signal and a first to a third transmission signal; and a display panel that includes a plurality of sub-pixels and displays an image using the gate signal and the first to third transmission signals, wherein the gate driving unit includes: a gate signal generating unit that generates a gate signal; a first transmission signal generating unit that generates a first transmission signal; and a second transmission signal generating unit and a third transmission signal generating unit that use the input and output signals of the gate signal generating unit and the input and output signals of the first transmission signal generating unit to generate the second transmission signal and the third transmission signal, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0192431, filed on December 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more particularly to a view-switching transmission signal generating unit that uses two transistors to generate view-switching transmission signals, and a view-switching display device including the view-switching transmission signal generating unit. Background Technology

[0004] Recently, with the advent of the information society, the display field has developed rapidly due to increased attention to information displays for processing and displaying large amounts of information and the growing demand for portable information media. Consequently, various thin and light flat panel display devices have been developed and have become prominent.

[0005] Among various flat panel display devices, organic light-emitting diode (OLED) displays are light-emitting devices and do not include the backlight unit used in non-light-emitting devices such as liquid crystal displays (LCDs). Therefore, OLED displays offer advantages in viewing angle, contrast ratio, and power consumption, making them suitable for a wide range of applications.

[0006] Specifically, OLED displays can be used in vehicle dashboards. In the automotive field, OLED displays with switchable viewing angles have been researched and developed, allowing drivers and passengers to selectively view images.

[0007] In OLED displays with switchable viewing angles, the wide-viewing-angle and narrow-viewing-angle LEDs of each subpixel are driven independently using a switchable viewing angle emission signal. Because a switchable viewing angle emission signal generation unit, including a shift register, is required to generate the signal, the non-display area of ​​the display panel is enlarged due to this unit, making it difficult to achieve narrow bezels. Summary of the Invention

[0008] Therefore, this disclosure relates to a view-switching transmission signal generator that substantially eliminates one or more problems caused by the aforementioned limitations and disadvantages, and a view-switching display device including the view-switching transmission signal generator.

[0009] The purpose of this disclosure is to provide a view-angle switchable transmission signal generation unit and a view-angle switchable display device including the view-angle switchable transmission signal generation unit. In the view-angle switchable display device, a view-angle switchable transmission signal is generated by using two transistors and the input and output signals of the gate signal generation unit and the transmission signal generation unit, thereby reducing the non-display area and obtaining a narrow bezel.

[0010] Another objective of this disclosure is to provide a view-angle switchable transmission signal generation unit and a view-angle switchable display device including the view-angle switchable transmission signal generation unit. In the view-angle switchable display device, the size of the gate driving unit is minimized and a narrow bezel is obtained by generating a view-angle switchable transmission signal using a first wide-viewing-angle signal, a second wide-viewing-angle signal, a first narrow-viewing-angle signal, and a second narrow-viewing-angle signal.

[0011] Further features and aspects will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the disclosure provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures particularly pointed out in the written description or description which may be derived therefrom, as well as in the claims and drawings.

[0012] To achieve these and other aspects of this disclosure, as embodied and broadly described herein, a view-switching display device includes: a timing control unit that generates image data, a data control signal, and a gate control signal; a data driving unit that generates a data signal using the image data and the data control signal; a gate driving unit that generates a gate signal and first to third transmission signals using the gate control signal; and a display panel that includes a plurality of sub-pixels and displays an image using the data signal, the gate signal, and the first to third transmission signals, wherein the gate driving unit includes: a gate signal generating unit that generates a gate signal; a first transmission signal generating unit that generates a first transmission signal; and a second transmission signal generating unit and a third transmission signal generating unit that generate the second transmission signal and the third transmission signal, respectively, using the input and output signals of the gate signal generating unit and the input and output signals of the first transmission signal generating unit.

[0013] In another aspect, a view-switching display device includes: a display panel comprising: a sub-pixel having a first light-emitting diode (LED) and a second LED, the first LED and the second LED being operated to one of an on state and an off state using a data signal, a gate signal, and a first to a third transmission signal; a semi-cylindrical lens and a semi-spherical lens corresponding to the first LED and the second LED, respectively; a data driving unit for generating the data signal; and a gate driving unit comprising: a gate signal generating unit for generating a gate signal; a first transmission signal generating unit for generating a first transmission signal; and a second transmission signal generating unit and a third transmission signal generating unit for generating the second transmission signal and the third transmission signal, respectively, using the input and output signals of the gate signal generating unit and the input and output signals of the first transmission signal generating unit.

[0014] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the inventive concept as claimed. Attached Figure Description

[0015] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate various aspects of this disclosure and, together with the specification, serve to explain the various principles of this disclosure.

[0016] In the attached diagram:

[0017] Figure 1 This is a plan view showing a view-switching display device according to a first embodiment of the present disclosure;

[0018] Figure 2 This is a cross-sectional view showing the display panel of a view-switching display device according to a first embodiment of the present disclosure;

[0019] Figure 3 This is a view showing electrodes and lenses in the pixels of a display panel of a view-switching display device according to a first embodiment of the present disclosure;

[0020] Figure 4 This is a plan view showing the pixels of the display panel of a view-switching display device according to a first embodiment of the present disclosure;

[0021] Figure 5 This is a view showing the operation of the pixels of the display panel of the view-switching display device according to the first embodiment of the present disclosure in wide-viewing-angle mode and narrow-viewing-angle mode.

[0022] Figure 6This is a circuit diagram illustrating the sub-pixels of a view-switching display device according to a first embodiment of the present disclosure;

[0023] Figure 7 This is a circuit diagram showing the gate driving unit of a view-switching display device according to a first embodiment of the present disclosure;

[0024] Figure 8 This is a view showing multiple signals used in the sub-pixel and gate driving unit of a view-switching display device according to a first embodiment of the present disclosure;

[0025] Figure 9 This is a circuit diagram illustrating a sub-pixel of a view-switching display device according to a second embodiment of the present disclosure;

[0026] Figure 10 This is a circuit diagram showing the gate driving unit of a view-switching display device according to a second embodiment of the present disclosure;

[0027] Figure 11 This is a view showing multiple signals used in the sub-pixel and gate driving unit of a view-switching display device according to a second embodiment of the present disclosure;

[0028] Figure 12 This is a circuit diagram showing the sub-pixels of a view-switching display device according to a third embodiment of the present disclosure;

[0029] Figure 13 This is a circuit diagram illustrating the gate driving unit of a view-switching display device according to a third embodiment of the present disclosure; and

[0030] Figure 14 This is a view showing multiple signals used in the sub-pixel and gate driving unit of a switchable display device according to a third embodiment of the present disclosure. Detailed Implementation

[0031] Reference will now be made in detail to various aspects of this disclosure, with example embodiments of the disclosure illustrated in the accompanying drawings.

[0032] Figure 1 This is a plan view illustrating a view-switching display device according to a first embodiment of the present disclosure. The display device may be an organic light-emitting diode (OLED) display device.

[0033] exist Figure 1 According to the first embodiment of the present disclosure, the view-switching display device 110 includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, and a display panel 150.

[0034] The timing control unit 120 uses image signals transmitted from an external system, such as a graphics card or television system, and multiple timing signals, including a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, to generate image data, data control signals, and gate control signals. The image data and data control signals are transmitted to the data drive unit 130, and the gate control signals are transmitted to the gate drive unit 140.

[0035] The data drive unit 130 uses the data control signal and image data transmitted from the timing control unit 120 to generate a data signal (data voltage), and transmits the data voltage to the data line DL of the display panel 150.

[0036] The gate driving unit 140 uses the gate control signal transmitted from the timing control unit 120 to generate a gate signal (gate voltage) and an emission signal, and applies the gate signal and emission signal to the gate line GL of the display panel 150.

[0037] The gate driving unit 140 may have an in-panel gate (GIP) type, which is formed in the non-display area NDA of the substrate of the display panel 150 having gate lines GL, data lines DL and pixels P.

[0038] Display panel 150 includes a display area DA at the center of display panel 150 and a non-display area NDA surrounding display area DA. Display panel 150 uses gate signals, transmission signals, and data signals to display images. In order to display images, display panel 150 includes multiple pixels P, multiple gate lines GL, and multiple data lines DL in display area DA.

[0039] Each of the plurality of pixels P includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, and gate line GL and data line DL intersect each other to define the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb. Each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb is connected to both gate line GL and data line DL.

[0040] When the view-switching display device 110 is an OLED display device, each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb may include multiple transistors such as switching transistors, driving transistors and sensing transistors, storage capacitors, and light-emitting diodes.

[0041] The structure and operation of the display panel 150 of the view-switching display device 110 will be described with reference to the accompanying drawings.

[0042] Figure 2This is a cross-sectional view showing the display panel of a view-switching display device according to a first embodiment of the present disclosure. Figure 3 This is a view showing electrodes and lenses in the pixels of a display panel of a view-switching display device according to a first embodiment of the present disclosure. Figure 4 This is a plan view showing the pixels of the display panel of a view-switching display device according to a first embodiment of the present disclosure, and Figure 5 This is a view showing the operation of the pixels of the display panel of the view-switching display device according to the first embodiment of the present disclosure in wide-viewing-angle mode and narrow-viewing-angle mode.

[0043] exist Figure 2 and Figure 3 In the first embodiment of the present disclosure, the display panel 150 of the view-switching display device 110 includes an array layer 152, a touch layer 154, a lens layer 156, and a polarization layer 158.

[0044] The array layer 152 includes a display area DA in which a plurality of pixels P are disposed and a non-display area NDA in which a gate driving unit 140 is disposed. The non-display area NDA surrounds the display area DA, and each of the plurality of pixels P includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb.

[0045] For example, based on the lifetime of the emissive layer, the area of ​​the green sub-pixel SPg can be larger than the area of ​​the red sub-pixel SPr but smaller than the area of ​​the blue sub-pixel SPb. Furthermore, the red sub-pixel SPr can have a quadrilateral shape, and each of the green sub-pixel SPg and the blue sub-pixel SPb can have a pentagonal shape.

[0046] Array layer 152 includes: a substrate; and a plurality of transistors T1 to T8 in each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb on the substrate. Figure 6 (of), storage capacitor Cst ( Figure 6 (of) and the first light-emitting diode D1 and the second light-emitting diode D2 ( Figure 6 Each of the first light-emitting diode D1 and the second light-emitting diode D2 may include an anode, a light-emitting layer, and a cathode sequentially disposed above the substrate.

[0047] Multiple semi-cylindrical lenses CL are provided to correspond to the first anode 162 of the first light-emitting diode D1, which is composed of red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb, and multiple hemispherical lenses SL are provided to correspond to the second anode 164 of the second light-emitting diode D2.

[0048] Therefore, a plurality of semi-cylindrical lenses CL are configured to correspond to the first opening 165a of the emluminating layer on the emluminating layer, and a plurality of hemispherical lenses SL are configured to correspond to the second opening 165b of the emluminating layer on the emluminating layer.

[0049] Each semi-cylindrical lens CL extends along the x-direction, such that a single semi-cylindrical lens CL corresponds to the first opening 165a of the adjacent red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb, and the area of ​​the semi-cylindrical lens CL can be larger than the area of ​​the first opening 165a.

[0050] For example, one semi-cylindrical lens CL can be configured as the first anode 162 of the first light-emitting diode D1 corresponding to the red sub-pixel SPr and the green sub-pixel SPg, while the other semi-cylindrical lens CL can be configured as the first anode 162 of the first light-emitting diode D1 corresponding to the blue sub-pixel SPb. The other semi-cylindrical lens CL can extend along the x-direction to the first anode 162 of the first light-emitting diode D1 of the adjacent blue sub-pixel SPb.

[0051] Therefore, a single semi-cylindrical lens CL corresponds to multiple first emitters of adjacent sub-pixels SPr, SPg, and SPb along the x-direction.

[0052] For example, a semi-cylindrical lens CL can correspond to the first emitting part of the adjacent red sub-pixel SPr and green sub-pixel SPg along the x direction, while another semi-cylindrical lens CL can correspond to the first emitting part of the adjacent blue sub-pixel SPb along the x direction.

[0053] Each hemispherical lens SL is configured to correspond to the second opening 165b, and multiple hemispherical lenses SL are disposed on the second anode 164 of the second light-emitting diode D2. The area of ​​the hemispherical lens SL can be larger than the area of ​​the second opening 165b.

[0054] Therefore, the multiple hemispherical lenses SL correspond to the second emitter of each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb.

[0055] Based on the lifetime of the emitting layer, the area of ​​the green sub-pixel SPg can be larger than the area of ​​the red sub-pixel SPr but smaller than the area of ​​the blue sub-pixel SPb. Therefore, the number of multiple hemispherical lenses SL in the green sub-pixel SPg can be greater than the number of multiple hemispherical lenses SL in the red sub-pixel SPr but smaller than the number of multiple hemispherical lenses SL in the blue sub-pixel SPb.

[0056] Spacers 280 can be provided in the regions adjacent to the first anode 162 of the blue sub-pixel SPb along the x-direction and the second anode 164 of the green sub-pixel SPg along the y-direction, and another semi-cylindrical lens CL can be provided to overlap with spacers 280.

[0057] When the light-emitting layer is formed by an evaporation process, the spacer 280 can support a fine metal mask. When the light-emitting layer is formed by a solution process, the spacer 280 can be omitted.

[0058] The touch layer 154 includes multiple transmitting electrodes and multiple receiving electrodes. Touch can be sensed from the capacitance changes between the multiple transmitting electrodes and the multiple receiving electrodes.

[0059] Lens layer 156 includes a plurality of semi-cylindrical lenses CL and a plurality of hemispherical lenses SL. The plurality of semi-cylindrical lenses CL can be configured as a first light-emitting diode D1 corresponding to each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb, and the plurality of hemispherical lenses SL can be configured as a second light-emitting diode D2 corresponding to each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb.

[0060] The polarization layer 158 may include a linear polarization layer and a delay layer. The polarization layer 158 converts the polarization state of external light incident on the display panel 150 to prevent the external light from being re-emitted to the outside.

[0061] Figure 4 The connection relationship between the contact and emitter of each sub-pixel is shown. The emitter corresponds to the anode of the light-emitting diode, and each line transmitting the signal is specified by the corresponding signal.

[0062] exist Figure 4 In this model, the red subpixel SPr and the blue subpixel SPb have the same structure as each other, and the green subpixel SPg has a structure symmetrical to each of the red subpixel SPr and the blue subpixel SPb. Two subpixels with the same structure as the red subpixel SPr and the green subpixel SPg, which are symmetrical to each other, are repeatedly arranged.

[0063] With the second transistor T2 in the red sub-pixel SPr ( Figure 6 The first contact CT1 corresponding to the drain electrode of the red sub-pixel SPr is connected to the first anode 162 in the red sub-pixel SPr, and is connected to the third transistor T3 in the red sub-pixel SPr. Figure 6The second contact CT2 corresponding to the drain electrode of the second transistor T2 in the green sub-pixel SPg is connected to the second anode 164 in the green sub-pixel SPg. The first contact CT1 corresponding to the drain electrode of the second transistor T2 in the green sub-pixel SPg is connected to the first anode 162 in the green sub-pixel SPg, and the second contact CT2 corresponding to the drain electrode of the third transistor T3 in the green sub-pixel SPg is connected to the second anode 164 in the green sub-pixel SPg. The first contact CT1 corresponding to the drain electrode of the second transistor T2 in the blue sub-pixel SPb is connected to the first anode 162 in the blue sub-pixel SPb, and the second contact CT2 corresponding to the drain electrode of the third transistor T3 in the blue sub-pixel SPb is connected to the second anode 164 in the blue sub-pixel SPb.

[0064] The first anode 162 and the second anode 164 of the red sub-pixel SPr of another pixel can be disposed between the first anode 162 and the second anode 164 in the blue sub-pixel SPb, and the first contact portion CT1 and the second contact portion CT2 of the blue sub-pixel SPb can be disposed between the first anode 162 and the second anode 164 in the blue sub-pixel SPb. Therefore, the design freedom is improved.

[0065] In another embodiment, the first anode 162 and the second anode 164 of the blue sub-pixel SPb can be disposed between the first anode 162 of the red sub-pixel SPr of another pixel and the second anode 164 of the red sub-pixel SPr of another pixel, and the first contact portion CT1 of the blue sub-pixel SPb and the first anode 162 connected to the first contact portion CT1 can be disposed between the second contact portion CT2 of the blue sub-pixel SPb and the second anode 164 connected to the second contact portion CT2.

[0066] exist Figure 5 In the wide viewing angle mode, when the display panel 150 is operated, the first light-emitting diode D1 of each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb has an ON state for emitting light, and the second light-emitting diode D2 of each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb has an OFF state for not emitting light.

[0067] Therefore, the light from the first light-emitting diode D1 is emitted from the display panel 150 through a plurality of semi-cylindrical lenses CL, and is focused in the vertical direction and diffused in the horizontal direction. Thus, the viewing angle switchable display device 110 displays an image with a narrow viewing angle in the vertical direction and a wide viewing angle in the horizontal direction.

[0068] When the display panel 150 is operated in narrow viewing angle mode, the first light-emitting diode D1 of each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb is in an off state where it does not emit light, and the second light-emitting diode D2 of each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb is in an on state where it emits light.

[0069] Therefore, the light from the second light-emitting diode D2 is emitted from the display panel 150 through multiple hemispherical lenses SL to be focused in both the vertical and horizontal directions. Thus, the viewing angle switchable display device 110 displays an image with a narrow viewing angle in both the vertical and horizontal directions.

[0070] The view-angle switchable display device 110 displays an image with a wide viewing angle in the left-right direction in wide viewing angle mode and an image with a narrow viewing angle in the left-right direction in narrow viewing angle mode. Therefore, both the driver and the passenger can view the image in wide viewing angle mode, while one of the driver and the passenger can view the image in narrow viewing angle mode.

[0071] Since the view-switching display device 110 displays an image with a narrow viewing angle along the vertical direction in both wide-view mode and narrow-view mode, it prevents the driver's line of sight from being obstructed by the image being reflected on the windshield.

[0072] The structure and operation of the sub-pixel and gate driving unit of the view-switching display device 110 will be described with reference to the accompanying drawings.

[0073] Figure 6 This is a circuit diagram illustrating the sub-pixels of a view-switching display device according to a first embodiment of the present disclosure. Figure 7 This is a circuit diagram illustrating the gate driving unit of a view-switching display device according to a first embodiment of the present disclosure, and Figure 8 This is a view showing multiple signals used in the sub-pixel and gate driving units of a switchable display device according to a first embodiment of the present disclosure.

[0074] exist Figure 6 In the first embodiment of the disclosed content, each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the display panel 150 of the view switchable display device 110 includes a first transistor T1 to an eighth transistor T8, a storage capacitor Cst, and a first light-emitting diode D1 and a second light-emitting diode D2.

[0075] For example, the first transistor T1 through the eighth transistor T8 can be positive.

[0076] The first transistor T1, which drives the transistor, is switched (on and off) according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the first transistor T1 is connected to the first electrode of the storage capacitor Cst and the drain electrode of the fourth transistor T4. The source electrode of the first transistor T1 is connected to the high-level voltage VDD, and the drain electrode of the first transistor T1 is connected to the source electrode of the fourth transistor T4, the source electrode of the second transistor T2, and the source electrode of the third transistor T3.

[0077] The second transistor T2, which emits the transistor, is switched according to the second emission signal EM2. The gate electrode of the second transistor T2 is connected to the second emission signal EM2, the source electrode of the second transistor T2 is connected to the drain electrode of the first transistor T1, the source electrode of the fourth transistor T4, and the source electrode of the third transistor T3, and the drain electrode of the second transistor T2 is connected to the source electrode of the fifth transistor T5 and the anode of the first light-emitting diode D1.

[0078] The third transistor T3 of the emitting transistor is switched according to the third emitting signal EM3. The gate electrode of the third transistor T3 is connected to the third emitting signal EM3, the source electrode of the third transistor T3 is connected to the drain electrode of the first transistor T1, the source electrode of the fourth transistor T4 and the source electrode of the second transistor T2, and the drain electrode of the third transistor T3 is connected to the source electrode of the sixth transistor T6 and the anode of the second light-emitting diode D2.

[0079] The fourth transistor T4 is switched according to the gate2 signal SCAN2. The gate electrode of the fourth transistor T4 is connected to the gate2 signal SCAN2, the source electrode of the fourth transistor T4 is connected to the drain electrode of the first transistor T1, the source electrode of the second transistor T2 and the source electrode of the third transistor T3, and the drain electrode of the fourth transistor T4 is connected to the gate electrode of the first transistor T1 and the first electrode of the storage capacitor Cst.

[0080] The fifth transistor T5 is switched according to the gate2 signal SCAN2. The gate electrode of the fifth transistor T5 is connected to the gate2 signal SCAN2, the source electrode of the fifth transistor T5 is connected to the drain electrode of the second transistor T2 and the anode of the first light-emitting diode D1, and the drain electrode of the fifth transistor T5 is connected to the drain electrode of the seventh transistor T7, the drain electrode of the sixth transistor T6 and the reference signal Vref.

[0081] The sixth transistor T6 is switched according to the gate2 signal SCAN2. The gate electrode of the sixth transistor T6 is connected to the gate2 signal SCAN2, the source electrode of the sixth transistor T6 is connected to the drain electrode of the third transistor T3 and the anode of the second light-emitting diode D2, and the drain electrode of the sixth transistor T6 is connected to the drain electrode of the seventh transistor T7, the drain electrode of the fifth transistor T5 and the reference signal Vref.

[0082] The seventh transistor T7 is switched according to the first transmit signal EM1. The gate electrode of the seventh transistor T7 is connected to the first transmit signal EM1, the source electrode of the seventh transistor T7 is connected to the second electrode of the storage capacitor Cst and the source electrode of the eighth transistor T8, and the drain electrode of the seventh transistor T7 is connected to the drain electrode of the fifth transistor T5 and the drain electrode of the sixth transistor T6.

[0083] The eighth transistor T8 of the switching transistors is switched according to the gate1 signal SCAN1. The gate electrode of the eighth transistor T8 is connected to the gate1 signal SCAN1, the source electrode of the eighth transistor T8 is connected to the second electrode of the storage capacitor Cst and the source electrode of the seventh transistor T7, and the drain electrode of the eighth transistor T8 is connected to the data signal Vdata.

[0084] The storage capacitor Cst stores the data signal Vdata and the threshold voltage Vth. The first electrode of the storage capacitor Cst is connected to the gate electrode of the first transistor T1 and the drain electrode of the fourth transistor T4, and the second electrode of the storage capacitor Cst is connected to the source electrode of the seventh transistor T7 and the source electrode of the eighth transistor T8.

[0085] A first light-emitting diode (LED) D1 is connected between a second transistor T2 and a fifth transistor T5 and a low-level voltage VSS, and emits light proportional to the current of the first transistor T1. The anode of the first LED D1 is connected to the drain electrode of the second transistor T2 and the source electrode of the fifth transistor T5, and the cathode of the first LED D1 is connected to the low-level voltage VSS. The first LED D1 is configured to correspond to a plurality of semi-cylindrical lenses CL. The first LED D1 has an on state to obtain a wide viewing angle mode in the left-right direction and an off state to obtain a narrow viewing angle mode in the left-right direction.

[0086] A second light-emitting diode (LED) D2 is connected between the third transistor T3 and the sixth transistor T6 and a low-level voltage VSS, and emits light proportional to the current of the first transistor T1. The anode of the second LED D2 is connected to the drain electrode of the third transistor T3 and the source electrode of the sixth transistor T6, and the cathode of the second LED D2 is connected to the low-level voltage VSS. The second LED D2 is configured to correspond to a plurality of hemispherical lenses SL. The second LED D2 has a conducting state to obtain a narrow viewing angle mode in the left-right direction.

[0087] exist Figure 7 In the first embodiment of the present disclosure, the gate driving unit 140 of the view-switching display device 110 includes a gate1 signal generation unit S1G, a gate2 signal generation unit S2G, a first transmission signal generation unit EG1, a second transmission signal generation unit EG2, and a third transmission signal generation unit EG3.

[0088] The gate1 signal generation unit S1G, gate2 signal generation unit S2G, first transmission signal generation unit EG1, second transmission signal generation unit EG2, and third transmission signal generation unit EG3 are connected to a horizontal pixel line of the display panel 150. The gate1 signal generation unit S1G, gate2 signal generation unit S2G, and first transmission signal generation unit EG1, having the same structure, are configured as the pre-stage and post-stage of the gate1 signal generation unit S1G, gate2 signal generation unit S2G, and first transmission signal generation unit EG1, and are cascaded together. Multiple stages of the gate1 signal generation unit S1G, gate2 signal generation unit S2G, and first transmission signal generation unit EG1 can be connected to multiple horizontal pixel lines.

[0089] For example, the gate1 signal generation unit S1G, the gate2 signal generation unit S2G, and the first transmit signal generation unit EG1 can correspond to a stage of the shift register.

[0090] Furthermore, the second and third transmit signal generation units EG2 and EG3, having the same structure, are configured as the pre-stage and post-stage of the second and third transmit signal generation units EG2 and EG3, respectively. Multiple stages of the second and third transmit signal generation units EG2 and EG3 can be connected to multiple horizontal pixel lines.

[0091] The gate1 signal generation unit S1G includes first gate1 transistors S1T1 to ninth gate1 transistors S1T9, four gate1 pass transistors S1Tp, gate1q capacitor S1Cq, and gate1qb capacitor S1Cqb. The gate1 signal generation unit S1G uses the gate1 start signal S1VST (or the previous gate1 output signal), the gate1 high signal S1VGH, the gate1 low signal S1VGL, the gate1 reset signal S1QRST, the (N-1)th gate1 clock S1CLKN-1, the (N)th gate1 clock S1CLKN, and the (N+2)th gate1 clock S1CLKN+2 to generate the gate1 output signal S1O as the gate1 signal SCAN1, and supplies the gate1 signal SCAN1 to the nth horizontal pixel line of the display panel 150.

[0092] For example, the first gate1 transistor S1T1 to the ninth gate1 transistor S1T9 and the four gate1 transmission transistors S1Tp can be positive. The gate1 start signal S1VST, the gate1 reset signal S1QRST, and the (N-1)th gate1 clock S1CLKN-1, the (N)th gate1 clock S1CLKN, and the (N+2)th gate1 clock S1CLKN+2 can be supplied by the timing control unit 120, and the gate1 high signal S1VGH and the gate1 low signal S1VGL can be supplied by the power supply unit.

[0093] The gate2 signal generation unit S2G includes first gate2 transistors S2T1 to ninth gate2 transistors S2T9, four gate2 transmission transistors S2Tp, gate2q capacitor S2Cq, and gate2qb capacitor S2Cqb. The gate2 signal generation unit S2G uses the gate2 start signal S2VST (or the previous gate2 output signal), the gate2 high signal S2VGH, the gate2 low signal S2VGL, the gate2 reset signal S2QRST, the (N-1)th gate2 clock S2CLKN-1, the (N)th gate2 clock S2CLKN, and the (N+2)th gate2 clock S2CLKN+2 to generate the gate2 output signal S2O as the gate2 signal SCAN2, and supplies the gate2 signal SCAN2 to the nth horizontal pixel line of the display panel 150.

[0094] For example, the first gate2 transistor S2T1 to the ninth gate2 transistor S2T9 and the four gate2 transmission transistors S2Tp can be positive. The gate2 start signal S2VST, the gate2 reset signal S2QRST, and the (N-1)th gate2 clock S2CLKN-1, the (N)th gate2 clock S2CLKN, and the (N+2)th gate2 clock S2CLKN+2 can be supplied by the timing control unit 120, and the gate2 high signal S2VGH and the gate2 low signal S2VGL can be supplied by the power supply unit.

[0095] The first transmit signal generation unit EG1 includes first transmit transistors ET1 to twelfth transmit transistors ET12, transmit-q capacitor ECq, transmit-qp capacitor ECqp, and transmit-qb capacitor ECqb. The first transmit signal generation unit EG1 uses a transmit start signal EVST (or a previous transmit output signal), a transmit high signal VEH, a transmit low signal VEL, a transmit reset signal ERST, a first transmit clock ECLK1, and a second transmit clock ECLK2 to generate a transmit output signal EO as a first transmit signal EM1, and supplies the first transmit signal EM1 to the nth horizontal pixel line of the display panel 150.

[0096] For example, the first emitter transistor ET1 to the twelfth emitter transistor ET12 can be positive. The emit start signal EVST, the emit reset signal ERST, and the first emit clock ECLK1 and the second emit clock ECLK2 can be supplied by the timing control unit 120, and the emit high signal VEH and the emit low signal VEL can be supplied by the power supply unit.

[0097] The second transmission signal generation unit EG2 includes a first wide-viewing-angle transistor Tw1 and a second wide-viewing-angle transistor Tw2. The second transmission signal generation unit EG2 uses the first wide-viewing-angle signal WV1 and the second wide-viewing-angle signal WV2 to generate either the first transmission signal EM1 of the transmission output signal EO of the first transmission signal generation unit EG1 or the high logic voltage Vh of the transmission high signal VEH of the first transmission signal generation unit EG1 as the second transmission signal EM2, and supplies the second transmission signal EM2 to the nth horizontal pixel line of the display panel 150.

[0098] For example, the first wide-viewing-angle transistor Tw1 and the second wide-viewing-angle transistor Tw2 can be positive. The first wide-viewing-angle signal WV1 and the second wide-viewing-angle signal WV2 can have opposite polarities and can be supplied by the timing control unit 120 or the power supply unit.

[0099] The first wide-viewing-angle transistor Tw1 is switched according to the first wide-viewing-angle signal WV1. The gate electrode of the first wide-viewing-angle transistor Tw1 is connected to the first wide-viewing-angle signal WV1, the source electrode of the first wide-viewing-angle transistor Tw1 is connected to the first transmit signal EM1, and the drain electrode of the first wide-viewing-angle transistor Tw1 is connected to the source electrode of the second wide-viewing-angle transistor Tw2.

[0100] The second wide-viewing-angle transistor Tw2 is switched according to the second wide-viewing-angle signal WV2. The gate electrode of the second wide-viewing-angle transistor Tw2 is connected to the second wide-viewing-angle signal WV2, the source electrode of the second wide-viewing-angle transistor Tw2 is connected to the drain electrode of the first wide-viewing-angle transistor Tw1, and the drain electrode of the second wide-viewing-angle transistor Tw2 is connected to the high logic voltage Vh.

[0101] The second transmitted signal EM2 is output from the connection node between the drain electrode of the first wide-viewing-angle transistor Tw1 and the source electrode of the second wide-viewing-angle transistor Tw2.

[0102] The third transmission signal generation unit EG3 includes a first narrow-view transistor Tn1 and a second narrow-view transistor Tn2. The third transmission signal generation unit EG3 uses the first narrow-view signal NV1 and the second narrow-view signal NV2 to generate either the first transmission signal EM1 of the transmission output signal EO of the first transmission signal generation unit EG1 or the high logic voltage Vh of the transmission high signal VEH of the first transmission signal generation unit EG1 as the third transmission signal EM3, and supplies the third transmission signal EM3 to the nth horizontal pixel line of the display panel 150.

[0103] For example, the first narrow-view transistor Tn1 and the second narrow-view transistor Tn2 can be positive. The first narrow-view signal NV1 and the second narrow-view signal NV2 can have opposite polarities and can be supplied by the timing control unit 120 or the power supply unit.

[0104] The first narrow-view transistor Tn1 is switched according to the first narrow-view signal NV1. The gate electrode of the first narrow-view transistor Tn1 is connected to the first narrow-view signal NV1, the source electrode of the first narrow-view transistor Tn1 is connected to the first transmit signal EM1, and the drain electrode of the first narrow-view transistor Tn1 is connected to the source electrode of the second narrow-view transistor Tn2.

[0105] The second narrow-view transistor Tn2 is switched according to the second narrow-view signal NV2. The gate electrode of the second narrow-view transistor Tn2 is connected to the second narrow-view signal NV2, the source electrode of the second narrow-view transistor Tn2 is connected to the drain electrode of the first narrow-view transistor Tn1, and the drain electrode of the second narrow-view transistor Tn2 is connected to the high logic voltage Vh.

[0106] The third transmit signal EM3 is output from the connection node between the drain electrode of the first narrow-view transistor Tn1 and the source electrode of the second narrow-view transistor Tn2.

[0107] exist Figure 8 During the first time period TP1 of the initial time period, the gate1 signal SCAN1 and the first transmit signal EM1 become low logic voltage Vl, and the gate2 signal SCAN2 becomes high logic voltage Vh. The seventh transistor T7 and the eighth transistor T8 are turned on, while the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, and the second electrode of the storage capacitor Cst becomes the reference signal Vref, thereby initializing the gate electrode of the first transistor T1.

[0108] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the first transmission signal EM1, and the second transistor T2 and the third transistor T3 are turned on.

[0109] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the transmission high signal VEH, and the second transistor T2 and the third transistor T3 are turned off.

[0110] During the second time period TP2 of the sensing period, gate1 signal SCAN1 and gate2 signal SCAN2 become low logic voltage Vl, and the first transmit signal EM1 becomes high logic voltage Vh. The fourth transistor T4, fifth transistor T5, sixth transistor T6, and eighth transistor T8 are turned on, and the seventh transistor T7 is turned off. The second electrode of the storage capacitor Cst becomes the data signal Vdata, and the first electrode of the storage capacitor Cst becomes the sum of the difference between the data signal Vdata and the reference voltage Vref (Vdata-Vref) and the threshold voltage Vth (Vdata-Vref+Vth), such that the threshold voltage Vth is stored in the storage capacitor Cst.

[0111] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the first transmission signal EM1, and the second transistor T2 and the third transistor T3 are turned off.

[0112] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the transmission high signal VEH, and the second transistor T2 and the third transistor T3 are turned off.

[0113] During the third time period TP3 of the hold period, gate1 signal SCAN1, gate2 signal SCAN2, and the first transmit signal EM1 become high logic voltage Vh. The fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 are turned off. The second electrode of the storage capacitor Cst remains at the data signal Vdata, and the first electrode of the storage capacitor Cst remains at the sum of the difference between the data signal Vdata and the reference voltage Vref (Vdata-Vref) and the threshold voltage Vth (Vdata-Vref+Vth).

[0114] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the first transmission signal EM1, and the second transistor T2 and the third transistor T3 are turned off.

[0115] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the high transmission signal VEH, and the second transistor T2 and the third transistor T3 are turned off.

[0116] During the fourth time period TP4 of the transmission phase, gate1 signal SCAN1 and gate2 signal SCAN2 become high logic voltage Vh, and the first transmission signal EM1 becomes low logic voltage Vl. The fourth transistor T4, fifth transistor T5, sixth transistor T6, and eighth transistor T8 are turned off, and the seventh transistor T7 is turned on. A current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdata-Vref+Vth-VDD)-Vth=Vdata-Vref-VDD) flows through the first transistor T1, and the first LED D1 and the second LED D2 emit light with a brightness corresponding to the current flowing through the first transistor T1, depending on the on and off states of the second transistor T2 and the third transistor T3.

[0117] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the ON state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the first transmission signal EM1, and the second transistor T2 and the third transistor T3 are turned on.

[0118] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the transmission high signal VEH, and the second transistor T2 and the third transistor T3 are turned off.

[0119] In the view-switching display device 110 according to the first embodiment of this disclosure, a first light-emitting diode D1 and a second light-emitting diode D2 emit light to display an image based on the operation of a first transistor T1 to an eighth transistor T8 and a storage capacitor Cst. Therefore, sub-pixels SP are used to compensate for changes in threshold voltage caused by degradation or usage time of the first light-emitting diode D1 and the second light-emitting diode D2, and brightness is adjusted by driving the first light-emitting diode D1 and the second light-emitting diode D2 according to a duty cycle corresponding to the emission time.

[0120] Furthermore, since the first LED D1 and the second LED D2 are driven to the on and off states respectively according to the second transmission signal EM2 and the third transmission signal EM3, a wide-viewing-angle mode and a narrow-viewing-angle mode are obtained. A wide-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the on state and driving the second LED D2 to the on or off state, and a narrow-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the off state and driving the second LED D2 to the on state.

[0121] Furthermore, the second transmission signal generating unit EG2, which generates the second transmission signal EM2 for viewing angle switching, is composed of a first wide-viewing-angle transistor Tw1 and a second wide-viewing-angle transistor Tw2, and the third transmission signal generating unit EG3, which generates the third transmission signal EM3 for viewing angle switching, is composed of a first narrow-viewing-angle transistor Tn1 and a second narrow-viewing-angle transistor Tn2. Therefore, the sizes of the second transmission signal generating unit EG2 and the third transmission signal generating unit EG3 are minimized, and the size of the gate driving unit 140 is also minimized. Thus, the area of ​​the non-display region is reduced to achieve a narrow bezel.

[0122] Figure 9 This is a circuit diagram illustrating the sub-pixels of a view-switching display device according to a second embodiment of the present disclosure. Figure 10 This is a circuit diagram illustrating the gate driving unit of a view-switching display device according to a second embodiment of the present disclosure, and Figure 11 This is a view illustrating multiple signals used in the sub-pixel and gate driving units of a switchable display device according to a second embodiment of this disclosure. Descriptions of portions of the second embodiment that are identical to those of the first embodiment will be omitted.

[0123] exist Figure 9 In the second embodiment of the present disclosure, each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the display panel of the view switchable display device includes a first transistor T1 to a twelfth transistor T12, a storage capacitor Cst, and a first light-emitting diode D1 and a second light-emitting diode D2.

[0124] For example, the first transistor T1 through the twelfth transistor T12 can be positive.

[0125] The first transistor T1 of the switching transistor is switched (turned on and turned off) according to the nth gate signal SCAN(n). The gate electrode of the first transistor T1 is connected to the nth gate signal SCAN(n), the source electrode of the first transistor T1 is connected to the data signal Vdata, and the drain electrode of the first transistor T1 is connected to the source electrode of the second transistor T2 and the source electrode of the sixth transistor T6.

[0126] The second transistor T2, which drives the transistor, is switched according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the second transistor T2 is connected to the first electrode of the storage capacitor Cst, the drain electrode of the seventh transistor T7, and the source electrode of the ninth transistor T9. The source electrode of the second transistor T2 is connected to the drain electrode of the first transistor T1 and the source electrode of the sixth transistor T6. Furthermore, the drain electrode of the second transistor T2 is connected to the source electrode of the third transistor T3 and the source electrode of the seventh transistor T7.

[0127] The third transistor T3 of the emitter transistor is switched according to the first emitter signal EM1. The gate electrode of the third transistor T3 is connected to the first emitter signal EM1, the source electrode of the third transistor T3 is connected to the drain electrode of the second transistor T2 and the source electrode of the seventh transistor T7, and the drain electrode of the third transistor T3 is connected to the source electrode of the fourth transistor T4 and the source electrode of the fifth transistor T5.

[0128] The fourth transistor T4 of the emitter transistor is switched according to the second emitter signal EM2. The gate electrode of the fourth transistor T4 is connected to the second emitter signal EM2, the source electrode of the fourth transistor T4 is connected to the drain electrode of the third transistor T3 and the source electrode of the fifth transistor T5, and the drain electrode of the fourth transistor T4 is connected to the source electrode of the eighth transistor T8 and the anode of the first light-emitting diode D1.

[0129] The fifth transistor T5 of the emitter transistor is switched according to the third emitter signal EM3. The gate electrode of the fifth transistor T5 is connected to the third emitter signal EM3, the source electrode of the fifth transistor T5 is connected to the drain electrode of the third transistor T3 and the source electrode of the fourth transistor T4, and the drain electrode of the fifth transistor T5 is connected to the anode of the second light-emitting diode D2.

[0130] The sixth transistor T6 is switched according to the first transmit signal EM1. The gate electrode of the sixth transistor T6 is connected to the first transmit signal EM1, the source electrode of the sixth transistor T6 is connected to the drain electrode of the first transistor T1 and the source electrode of the second transistor T2, and the drain electrode of the sixth transistor T6 is connected to the high-level voltage VDD and the source electrode of the tenth transistor T10.

[0131] The seventh transistor T7 is switched according to the nth gate signal SCAN(n). The gate electrode of the seventh transistor T7 is connected to the nth gate signal SCAN(n), the source electrode of the seventh transistor T7 is connected to the drain electrode of the second transistor T2 and the source electrode of the third transistor T3, and the drain electrode of the seventh transistor T7 is connected to the gate electrode of the second transistor T2, the first electrode of the storage capacitor Cst and the source electrode of the ninth transistor T9.

[0132] The eighth transistor T8 is switched according to the nth gate signal SCAN(n). The gate electrode of the eighth transistor T8 is connected to the nth gate signal SCAN(n), the source electrode of the eighth transistor T8 is connected to the drain electrode of the fourth transistor T4 and the anode of the first light-emitting diode D1, and the drain electrode of the eighth transistor T8 is connected to the drain electrode of the ninth transistor T9 and the initial signal Vini.

[0133] The ninth transistor T9 is switched according to the (n-1)th gate signal SCAN(n-1). The gate electrode of the ninth transistor T9 is connected to the (n-1)th gate signal SCAN(n-1), the source electrode of the ninth transistor T9 is connected to the first electrode of the storage capacitor Cst, the gate electrode of the second transistor T2, and the drain electrode of the seventh transistor T7, and the drain electrode of the ninth transistor T9 is connected to the drain electrode of the eighth transistor T8 and the initial signal Vini.

[0134] The tenth transistor T10 is switched according to the first transmit signal EM1. The gate electrode of the tenth transistor T10 is connected to the first transmit signal EM1, the source electrode of the tenth transistor T10 is connected to the drain electrode of the sixth transistor T6 and the high-level voltage VDD, and the drain electrode of the tenth transistor T10 is connected to the second electrode of the storage capacitor Cst, the source electrode of the eleventh transistor T11, and the source electrode of the twelfth transistor T12.

[0135] The eleventh transistor T11 is switched according to the nth gate signal SCAN(n). The gate electrode of the eleventh transistor T11 is connected to the nth gate signal SCAN(n), the source electrode of the eleventh transistor T11 is connected to the drain electrode of the tenth transistor T10, the source electrode of the twelfth transistor T12 and the second electrode of the storage capacitor Cst, and the drain electrode of the eleventh transistor T11 is connected to the reference signal Vref and the drain electrode of the twelfth transistor T12.

[0136] The twelfth transistor T12 is switched according to the (n-1)th gate signal SCAN(n-1). The gate electrode of the twelfth transistor T12 is connected to the (n-1)th gate signal SCAN(n-1), the source electrode of the twelfth transistor T12 is connected to the drain electrode of the tenth transistor T10, the source electrode of the eleventh transistor T11, and the second electrode of the storage capacitor Cst, and the drain electrode of the twelfth transistor T12 is connected to the reference signal Vref and the drain electrode of the eleventh transistor T11.

[0137] The storage capacitor Cst stores the high-level voltage VDD, the data signal Vdata, and the threshold voltage Vth. The first electrode of the storage capacitor Cst is connected to the gate electrode of the second transistor T2, the drain electrode of the seventh transistor T7, and the source electrode of the ninth transistor T9, and the second electrode of the storage capacitor Cst is connected to the drain electrode of the tenth transistor T10, the source electrode of the eleventh transistor T11, and the source electrode of the twelfth transistor T12.

[0138] A first light-emitting diode (LED) D1 is connected between a fourth transistor T4 and an eighth transistor T8 and a low-level voltage VSS, and emits light proportional to the current of a second transistor T2. The anode of the first LED D1 is connected to the drain electrode of the fourth transistor T4 and the source electrode of the eighth transistor T8, and the cathode of the first LED D1 is connected to the low-level voltage VSS. The first LED D1 is configured to correspond to a plurality of semi-cylindrical lenses CL. The first LED D1 has an on state to obtain a wide viewing angle mode in the left-right direction and an off state to obtain a narrow viewing angle mode in the left-right direction.

[0139] A second light-emitting diode (LED) D2 is connected between the fifth transistor T5 and a low-level voltage VSS, and emits light proportional to the current of the second transistor T2. The anode of the second LED D2 is connected to the drain electrode of the fifth transistor T5, and the cathode of the second LED D2 is connected to the low-level voltage VSS. The second LED D2 is configured to correspond to a plurality of hemispherical lenses SL. The second LED D2 has a conducting state to obtain a narrow viewing angle mode in the left-right direction.

[0140] exist Figure 10In the second embodiment of the present disclosure, the gate driving unit 240 of the view-switching display device includes a gate signal generation unit SG, a first transmission signal generation unit EG1, a second transmission signal generation unit EG2, and a third transmission signal generation unit EG3.

[0141] A gate signal generation unit SG, a first transmit signal generation unit EG1, a second transmit signal generation unit EG2, and a third transmit signal generation unit EG3 are connected to a horizontal pixel line of the display panel. The gate signal generation unit SG and the first transmit signal generation unit EG1, having the same structure, are configured as the pre-stage and post-stage of the gate signal generation unit SG and the first transmit signal generation unit EG1, and are cascaded together. Multiple stages of the gate signal generation unit SG and the first transmit signal generation unit EG1 can be connected to multiple horizontal pixel lines.

[0142] For example, the gate signal generation unit SG and the first transmit signal generation unit EG1 can correspond to a stage of the shift register.

[0143] Furthermore, the second and third transmit signal generation units EG2 and EG3, having the same structure, are configured as the pre-stage and post-stage of the second and third transmit signal generation units EG2 and EG3, respectively. Multiple stages of the second and third transmit signal generation units EG2 and EG3 can be connected to multiple horizontal pixel lines.

[0144] The gate signal generation unit SG includes first gate transistors ST1 to ninth gate transistors ST9, four gate transfer transistors STp, gate q capacitor SCq, and gate qb capacitor SCqb. The gate signal generation unit SG uses the gate start signal SVST (or the previous gate output signal), the gate high signal SVGH, the gate low signal SVGL, the gate reset signal SQRST, the (N-1)th gate clock SCLKN-1, the Nth gate clock SCLKN, and the (N+2)th gate clock SCLKN+2 to generate the gate output signal SO as the nth gate signal SCAN(n), and supplies the nth gate signal SCAN(n) to the nth horizontal pixel line of the display panel.

[0145] For example, the first gate transistor ST1 to the ninth gate transistor ST9 and the four gate transfer transistors STp can be positive. The gate start signal SVST, the gate reset signal SQRST, and the (N-1)th gate clock SCLKN-1, the Nth gate clock SCLKN, and the (N+2)th gate clock SCLKN+2 can be supplied by the timing control unit, and the gate high signal SVGH and the gate low signal SVGL can be supplied by the power supply unit.

[0146] The first transmit signal generation unit EG1 includes first transmit transistors ET1 to twelfth transmit transistors ET12, transmit-q capacitor ECq, transmit-qp capacitor ECqp, and transmit-qb capacitor ECqb. The first transmit signal generation unit EG1 uses a transmit start signal EVST (or a previous transmit output signal), a transmit high signal VEH, a transmit low signal VEL, a transmit reset signal ERST, and a first transmit clock ECLK1 and a second transmit clock ECLK2 to generate a transmit output signal EO as a first transmit signal EM1, and supplies the first transmit signal EM1 to the nth horizontal pixel line of the display panel.

[0147] For example, the first emitter transistor ET1 through the twelfth emitter transistor ET12 can be positive. The emit start signal EVST, the emit reset signal ERST, and the first emit clock ECLK1 and the second emit clock ECLK2 can be supplied by the timing control unit, and the emit high signal VEH and the emit low signal VEL can be supplied by the power supply unit.

[0148] The second transmission signal generation unit EG2 includes a second wide-viewing-angle transistor Tw2 and a first wide-viewing-angle transistor Tw1. The second transmission signal generation unit EG2 uses the second wide-viewing-angle signal WV2 and the first wide-viewing-angle signal WV1 to generate the low logic voltage Vl of the transmission low signal VEL of the first transmission signal generation unit EG1 or the nth gate signal SCAN(n) of the gate output signal SO of the gate signal generation unit SG as the second transmission signal EM2, and supplies the second transmission signal EM2 to the nth horizontal pixel line of the display panel.

[0149] For example, the first wide-viewing-angle transistor Tw1 and the second wide-viewing-angle transistor Tw2 can be positive. The first wide-viewing-angle signal WV1 and the second wide-viewing-angle signal WV2 can have opposite polarities and can be supplied by a timing control unit or a power supply unit.

[0150] The second wide-viewing-angle transistor Tw2 is switched according to the second wide-viewing-angle signal WV2. The gate electrode of the second wide-viewing-angle transistor Tw2 is connected to the second wide-viewing-angle signal WV2, the source electrode of the second wide-viewing-angle transistor Tw2 is connected to the nth gate signal SCAN(n), and the drain electrode of the second wide-viewing-angle transistor Tw2 is connected to the source electrode of the first wide-viewing-angle transistor Tw1.

[0151] The first wide-viewing-angle transistor Tw1 is switched according to the first wide-viewing-angle signal WV1. The gate electrode of the first wide-viewing-angle transistor Tw1 is connected to the first wide-viewing-angle signal WV1, the source electrode of the first wide-viewing-angle transistor Tw1 is connected to the drain electrode of the second wide-viewing-angle transistor Tw2, and the drain electrode of the first wide-viewing-angle transistor Tw1 is connected to the low logic voltage Vl.

[0152] The second transmitted signal EM2 is output from the connection node between the drain electrode of the second wide-view transistor Tw2 and the source electrode of the first wide-view transistor Tw1.

[0153] The third transmit signal generation unit EG3 includes a second narrow-view transistor Tn2 and a first narrow-view transistor Tn1. The third transmit signal generation unit EG3 uses the second narrow-view signal NV2 and the first narrow-view signal NV1 to generate the nth gate signal SCAN(n) of the gate output signal SO of the gate signal generation unit SG or the low logic voltage Vl of the transmit low signal VEL of the first transmit signal generation unit EG1 as the third transmit signal EM3, and supplies the third transmit signal EM3 to the nth horizontal pixel line of the display panel.

[0154] For example, the second narrow-view transistor Tn2 and the first narrow-view transistor Tn1 can be positive. The second narrow-view signal NV2 and the first narrow-view signal NV1 can have opposite polarities and can be supplied by a timing control unit or a power supply unit.

[0155] The second narrow-view transistor Tn2 is switched according to the second narrow-view signal NV2. The gate electrode of the second narrow-view transistor Tn2 is connected to the second narrow-view signal NV2, the source electrode of the second narrow-view transistor Tn2 is connected to the nth gate signal SCAN(n), and the drain electrode of the second narrow-view transistor Tn2 is connected to the source electrode of the first narrow-view transistor Tn1.

[0156] The first narrow-view transistor Tn1 is switched according to the first narrow-view signal NV1. The gate electrode of the first narrow-view transistor Tn1 is connected to the first narrow-view signal NV1, the source electrode of the first narrow-view transistor Tn1 is connected to the drain electrode of the second narrow-view transistor Tn2, and the drain electrode of the first narrow-view transistor Tn1 is connected to the low logic voltage Vl.

[0157] The third transmit signal EM3 is output from the connection node between the drain electrode of the second narrow-view transistor Tn2 and the source electrode of the first narrow-view transistor Tn1.

[0158] exist Figure 11During the first time period TP1 of the initial time period, the (n-1)th gate signal SCAN(n-1) becomes a low logic voltage Vl, and the nth gate signal SCAN(n) and the first transmit signal EM1 become a high logic voltage Vh. The ninth transistor T9 and the twelfth transistor T12 are turned on, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are turned off. The first and second electrodes of the storage capacitor Cst become the initial signal Vini and the reference signal Vref, respectively, thus initializing the first and second electrodes of the storage capacitor Cst.

[0159] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0160] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0161] During the second time period TP2 of the sensing period, the (n-1)th gate signal SCAN(n-1) and the first transmit signal EM1 become high logic voltage Vh, and the nth gate signal SCAN(n) becomes low logic voltage Vl. The third transistor T3, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, and the twelfth transistor T12 are turned off, while the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 are turned on. The second electrode of the storage capacitor Cst becomes the reference signal Vref, and the first electrode of the storage capacitor Cst becomes the sum of the data signal Vdata and the threshold voltage Vth (Vdata+Vth), such that the threshold voltage Vth is stored in the storage capacitor Cst.

[0162] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the anodes of the first LED D1 and the second LED D2 become the initial signal Vini.

[0163] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned on, causing the anodes of the first LED D1 and the second LED D2 to become the initial signal Vini.

[0164] During the third time period TP3 of the hold period, the (n-1)th gate signal SCAN(n-1), the nth gate signal SCAN(n), and the first transmit signal EM1 become high logic voltage Vh. The first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off. The second electrode of the storage capacitor Cst remains at the reference signal Vref, and the first electrode of the storage capacitor Cst remains at the sum of the data signal Vdata and the threshold voltage Vth (Vdata+Vth).

[0165] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0166] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0167] During the fourth time period TP4 of the transmission phase, the (n-1)th gate signal SCAN(n-1) and the nth gate signal SCAN(n) become high logic voltage Vh, and the first transmission signal EM1 becomes low logic voltage Vl. The first transistor T1, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned off, while the third transistor T3, the sixth transistor T6, and the tenth transistor T10 are turned on. A current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdata+Vth+VDD-Vref-VDD)-Vth=Vdata-Vref) flows through the first transistor T1, and the first light-emitting diode D1 and the second light-emitting diode D2 emit light with a brightness corresponding to the current flowing through the first transistor T1, depending on the on and off states of the fourth transistor T4 and the fifth transistor T5.

[0168] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the ON state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0169] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0170] In the view-switching display device according to the second embodiment of this disclosure, the first light-emitting diode D1 and the second light-emitting diode D2 emit light to display an image based on the operation of the first transistor T1 to the twelfth transistor T12 and the storage capacitor Cst. Therefore, sub-pixels SP are used to compensate for changes in the threshold voltage caused by the degradation or usage time of the first light-emitting diode D1 and the second light-emitting diode D2, and the brightness is adjusted by driving the first light-emitting diode D1 and the second light-emitting diode D2 according to the duty cycle corresponding to the emission time.

[0171] Furthermore, since the first LED D1 and the second LED D2 are driven to the on and off states respectively according to the second transmission signal EM2 and the third transmission signal EM3, a wide-viewing-angle mode and a narrow-viewing-angle mode are obtained. A wide-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the on state and driving the second LED D2 to the on or off state, and a narrow-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the off state and driving the second LED D2 to the on state.

[0172] Furthermore, the second transmission signal generating unit EG2, which generates the second transmission signal EM2 for viewing angle switching, is composed of a first wide-viewing-angle transistor Tw1 and a second wide-viewing-angle transistor Tw2, and the third transmission signal generating unit EG3, which generates the third transmission signal EM3 for viewing angle switching, is composed of a first narrow-viewing-angle transistor Tn1 and a second narrow-viewing-angle transistor Tn2. Therefore, the sizes of the second transmission signal generating unit EG2 and the third transmission signal generating unit EG3 are minimized, and the size of the gate driving unit 240 is also minimized. Thus, the area of ​​the non-display region is reduced to achieve a narrow bezel.

[0173] Figure 12 This is a circuit diagram illustrating the sub-pixels of a view-switching display device according to a third embodiment of the present disclosure. Figure 13 This is a circuit diagram illustrating the gate driving unit of a view-switching display device according to a third embodiment of the present disclosure, and Figure 14 This is a view illustrating multiple signals used in the sub-pixel and gate driving units of a switchable display device according to a third embodiment of this disclosure. Descriptions of portions of the third embodiment that are identical to those of the first and second embodiments will be omitted.

[0174] exist Figure 12In the third embodiment of the present disclosure, each of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the display panel of the view switchable display device includes a first transistor T1 to a ninth transistor T9, a storage capacitor Cst, and a first light-emitting diode D1 and a second light-emitting diode D2.

[0175] For example, the first transistor T1 through the ninth transistor T9 can be positive.

[0176] The first transistor T1 of the switching transistor is switched (turned on and turned off) according to the nth gate signal SCAN(n). The gate electrode of the first transistor T1 is connected to the nth gate signal SCAN(n), the source electrode of the first transistor T1 is connected to the data signal Vdata, and the drain electrode of the first transistor T1 is connected to the source electrode of the second transistor T2 and the source electrode of the sixth transistor T6.

[0177] The second transistor T2, which drives the transistor, is switched according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the second transistor T2 is connected to the first electrode of the storage capacitor Cst, the drain electrode of the seventh transistor T7, and the source electrode of the ninth transistor T9. The source electrode of the second transistor T2 is connected to the drain electrode of the first transistor T1 and the source electrode of the sixth transistor T6. Furthermore, the drain electrode of the second transistor T2 is connected to the source electrode of the third transistor T3 and the source electrode of the seventh transistor T7.

[0178] The third transistor T3 of the emitter transistor is switched according to the first emitter signal EM1. The gate electrode of the third transistor T3 is connected to the first emitter signal EM1, the source electrode of the third transistor T3 is connected to the drain electrode of the second transistor T2 and the source electrode of the seventh transistor T7, and the drain electrode of the third transistor T3 is connected to the source electrode of the fourth transistor T4 and the source electrode of the fifth transistor T5.

[0179] The fourth transistor T4 of the emitter transistor is switched according to the second emitter signal EM2. The gate electrode of the fourth transistor T4 is connected to the second emitter signal EM2, the source electrode of the fourth transistor T4 is connected to the drain electrode of the third transistor T3 and the source electrode of the fifth transistor T5, and the drain electrode of the fourth transistor T4 is connected to the source electrode of the eighth transistor T8 and the anode of the first light-emitting diode D1.

[0180] The fifth transistor T5 of the emitter transistor is switched according to the third emitter signal EM3. The gate electrode of the fifth transistor T5 is connected to the third emitter signal EM3, the source electrode of the fifth transistor T5 is connected to the drain electrode of the third transistor T3 and the source electrode of the fourth transistor T4, and the drain electrode of the fifth transistor T5 is connected to the anode of the second light-emitting diode D2.

[0181] The sixth transistor T6 is switched according to the first transmit signal EM1. The gate electrode of the sixth transistor T6 is connected to the first transmit signal EM1, the source electrode of the sixth transistor T6 is connected to the drain electrode of the first transistor T1 and the source electrode of the second transistor T2, and the drain electrode of the sixth transistor T6 is connected to the high-level voltage VDD and the second electrode of the storage capacitor Cst.

[0182] The seventh transistor T7 is switched according to the nth gate signal SCAN(n). The gate electrode of the seventh transistor T7 is connected to the nth gate signal SCAN(n), the source electrode of the seventh transistor T7 is connected to the drain electrode of the second transistor T2 and the source electrode of the third transistor T3, and the drain electrode of the seventh transistor T7 is connected to the gate electrode of the second transistor T2, the first electrode of the storage capacitor Cst and the source electrode of the ninth transistor T9.

[0183] The eighth transistor T8 is switched according to the nth gate signal SCAN(n). The gate electrode of the eighth transistor T8 is connected to the nth gate signal SCAN(n), the source electrode of the eighth transistor T8 is connected to the drain electrode of the fourth transistor T4 and the anode of the first light-emitting diode D1, and the drain electrode of the eighth transistor T8 is connected to the drain electrode of the ninth transistor T9 and the initial signal Vini.

[0184] The ninth transistor T9 is switched according to the (n-1)th gate signal SCAN(n-1). The gate electrode of the ninth transistor T9 is connected to the (n-1)th gate signal SCAN(n-1), the source electrode of the ninth transistor T9 is connected to the first electrode of the storage capacitor Cst, the gate electrode of the second transistor T2, and the drain electrode of the seventh transistor T7, and the drain electrode of the ninth transistor T9 is connected to the drain electrode of the eighth transistor T8 and the initial signal Vini.

[0185] The storage capacitor Cst stores the high-level voltage VDD, the data signal Vdata, and the threshold voltage Vth. The first electrode of the storage capacitor Cst is connected to the gate electrode of the second transistor T2, the drain electrode of the seventh transistor T7, and the source electrode of the ninth transistor T9, and the second electrode of the storage capacitor Cst is connected to the high-level voltage VDD and the drain electrode of the sixth transistor T6.

[0186] A first light-emitting diode (LED) D1 is connected between a fourth transistor T4 and an eighth transistor T8 and a low-level voltage VSS, and emits light proportional to the current of a second transistor T2. The anode of the first LED D1 is connected to the drain electrode of the fourth transistor T4 and the source electrode of the eighth transistor T8, and the cathode of the first LED D1 is connected to the low-level voltage VSS. The first LED D1 is configured to correspond to a plurality of semi-cylindrical lenses CL. The first LED D1 has an on state to obtain a wide viewing angle mode in the left-right direction and an off state to obtain a narrow viewing angle mode in the left-right direction.

[0187] A second light-emitting diode (LED) D2 is connected between the fifth transistor T5 and a low-level voltage VSS, and emits light proportional to the current of the second transistor T2. The anode of the second LED D2 is connected to the drain electrode of the fifth transistor T5, and the cathode of the second LED D2 is connected to the low-level voltage VSS. The second LED D2 is configured to correspond to a plurality of hemispherical lenses SL. The second LED D2 has a conducting state to obtain a narrow viewing angle mode in the left-right direction.

[0188] exist Figure 13 In the third embodiment of the present disclosure, the gate driving unit 340 of the view-switching display device includes a gate signal generation unit SG, a first transmission signal generation unit EG1, a second transmission signal generation unit EG2, and a third transmission signal generation unit EG3.

[0189] A gate signal generation unit SG, a first transmit signal generation unit EG1, a second transmit signal generation unit EG2, and a third transmit signal generation unit EG3 are connected to a horizontal pixel line of the display panel. The gate signal generation unit SG and the first transmit signal generation unit EG1, having the same structure, are configured as the pre-stage and post-stage of the gate signal generation unit SG and the first transmit signal generation unit EG1, and are cascaded together. Multiple stages of the gate signal generation unit SG and the first transmit signal generation unit EG1 can be connected to multiple horizontal pixel lines.

[0190] For example, the gate signal generation unit SG and the first transmit signal generation unit EG1 can correspond to a stage of the shift register.

[0191] Furthermore, the second and third transmit signal generation units EG2 and EG3, having the same structure, are configured as the pre-stage and post-stage of the second and third transmit signal generation units EG2 and EG3, respectively. Multiple stages of the second and third transmit signal generation units EG2 and EG3 can be connected to multiple horizontal pixel lines.

[0192] The gate signal generation unit SG includes first gate transistors ST1 to ninth gate transistors ST9, four gate transfer transistors STp, gate q capacitor SCq, and gate qb capacitor SCqb. The gate signal generation unit SG uses the gate start signal SVST (or the previous gate output signal), the gate high signal SVGH, the gate low signal SVGL, the gate reset signal SQRST, the (N-1)th gate clock SCLKN-1, the Nth gate clock SCLKN, and the (N+2)th gate clock SCLKN+2 to generate the gate output signal SO as the nth gate signal SCAN(n), and supplies the nth gate signal SCAN(n) to the nth horizontal pixel line of the display panel.

[0193] For example, the first gate transistor ST1 to the ninth gate transistor ST9 and the four gate transfer transistors STp can be positive. The gate start signal SVST, the gate reset signal SQRST, and the (N-1)th gate clock SCLKN-1, the Nth gate clock SCLKN, and the (N+2)th gate clock SCLKN+2 can be supplied by the timing control unit, and the gate high signal SVGH and the gate low signal SVGL can be supplied by the power supply unit.

[0194] The first transmit signal generation unit EG1 includes first transmit transistors ET1 to twelfth transmit transistors ET12, transmit-q capacitor ECq, transmit-qp capacitor ECqp, and transmit-qb capacitor ECqb. The first transmit signal generation unit EG1 uses a transmit start signal EVST (or a previous transmit output signal), a transmit high signal VEH, a transmit low signal VEL, a transmit reset signal ERST, and a first transmit clock ECLK1 and a second transmit clock ECLK2 to generate a transmit output signal EO as a first transmit signal EM1, and supplies the first transmit signal EM1 to the nth horizontal pixel line of the display panel.

[0195] For example, the first emitter transistor ET1 through the twelfth emitter transistor ET12 can be positive. The emit start signal EVST, the emit reset signal ERST, and the first emit clock ECLK1 and the second emit clock ECLK2 can be supplied by the timing control unit, and the emit high signal VEH and the emit low signal VEL can be supplied by the power supply unit.

[0196] The second transmission signal generation unit EG2 includes a second wide-viewing-angle transistor Tw2 and a first wide-viewing-angle transistor Tw1. The second transmission signal generation unit EG2 uses the second wide-viewing-angle signal WV2 and the first wide-viewing-angle signal WV1 to generate the low logic voltage Vl of the transmission low signal VEL of the first transmission signal generation unit EG1 or the nth gate signal SCAN(n) of the gate output signal SO of the gate signal generation unit SG as the second transmission signal EM2, and supplies the second transmission signal EM2 to the nth horizontal pixel line of the display panel.

[0197] For example, the first wide-viewing-angle transistor Tw1 and the second wide-viewing-angle transistor Tw2 can be positive. The first wide-viewing-angle signal WV1 and the second wide-viewing-angle signal WV2 can have opposite polarities and can be supplied by a timing control unit or a power supply unit.

[0198] The second wide-viewing-angle transistor Tw2 is switched according to the second wide-viewing-angle signal WV2. The gate electrode of the second wide-viewing-angle transistor Tw2 is connected to the second wide-viewing-angle signal WV2, the source electrode of the second wide-viewing-angle transistor Tw2 is connected to the nth gate signal SCAN(n), and the drain electrode of the second wide-viewing-angle transistor Tw2 is connected to the source electrode of the first wide-viewing-angle transistor Tw1.

[0199] The first wide-viewing-angle transistor Tw1 is switched according to the first wide-viewing-angle signal WV1. The gate electrode of the first wide-viewing-angle transistor Tw1 is connected to the first wide-viewing-angle signal WV1, the source electrode of the first wide-viewing-angle transistor Tw1 is connected to the drain electrode of the second wide-viewing-angle transistor Tw2, and the drain electrode of the first wide-viewing-angle transistor Tw1 is connected to the low logic voltage Vl.

[0200] The second transmitted signal EM2 is output from the connection node between the drain electrode of the second wide-view transistor Tw2 and the source electrode of the first wide-view transistor Tw1.

[0201] The third transmit signal generation unit EG3 includes a second narrow-view transistor Tn2 and a first narrow-view transistor Tn1. The third transmit signal generation unit EG3 uses the second narrow-view signal NV2 and the first narrow-view signal NV1 to generate the nth gate signal SCAN(n) of the gate output signal SO of the gate signal generation unit SG or the low logic voltage Vl of the transmit low signal VEL of the first transmit signal generation unit EG1 as the third transmit signal EM3, and supplies the third transmit signal EM3 to the nth horizontal pixel line of the display panel.

[0202] For example, the second narrow-view transistor Tn2 and the first narrow-view transistor Tn1 can be positive. The second narrow-view signal NV2 and the first narrow-view signal NV1 can have opposite polarities and can be supplied by a timing control unit or a power supply unit.

[0203] The second narrow-view transistor Tn2 is switched according to the second narrow-view signal NV2. The gate electrode of the second narrow-view transistor Tn2 is connected to the second narrow-view signal NV2, the source electrode of the second narrow-view transistor Tn2 is connected to the nth gate signal SCAN(n), and the drain electrode of the second narrow-view transistor Tn2 is connected to the source electrode of the first narrow-view transistor Tn1.

[0204] The first narrow-view transistor Tn1 is switched according to the first narrow-view signal NV1. The gate electrode of the first narrow-view transistor Tn1 is connected to the first narrow-view signal NV1, the source electrode of the first narrow-view transistor Tn1 is connected to the drain electrode of the second narrow-view transistor Tn2, and the drain electrode of the first narrow-view transistor Tn1 is connected to the low logic voltage Vl.

[0205] The third transmit signal EM3 is output from the connection node between the drain electrode of the second narrow-view transistor Tn2 and the source electrode of the first narrow-view transistor Tn1.

[0206] exist Figure 14 During the first time period TP1 of the initial time period, the (n-1)th gate signal SCAN(n-1) becomes a low logic voltage Vl, and the nth gate signal SCAN(n) and the first transmit signal EM1 become a high logic voltage Vh. The ninth transistor T9 is turned on, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The first and second electrodes of the storage capacitor Cst become the initial signal Vini and the high-level voltage VDD, respectively, thus initializing the first electrode of the storage capacitor Cst.

[0207] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0208] During the first time period TP1 of the initial period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0209] During the second time period TP2 of the sensing period, the (n-1)th gate signal SCAN(n-1) and the first transmit signal EM1 become high logic voltage Vh, and the nth gate signal SCAN(n) becomes low logic voltage Vl. The third transistor T3, the sixth transistor T6, and the ninth transistor T9 are turned off, and the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on. The second electrode of the storage capacitor Cst becomes high level voltage VDD, and the first electrode of the storage capacitor Cst becomes the sum of the data signal Vdata and the threshold voltage Vth (Vdata+Vth), so that the threshold voltage Vth is stored in the storage capacitor Cst.

[0210] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the anodes of the first LED D1 and the second LED D2 become the initial signal Vini.

[0211] During the second time period TP2 of the sensing period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned on, causing the anodes of the first LED D1 and the second LED D2 to become the initial signal Vini.

[0212] During the third time period TP3 of the hold period, the (n-1)th gate signal SCAN(n-1), the nth gate signal SCAN(n), and the first transmit signal EM1 become high logic voltage Vh. The first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. The second electrode of the storage capacitor Cst remains at a high level voltage VDD, and the first electrode of the storage capacitor Cst remains at the sum of the data signal Vdata and the threshold voltage Vth (Vdata+Vth).

[0213] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the on state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0214] During the third time period TP3 of the holding period, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0215] During the fourth time period TP4 of the transmission phase, the (n-1)th gate signal SCAN(n-1) and the nth gate signal SCAN(n) become high logic voltage Vh, and the first transmission signal EM1 becomes low logic voltage Vl. The first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, while the third transistor T3 and the sixth transistor T6 are turned on. A current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdata+Vth)-Vth=Vdata) flows through the first transistor T1, and the first light-emitting diode D1 and the second light-emitting diode D2 emit light with a brightness corresponding to the current flowing through the first transistor T1, depending on the on and off states of the fourth transistor T4 and the fifth transistor T5.

[0216] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the ON state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become low logic voltage Vl, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become high logic voltage Vh. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned on, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned off. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become low logic voltage Vl due to the low transmission signal VEL, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0217] During the fourth time period TP4 of the transmission phase, when the first LED D1 and the second LED D2 are in the off state, the first wide-viewing-angle signal WV1 and the first narrow-viewing-angle signal NV1 become high logic voltage Vh, and the second wide-viewing-angle signal WV2 and the second narrow-viewing-angle signal NV2 become low logic voltage Vl. The first wide-viewing-angle transistor Tw1 and the first narrow-viewing-angle transistor Tn1 are turned off, and the second wide-viewing-angle transistor Tw2 and the second narrow-viewing-angle transistor Tn2 are turned on. The second transmission signal EM2 and the third transmission signal EM3 output from the second transmission signal generation unit EG2 and the third transmission signal generation unit EG3 become high logic voltage Vh due to the nth gate signal SCAN(n), and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0218] In the view-switching display device according to the third embodiment of this disclosure, a first light-emitting diode D1 and a second light-emitting diode D2 emit light to display an image based on the operation of a first transistor T1 to a ninth transistor T9 and a storage capacitor Cst. Therefore, sub-pixels SP are used to compensate for changes in the threshold voltage caused by the degradation or usage time of the first light-emitting diode D1 and the second light-emitting diode D2, and the brightness is adjusted by driving the first light-emitting diode D1 and the second light-emitting diode D2 according to the duty cycle corresponding to the emission time.

[0219] Furthermore, since the first LED D1 and the second LED D2 are driven to the on and off states respectively according to the second transmission signal EM2 and the third transmission signal EM3, a wide-viewing-angle mode and a narrow-viewing-angle mode are obtained. A wide-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the on state and driving the second LED D2 to the on or off state, and a narrow-viewing-angle mode in the left-right direction is obtained by driving the first LED D1 to the off state and driving the second LED D2 to the on state.

[0220] Furthermore, the second transmission signal generating unit EG2, which generates the second transmission signal EM2 for viewing angle switching, is composed of a first wide-viewing-angle transistor Tw1 and a second wide-viewing-angle transistor Tw2, and the third transmission signal generating unit EG3, which generates the third transmission signal EM3 for viewing angle switching, is composed of a first narrow-viewing-angle transistor Tn1 and a second narrow-viewing-angle transistor Tn2. Therefore, the sizes of the second transmission signal generating unit EG2 and the third transmission signal generating unit EG3 are minimized, and the size of the gate driving unit 340 is also minimized. Thus, the area of ​​the non-display region is reduced to achieve a narrow bezel.

[0221] Therefore, in the view-switching display device according to the present disclosure, since the view-switching transmission signal is generated by switching the input signal and output signal of the gate signal generation unit and the transmission signal generation unit by using two transistors, the area of ​​the non-display area is reduced and a narrow bezel is obtained.

[0222] Furthermore, since the first wide-viewing-angle signal and the second wide-viewing-angle signal, as well as the first narrow-viewing-angle signal and the second narrow-viewing-angle signal, are used to generate the viewing angle switching transmission signal, the size of the gate driving unit is minimized and a narrow bezel is obtained.

[0223] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device of this disclosure without departing from the technical concept or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A view-switching display device, comprising: The timing control unit generates image data, data control signals, and gate control signals; The data driving unit generates a data signal using the image data and the data control signal; A gate driving unit that uses the gate control signal to generate a gate signal and a first transmit signal, a second transmit signal and a third transmit signal; as well as A display panel includes multiple sub-pixels and uses the data signal, the gate signal, and the first transmission signal, the second transmission signal, and the third transmission signal to display an image. The gate driving unit includes: A gate signal generation unit that generates the gate signal; A first transmission signal generating unit generates the first transmission signal; and The second and third transmission signal generation units use the input and output signals of the gate signal generation unit and the input and output signals of the first transmission signal generation unit to generate the second and third transmission signals, respectively. Each of the plurality of sub-pixels includes: a first light-emitting diode driven according to the second emission signal; and a second light-emitting diode driven according to the third emission signal. Specifically, a wide viewing angle mode is obtained by driving the first light-emitting diode to the on state and driving the second light-emitting diode to the on state or the off state, and a narrow viewing angle mode is obtained by driving the first light-emitting diode to the off state and driving the second light-emitting diode to the on state.

2. The view-switching display device according to claim 1, wherein, The display panel includes: An array layer comprising a plurality of transistors, a storage capacitor, and a first light-emitting diode and a second light-emitting diode in each of the plurality of sub-pixels; The touch layer above the array layer; A lens layer, located above the touch layer, includes a plurality of semi-cylindrical lenses corresponding to the first light-emitting diode and a plurality of hemispherical lenses corresponding to the second light-emitting diode; and A polarizing layer, which is above the lens layer and includes a linear polarizing layer and a delay layer.

3. The view-switching display device according to claim 2, wherein, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels that constitute a pixel, and The number of hemispherical lenses in the green sub-pixel is greater than the number of hemispherical lenses in the red sub-pixel but less than the number of hemispherical lenses in the blue sub-pixel.

4. The view-switching display device according to claim 2, wherein, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels that constitute a pixel, and In this configuration, the first anode of the first light-emitting diode and the second anode of the second light-emitting diode in the red sub-pixel of an adjacent pixel are positioned between the first anode of the first light-emitting diode and the second anode of the second light-emitting diode in the blue sub-pixel.

5. The view-switching display device according to claim 1, wherein, The gate signals include gate1 signal and gate2 signal. The gate signal generation unit includes a gate1 signal generation unit for generating the gate1 signal and a gate2 signal generation unit for generating the gate2 signal. The second transmission signal generation unit includes: a first wide-viewing-angle transistor, which is switched according to a first wide-viewing-angle signal and generates the first transmission signal as the second transmission signal; and a second wide-viewing-angle transistor, which is switched according to a second wide-viewing-angle signal having the opposite polarity to the first wide-viewing-angle signal and generates a high logic voltage of the input signal of the first transmission signal generation unit as the second transmission signal. The third transmission signal generation unit includes: a first narrow-view transistor, which is switched according to a first narrow-view signal and generates the first transmission signal as the third transmission signal; and a second narrow-view transistor, which is switched according to a second narrow-view signal having the opposite polarity to the first narrow-view signal and generates a high logic voltage of the input signal of the first transmission signal generation unit as the third transmission signal.

6. The view-switching display device according to claim 5, wherein, Each of the plurality of sub-pixels also includes: The first transistor is connected to a high-level voltage; The second transistor is switched and connected to the first transistor according to the second transmit signal; A third transistor is switched and connected to the first transistor according to the third transmit signal; A fourth transistor is switched and connected to the first transistor according to the gate2 signal; The fifth transistor is switched and connected to the second transistor according to the gate2 signal; The sixth transistor is switched and connected to the third transistor according to the gate2 signal; The seventh transistor is switched and connected to the reference signal according to the first transmit signal; The eighth transistor, which is switched according to the gate1 signal and connected to the data signal; and A storage capacitor is connected between the first transistor, the fourth transistor, and the eighth transistor. Wherein, the first light-emitting diode is connected between the second transistor and the low-level voltage, and The second light-emitting diode is connected between the third transistor and the low-level voltage.

7. The view-switching display device according to claim 6, wherein, During the first time period, the gate1 signal and the first transmit signal have a low logic voltage and the gate2 signal has a high logic voltage. The second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state, and high logic voltages for the first and second LEDs in the off state. During the second time period, the gate1 signal and the gate2 signal have low logic voltages, the first transmit signal has a high logic voltage, the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the on state, and the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the off state. During the third time period, the gate1 signal, the gate2 signal, and the first transmit signal have high logic voltages; the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the on state; and the second and third transmit signals have high logic voltages for the first and second LEDs in the off state. During the fourth time period, the gate1 signal and the gate2 signal have high logic voltages and the first transmit signal has a low logic voltage. The second transmit signal and the third transmit signal have low logic voltages for the first light-emitting diode and the second light-emitting diode in the on state, and the second transmit signal and the third transmit signal have high logic voltages for the first light-emitting diode and the second light-emitting diode in the off state.

8. The view-switching display device according to claim 1, wherein, The second transmit signal generation unit includes: a second wide-viewing-angle transistor, which is switched according to a second wide-viewing-angle signal and generates the gate signal as the second transmit signal; and a first wide-viewing-angle transistor, which is switched according to a first wide-viewing-angle signal having the opposite polarity to the second wide-viewing-angle signal and generates a low logic voltage of the input signal of the first transmit signal generation unit as the second transmit signal. The third transmit signal generation unit includes: a second narrow-view transistor, which is switched according to a second narrow-view signal and generates the gate signal as the third transmit signal; and a first narrow-view transistor, which is switched according to a first narrow-view signal having the opposite polarity to the second narrow-view signal and generates a low logic voltage of the input signal of the first transmit signal generation unit as the third transmit signal.

9. The view-switching display device according to claim 8, wherein, The gate signal includes the (n-1)th gate signal and the nth gate signal. Each of the plurality of sub-pixels further includes: A first transistor, which is switched according to the nth gate signal and connected to the data signal; A second transistor is connected to the first transistor; The third transistor is switched and connected to the second transistor according to the first transmit signal; A fourth transistor, which is switched and connected to the third transistor according to the second transmit signal; The fifth transistor is switched and connected to the third transistor according to the third transmit signal; A sixth transistor, which is switched and connected to the first transistor according to the first transmit signal; The seventh transistor is switched and connected to the second transistor according to the nth gate signal; The eighth transistor is switched according to the nth gate signal and connected to the fourth transistor; The ninth transistor is switched and connected to the second transistor according to the (n-1)th gate signal; The tenth transistor is switched and connected to a high-level voltage according to the first transmit signal; The eleventh transistor is switched according to the nth gate signal and connected to the reference voltage; The twelfth transistor, which is switched according to the (n-1)th gate signal and connected to the reference voltage; and A storage capacitor is connected between the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor. The first light-emitting diode is connected between the fourth transistor and the low-level voltage, and The second light-emitting diode is connected between the fifth transistor and the low-level voltage.

10. The view-switching display device according to claim 9, wherein, During the first time period, the (n-1)th gate signal has a low logic voltage and the nth gate signal and the first transmit signal have a high logic voltage; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the off state. During the second time period, the (n-1)th gate signal and the first transmit signal have a high logic voltage and the nth gate signal has a low logic voltage; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the off state. During the third time period, the (n-1)th gate signal, the nth gate signal, and the first transmit signal have high logic voltages; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the off state. During the fourth time period, the (n-1)th gate signal and the nth gate signal have high logic voltages and the first transmit signal has a low logic voltage. The second transmit signal and the third transmit signal have low logic voltages for the first light-emitting diode and the second light-emitting diode in the on state, and the second transmit signal and the third transmit signal have high logic voltages for the first light-emitting diode and the second light-emitting diode in the off state.

11. The view-switching display device according to claim 8, wherein, The gate signal includes the (n-1)th gate signal and the nth gate signal. Each of the plurality of sub-pixels further includes: A first transistor, which is switched according to the nth gate signal and connected to the data signal; A second transistor is connected to the first transistor; The third transistor is switched and connected to the second transistor according to the first transmit signal; A fourth transistor, which is switched and connected to the third transistor according to the second transmit signal; The fifth transistor is switched and connected to the third transistor according to the third transmit signal; A sixth transistor, which is switched and connected to the first transistor according to the first transmit signal; The seventh transistor is switched and connected to the second transistor according to the nth gate signal; The eighth transistor is switched according to the nth gate signal and connected to the fourth transistor; The ninth transistor, which is switched according to the (n-1)th gate signal and connected to the second transistor; and A storage capacitor is connected between the second transistor, the sixth transistor, the seventh transistor, and the ninth transistor. The first light-emitting diode is connected between the fourth transistor and the low-level voltage, and The second light-emitting diode is connected between the fifth transistor and the low-level voltage.

12. The view-switching display device according to claim 11, wherein, During the first time period, the (n-1)th gate signal has a low logic voltage and the nth gate signal and the first transmit signal have a high logic voltage; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the off state. During the second time period, the (n-1)th gate signal and the first transmit signal have a high logic voltage and the nth gate signal has a low logic voltage; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the off state. During the third time period, the (n-1)th gate signal, the nth gate signal, and the first transmit signal have high logic voltages; the second transmit signal and the third transmit signal have low logic voltages for the first and second LEDs in the on state; and the second transmit signal and the third transmit signal have high logic voltages for the first and second LEDs in the off state. During the fourth time period, the (n-1)th gate signal and the nth gate signal have high logic voltages and the first transmit signal has a low logic voltage. The second transmit signal and the third transmit signal have low logic voltages for the first light-emitting diode and the second light-emitting diode in the on state, and the second transmit signal and the third transmit signal have high logic voltages for the first light-emitting diode and the second light-emitting diode in the off state.

13. A view-switching display device, comprising: A display panel includes: a sub-pixel having a first light-emitting diode and a second light-emitting diode, wherein the first light-emitting diode and the second light-emitting diode are operated to one of an on state and an off state using a data signal, a gate signal, and a first transmission signal, a second transmission signal, and a third transmission signal; and a semi-cylindrical lens and a semi-spherical lens corresponding to the first light-emitting diode and the second light-emitting diode, respectively. The data driving unit that generates the data signal; A gate driving unit includes: a gate signal generating unit that generates the gate signal; a first transmission signal generating unit that generates the first transmission signal; and a second transmission signal generating unit and a third transmission signal generating unit, wherein the second transmission signal generating unit and the third transmission signal generating unit use the input signal and output signal of the gate signal generating unit and the input signal and output signal of the first transmission signal generating unit to generate the second transmission signal and the third transmission signal, respectively.

14. The view-switching display device according to claim 13, wherein, The gate signals include gate1 signal and gate2 signal. The gate signal generation unit includes a gate1 signal generation unit for generating the gate1 signal and a gate2 signal generation unit for generating the gate2 signal. Wherein, the second transmit signal generation unit generates one of the first transmit signal (the output signal of the first transmit signal generation unit) and the high logic voltage of the input signal of the first transmit signal generation unit as the second transmit signal, and The third transmission signal is one of the first transmission signal generated by the third transmission signal generation unit and the high logic voltage of the input signal of the first transmission signal generation unit.

15. The view-switching display device according to claim 13, wherein, The second transmit signal generation unit generates one of the gate signal of the output signal of the gate signal generation unit and the low logic voltage of the input signal of the first transmit signal generation unit as the second transmit signal, and The third transmit signal is one of the gate signal from which the gate signal generation unit generates the output signal of the gate signal generation unit and the low logic voltage of the input signal of the first transmit signal generation unit.

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