Gate driver and display device including the same

Abstract

According to an aspect of the disclosure, a gate driver and a display device are provided. The display device includes a display panel having a plurality of sub-pixels defined thereon, the sub-pixels connected to a plurality of scan lines, and a gate driver including a plurality of stages for supplying a first scan signal and a second scan signal to each of the plurality of scan lines. Each of the plurality of stages can include a first output unit for outputting the first scan signal, a second output unit for outputting the second scan signal, a logic unit connected to the first output unit and the second output unit, a low clock signal line connected to the logic unit, and a high clock signal line connected to the second output unit. Accordingly, the first scan signal and the second scan signal can be output from a single stage, such that the structure of the gate driver can become simpler.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0191658, filed on December 29, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0003] This disclosure relates to gate drivers and display devices including such gate drivers, and more particularly, to gate drivers capable of controlling n-type transistors and display devices including such gate drivers. Background Technology

[0004] Display devices used in computer monitors, televisions, mobile phones, etc., include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0005] Such display devices are finding increasing applications, including computer monitors and televisions, as well as personal portable devices. Therefore, research is underway to develop display devices with larger display areas and reduced size and weight.

[0006] Display devices can drive multiple sub-pixels using a gate driver that supplies scan signals and a data driver that supplies data voltages. The gate driver can be configured as an in-board gate (GIP), meaning the gate driver IC can be integrated into the display panel. Unfortunately, depending on the display device's driving scheme or the internal compensation method of the sub-pixels, the sub-pixel circuitry can become complex. Therefore, the components and area used for driving the sub-pixels by the gate driver may increase, making it difficult to reduce the bezel area. Summary of the Invention

[0007] One object of this disclosure is to provide a gate driver capable of outputting a first scan signal and a second scan signal, and a display device including the gate driver.

[0008] Another object of this disclosure is to provide a gate driver capable of outputting a first scan signal and a second scan signal in a single stage, and a display device including the gate driver.

[0009] Another object of this disclosure is to provide a gate driver capable of outputting a second scan signal using an existing output timing of a first scan signal, and a display device including the gate driver.

[0010] Another object of this disclosure is to provide a gate driver capable of outputting a scan signal to control an n-type transistor and a display device including the gate driver.

[0011] Another object of this disclosure is to provide a display device with a reduced bezel area by simplifying the configuration of the gate driver.

[0012] Another object of this disclosure is to provide a display device including a gate driver with a simpler structure, since a first output unit for outputting a first scan signal and a second output unit for outputting a second scan signal share a single logic unit.

[0013] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0014] According to one aspect of this disclosure, a display device is provided, comprising: a display panel having a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; and a gate driver including a plurality of stages for supplying a high-level first scan signal and a second scan signal to each of the plurality of scan lines. Each of the plurality of stages may include: a first output unit for outputting the first scan signal; a second output unit for outputting the second scan signal; a logic unit connected to the first output unit and the second output unit; a low clock signal line for outputting a low-level low clock signal and connected to the logic unit; and a high clock signal line for outputting a high-level high clock signal and connected to the second output unit. According to an exemplary embodiment of this disclosure, the first scan signal and the second scan signal can be output from a single stage, thereby simplifying the structure of the gate driver and reducing the bezel area.

[0015] According to one aspect of this disclosure, a gate driver is provided, comprising a plurality of stages, each of the plurality of stages being configured to provide a first scan signal and a second scan signal, and comprising: a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a second gate low line and a first output terminal, wherein the first scan signal is output from the first output terminal; a second transistor having a gate electrode connected to a QB node, and a source electrode and a drain electrode connected between a gate high line and the first output terminal; a third transistor having a gate electrode connected to a low clock signal line, and a source electrode and a drain electrode connected between a Q node and the first output terminal of the preceding stage of the plurality of stages; and a fourth transistor having a gate electrode connected to the Q node. The transistor comprises: a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the second transistor outputs a second scan signal; and a seventh transistor, which has a gate electrode connected to a QN node and a source electrode connected to a high clock signal line and a second output terminal, wherein the QN node is electrically connected to the QB node, wherein the first, second, third, fifth, sixth, and seventh transistors are p-type transistors, and the fourth transistor is an n-type transistor.

[0016] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0017] According to an exemplary embodiment of this disclosure, the first scan signal and the second scan signal can be output from a single stage of the gate driver.

[0018] According to an exemplary embodiment of this disclosure, the second scan signal can be output using the existing output timing of the first scan signal, making the driving method simpler.

[0019] According to an exemplary embodiment of this disclosure, a first output unit for outputting a first scan signal and a second output unit for outputting a second scan signal share a single logic unit, which simplifies the structure of the gate driver.

[0020] According to an exemplary embodiment of this disclosure, the border area can be reduced by simplifying the circuit configuration for outputting the first scan signal and the second scan signal.

[0021] According to an exemplary embodiment of this disclosure, a high-level scan signal can be output to control an n-type transistor.

[0022] The effects of this disclosure are not limited to those exemplified above, and many more effects are included in this specification. Attached Figure Description

[0023] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated herein by reference and forming part of this application, illustrate embodiments of this disclosure and, together with the description, serve to explain various principles. In the drawings:

[0024] Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0025] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0026] Figure 3 This is a block diagram of a gate driver for a display device according to an exemplary embodiment.

[0027] Figure 4 This is a circuit diagram of a stage of a display device according to an exemplary embodiment of the present disclosure.

[0028] Figure 5 This is a timing diagram of a display device stage according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0029] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0030] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0031] The component is interpreted to include the normal tolerance range, even if not explicitly stated.

[0032] When using terms such as “on top of,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0033] When an element or layer is placed "on" another element or layer, other layers or other elements may be placed directly on or between the other element.

[0034] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0035] Throughout the specification, the same reference numerals generally denote the same elements.

[0036] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0037] Features of the various embodiments of this disclosure may be partially or completely adhered to or combined with each other, and may be interlocked and operated in various technical ways, and these embodiments may be performed independently or in association with each other.

[0038] Reference will now be made in detail to embodiments of this disclosure, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals may be used throughout the drawings to refer to the same or similar parts.

[0039] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 1 Only the display panel 110, gate driver 120, data driver 130 and timing controller 140 of the various components of the display device 100 are shown.

[0041] Reference Figure 1 The display device 100 includes: a display panel 110 including a plurality of sub-pixels SP; a gate driver 120 and a data driver 130 supplying various signals to the display panel 110; and a timing controller 140 controlling the gate driver 120 and the data driver 130.

[0042] Gate driver 120 supplies scan signals to multiple scan lines SL according to multiple gate control signals GCS provided from timing controller 140. Although in Figure 1 In the example shown, a gate driver 120 is disposed on one side of the display panel 110 and spaced apart from the display panel 110, but the number and position of gate drivers are not limited thereto.

[0043] In response to a data control signal DCS from a timing controller 140, the data driver 130 converts the image data RGB input from the timing controller 140 into a data voltage using a gamma voltage. The data driver 130 can receive gamma voltages from the gamma unit, select gamma voltages corresponding to the gray levels of the image data RGB from the gamma voltages to generate data voltages, and can apply the generated data voltages to multiple data lines DL.

[0044] Timing controller 140 aligns the RGB image data input from an external source and supplies it to data driver 130. Timing controller 140 can generate a gate control signal GCS and a data control signal DCS using synchronization signals input from an external source, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. Furthermore, timing controller 140 supplies the generated gate control signal GCS and data control signal DCS to gate driver 120 and data driver 130, respectively, to control gate driver 120 and data driver 130.

[0045] Display panel 110 is an element that displays images to a user and includes multiple subpixels SP. In display panel 110, multiple scan lines SL and multiple data lines DL intersect each other, and subpixels SP are connected to scan lines SL and data lines DL.

[0046] Each of the subpixels SP is the smallest unit forming the screen, and several subpixels SP can be aggregated to form a single pixel. Each of the multiple subpixels SP includes a light-emitting element and pixel circuitry for driving the light-emitting element. Depending on the type of display panel 110, the number of light-emitting elements may vary. For example, if the display panel 110 is an organic light-emitting display panel, the light-emitting elements may be organic light-emitting elements, each of which includes an anode, an organic light-emitting layer, and a cathode. Alternatively, light-emitting diodes (LEDs) or quantum dot light-emitting diodes (QLEDs) incorporating quantum dots (QDs) may be used as the light-emitting elements.

[0047] In the following text, reference will be made to Figure 2 The sub-pixels SP of a display device 100 according to an exemplary embodiment of the present disclosure are described in detail.

[0048] Figure 2This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0049] Reference Figure 2 The sub-pixel SP includes a light-emitting element EL, a first pixel transistor PT1, a second pixel transistor PT2, a third pixel transistor PT3, a fourth pixel transistor PT4, a fifth pixel transistor PT5, a sixth pixel transistor PT6, a seventh pixel transistor PT7, a driving transistor DT, and a storage capacitor Cst. The sub-pixel SP is connected to the data line DL, multiple scan lines SL, the transmit control signal line, the first initialization line, the second initialization line, the anode reset line, the high-potential power voltage line, and the low-potential power voltage line.

[0050] In the following description, it is assumed that the subpixel SP is set in the nth row.

[0051] Subpixel SP comprises multiple transistors. These transistors can be implemented as different types of transistors. One of the transistors can be a transistor that uses oxide semiconductor or low-temperature polycrystalline oxide (LTPO) as its active layer. Oxide semiconductor materials are suitable for switching transistors with short on-time and long off-time due to their low turn-off current. For example, in a set of multiple transistors, the first pixel transistor PT1 and the second pixel transistor PT2 can both be transistors using oxide semiconductor or LTPO as their active layer.

[0052] Specifically, in order to drive the display device 100 at a low speed, some of the transistors in the sub-pixel SP can be implemented as oxide semiconductor transistors. Since the length of a frame in low-speed driving is longer than the length of a frame in high-speed driving, it is important to maintain a constant voltage at each node of the sub-pixel SP. Oxide semiconductor transistors have very low turn-off current, which is beneficial for maintaining the voltage at each node until the next frame. Therefore, switching transistors such as the first pixel transistor PT1 and the second pixel transistor PT2 can be implemented as oxide semiconductor transistors to easily maintain the voltage at each node of the sub-pixel SP.

[0053] Another of the multiple transistors can be a transistor that uses low-temperature polycrystalline silicon (LTP) as the active layer. Due to the high mobility, low power consumption, and excellent reliability of polycrystalline silicon, it is suitable for driving transistors such as DT.

[0054] Incidentally, multiple transistors can be either n-type or p-type transistors. In an n-type transistor, electrons are the charge carriers, so electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a p-type transistor, holes are the charge carriers, so holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. One of the multiple transistors can be an n-type transistor, and another of the multiple transistors can be a p-type transistor.

[0055] For example, the first pixel transistor PT1 and the second pixel transistor PT2 can be n-type transistors and transistors using oxide semiconductor as the active layer. The fifth pixel transistor PT5 can be an n-type transistor and a transistor including cryogenic polysilicon as the active layer. Furthermore, the driving transistor DT, the third pixel transistor PT3, the fourth pixel transistor PT4, the sixth pixel transistor PT6, and the seventh pixel transistor PT7 can be p-type transistors and can be transistors including cryogenic polysilicon as the active layer. However, the materials of the active layers forming the multiple transistors and the types of multiple transistors are illustrative only and not limiting.

[0056] The first pixel transistor PT1 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first pixel transistor PT1 is connected to the first scan line SL1(n) of the nth row, and the source electrode and drain electrode are connected between the first node N1 and the third node N3. The first pixel transistor PT1 can connect the first node N1 and the third node N3 based on the first scan signal SCAN1(n) of the first scan line SL1(n) in the nth row.

[0057] The second pixel transistor PT2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second pixel transistor PT2 is connected to the second scan line SL2(n) of the nth row, and the source and drain electrodes are connected between the second node N2 and the data line DL. The second pixel transistor PT2 can transmit the data voltage Vdata from the data line DL to the second node N2 based on the second scan signal SCAN2(n) of the second scan line SL2(n) in the nth row.

[0058] The third pixel transistor PT3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third pixel transistor PT3 is connected to the emitter control signal line in the nth row, and the source and drain electrodes are connected between the high-potential power line and the second node N2. The third pixel transistor PT3 can transmit the high-potential power voltage VDD to the second node N2 based on the emitter control signal EM(n) from the emitter control signal line in the nth row.

[0059] The fourth pixel transistor PT4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth pixel transistor PT4 is connected to the emitter control signal line in the nth row, and the source and drain electrodes are connected between the third node N3 and the fourth node N4. The fourth pixel transistor PT4 can transfer drive current from the driving transistor DT to the light-emitting element EL based on the emitter control signal EM(n) from the emitter control signal line in the nth row.

[0060] The fifth pixel transistor PT5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth pixel transistor PT5 is connected to the first scan line SL1(n-2) in the (n-2)th row, and the source and drain electrodes are connected between the first initialization line and the storage capacitor Cst, and between the first initialization line and the first node N1. The fifth pixel transistor PT5 can transmit the first initialization voltage Vini1 of the first initialization line to the storage capacitor Cst and the first node N1 based on the first scan signal SCAN1(n-2) of the first scan line SL1(n-2) in the (n-2)th row.

[0061] The sixth pixel transistor PT6 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of PT6 is connected to the third scan line SL3(n) in the nth row, and the source and drain electrodes are connected between the anode reset line and the fourth node N4. PT6 can transmit the anode reset voltage VAR of the anode reset line to the fourth node N4 based on the third scan signal SCAN3(n) of the third scan line SL3(n) in the nth row. Therefore, when PT6 is turned on, the anode of the light-emitting element EL and the fourth node N4 can be initialized to the anode reset voltage VAR.

[0062] The seventh pixel transistor PT7 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the seventh pixel transistor PT7 is connected to the third scan line SL3(n) of the nth row, and the source and drain electrodes are connected between the second node N2 and the second initialization line. The seventh pixel transistor PT7 can transmit the second initialization voltage Vini2 of the second initialization line to the second node N2 based on the third scan signal SCAN3(n) of the third scan line SL3(n) in the nth row. At this time, the second initialization voltage Vini2 can be the on-bias stress voltage used to apply on-bias stress.

[0063] By applying conduction bias stress, transistor hysteresis can be mitigated. Transistors may exhibit hysteresis, where their characteristics change in the current frame depending on their operating state in the previous frame. For example, even when the same data voltage Vdata is supplied to the driving transistor DT, different levels of drive current may be generated depending on the operating state in the previous frame. Therefore, by applying conduction bias stress to multiple transistors, the characteristics of the transistors, i.e., their threshold voltages, can be initialized to a specific state. For example, the same conduction bias stress can be applied to each of multiple sub-pixels SP, such that the specific transistors of each of the multiple sub-pixels SP can be initialized to the same state. Thus, all sub-pixels SP can emit light of the same brightness in subsequent frames.

[0064] The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the first node N1, and the source and drain electrodes are connected between the second node N2 and the third node N3. When the driving transistor DT is turned on, a driving current is supplied to the light-emitting element EL, enabling the light-emitting element EL to emit light.

[0065] The storage capacitor Cst comprises multiple capacitor electrodes. Some of the capacitor electrodes are connected to a high-potential power line, while the other capacitor electrodes are connected to a first node N1. The storage capacitor Cst stores the voltage between the high-potential power voltage VDD and the voltage at the gate electrode of the driving transistor DT, thereby maintaining the drive current from the driving transistor DT when the light-emitting element EL emits light.

[0066] The light-emitting element EL includes an anode and a cathode. The anode of the light-emitting element EL is connected to the fourth node N4, and its cathode is connected to the low-potential power line from which a low-potential power voltage VSS is applied. The light-emitting element EL can emit light proportionally to the drive current from the driving transistor DT.

[0067] Incidentally, when switching transistors such as the first pixel transistor PT1 and the second pixel transistor PT2 are turned off, the voltage at nearby nodes may be distorted, causing backlash, meaning the brightness cannot reach the target value. For example, when the second pixel transistor PT2, connected between the source electrode of the driving transistor DT and the data line DL, is implemented as a p-type transistor, the data voltage Vdata may decrease due to backlash, making it difficult to output the target brightness. Furthermore, when driving the display device 100 in high-temperature or low-temperature environments, the distortion of the data voltage Vdata due to backlash may become more severe, potentially preventing the proper display of low-grayscale images.

[0068] In view of the above, in the display device 100 according to an exemplary embodiment of the present disclosure, the second pixel transistor PT2, connected between the source electrode of the driving transistor DT and the data line DL, is implemented as an n-type transistor, so that the data voltage Vdata can increase when a backlash occurs. The data voltage Vdata has a positive value, and brightness fluctuations may become more severe when the data voltage Vdata decreases rather than increases. When the second pixel transistor PT2 is changed to an n-type transistor, the data voltage Vdata increases even when a backlash occurs, resulting in greater improvement in brightness fluctuations compared to when a p-type transistor is used.

[0069] However, when the second pixel transistor PT2 is changed to an n-type transistor, the second scan signal SCAN2 output from the second scan line SL2 changes from a low level to a high level. Therefore, in the display device 100 according to an exemplary embodiment of this disclosure, in the configuration of the gate driver 120, some elements are added to the existing stage for outputting the first scan signal SCAN1 using the first scan line SL1, such that a single stage is formed for outputting the first scan signal SCAN1 and the second scan signal SCAN2 at high levels using the first scan line SL1 and the second scan line SL2, respectively. In this way, in the display device 100 according to an exemplary embodiment of this disclosure, in the process of changing the second scan signal SCAN2 from a low level to a high level, the existing stage can be used without adding a new stage, thus simplifying the gate driver 120.

[0070] In the following text, reference will be made to Figures 3 to 5 Describe gate driver 120.

[0071] Figure 3 This is a block diagram of a gate driver for a display device according to an exemplary embodiment. Figure 4 This is a circuit diagram of a stage of a display device according to an exemplary embodiment of the present disclosure. Figure 5 This is a timing diagram of a display device stage according to an exemplary embodiment of the present disclosure.

[0072] Reference Figure 3 The gate driver 120 includes multiple ST stages, high clock signal lines, and low clock signal lines.

[0073] Multiple ST stages generate a first scan signal SCAN1 and a second scan signal SCAN2. A single ST stage can be connected to a first scan line SL1 and a second scan line SL2 to output the first scan signal SCAN1 and the second scan signal SCAN2.

[0074] Stages ST are cascaded. For example, stages ST can be connected to each other, and one of the multiple stages ST can generate a scan signal based on the first scan signal SCAN1 output from the previous stage ST. Since the topmost stage ST (1) has no previous stage ST, it can receive a separate start signal VST to generate the first scan signal SCAN1 and the second scan signal SCAN2.

[0075] The clock signal lines include: low clock signal lines, which include a first low clock signal line and a second low clock signal line; and high clock signal lines, which include a first high clock signal line and a second high clock signal line. The low clock signal lines can be connected to logic unit 121 of stage ST, and the high clock signal lines can be connected to the second output unit 123 of stage ST. (See below for further details.) Figure 4 To describe it in more detail.

[0076] The first low clock signal line and the second low clock signal line are used to output a low-level clock signal. The first low clock signal LCLK1 of the first low clock signal line and the second low clock signal LCLK2 of the second low clock signal line can be output alternately.

[0077] The first and second high clock signal lines are used to output high-level clock signals. The first high clock signal HCLK1 of the first high clock signal line and the second high clock signal HCLK2 of the second high clock signal line can be output alternately.

[0078] Furthermore, odd-numbered stage STs in the plurality of stage STs are connected to the first low clock signal line and the first high clock signal line. Even-numbered stage STs in the plurality of stage STs are connected to the second low clock signal line and the second high clock signal line. For example, the first low clock signal LCLK1 and the first high clock signal HCLK1 can be input to stage ST(n) in the nth row, and the second low clock signal LCLK2 and the second high clock signal HCLK2 can be input to stage ST(n+1) in the (n+1)th row.

[0079] In the following text, among the multiple stages ST, the stage ST(n) in the nth row to which the first low clock signal LCLK1 and the first high clock signal HCLK1 are input will be described as an example of the stage ST of the gate driver 120 of the display device 100 according to an exemplary embodiment.

[0080] Reference Figure 4The stage ST(n) includes a logic unit 121, a first output unit 122, and a second output unit 123. The logic unit 121 outputs a voltage to drive the first output unit 122 and the second output unit 123. The first output unit 121 can output a first scan signal SCAN1(n) to a first scan line SL1(n) based on the voltage output from the logic unit 121. The second output unit 123 can output a second scan signal SCAN2(n) to a second scan line SL2(n) based on the first scan signal SCAN1(n) output from the first output unit 122 and the voltage output from the logic unit 121.

[0081] Stage ST(n) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first auxiliary transistor Ta1, a second auxiliary transistor Ta2, a first capacitor CQ, and a second capacitor CQN. The first transistor T1, the second transistor T2, and the first capacitor CQ may be included in the first output unit 122. The third transistor T3, the fourth transistor T4, the fifth transistor T5, and the first auxiliary transistor Ta1 may be included in the logic unit 121. The sixth transistor T6, the seventh transistor T7, the second auxiliary transistor Ta2, and the second capacitor CQN may be included in the second output unit 123.

[0082] In the following description, only the fourth transistor T4 of the plurality of transistors in stage ST(n) is an n-type oxide semiconductor transistor, while the other transistors are p-type low-temperature polysilicon transistors. However, it should be understood that this disclosure is not limited thereto.

[0083] The first transistor T1 of the first output unit 122 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 is connected to the Q node, and its source and drain electrodes are connected between a second gate low line from which it outputs a second gate low voltage VGL2 and a first output terminal from which it outputs a first scan signal SCAN1(n). The first transistor T1 can be turned on when it is not outputting the first scan signal SCAN1(n) to transmit the second gate low voltage VGL2 to the first output terminal.

[0084] The second transistor T2 of the first output unit 122 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second transistor T2 is connected to the QB node, and its source and drain electrodes are connected between the gate high line from its output gate high voltage VGH and the first output terminal. The second transistor T2 can be turned on by the voltage at the QB node to transmit the gate high voltage VGH to the first output terminal, and the gate high voltage VGH can be output as a first scan signal SCAN1(n).

[0085] The first capacitor CQ of the first output unit 122 is connected between the Q node and the first output terminal. The first capacitor CQ can store the voltage at the Q node. When the first scan signal SCAN1(n) is output, the voltage associated with the high-level first scan signal SCAN1(n-1) output from the previous stage ST(n-1) can be stored at the first capacitor CQ, so that the first transistor T1 can remain off.

[0086] The third transistor T3 of logic unit 121 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 is connected to a first low clock signal line, and the source and drain electrodes are connected between the first output terminal of the previous stage ST(n-1) and the Q2 node. The third transistor T3 can be turned on by the first low clock signal LCLK1, and can transmit the first scan signal SCAN1(n-1) output from the previous stage ST(n-1) to the Q2 node and the Q node.

[0087] Furthermore, for another stage ST connected to the second low clock signal line instead of the first low clock signal line, such as stage ST in row (n+1), the third transistor T3 can be turned on by the second low clock signal LCLK2.

[0088] The fourth transistor T4 of logic unit 121 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth transistor T4 is connected to the Q node, and its source and drain electrodes are connected between the second gate low line from which it outputs the second gate low voltage VGL2 and the QB node. When the first scan signal SCAN1(n) is output, the fourth transistor T4 can transmit the second gate low voltage VGL2 to the QB node to keep the second transistor T2 in the on state.

[0089] The fifth transistor T5 of logic unit 121 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth transistor T5 is connected to the Q2 node, and its source and drain electrodes are connected to the gate high line and the QB node. When the first scan signal SCAN1(n) is not output, the fifth transistor T5 can transmit the gate high voltage VGH to the QB node to turn off the second transistor T2, and can prevent the gate high voltage VGH from being transmitted to the first output terminal.

[0090] The first auxiliary transistor Ta1 of logic unit 121 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first auxiliary transistor Ta1 is connected to a first gate low line from which it outputs a first gate low voltage VGL1, and the source and drain electrodes are connected between node Q2 and node Q. The first auxiliary transistor Ta1 may have a gate electrode connected to the first gate low line and always remain on. The first auxiliary transistor Ta1 may keep the voltages at node Q2 and node Q substantially the same and may prevent voltage leakage from node Q to node Q2.

[0091] The sixth transistor T6 of the second output unit 123 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sixth transistor T6 is connected to the first output terminal of the first output unit 122, and the source and drain electrodes are connected between the first gate low line and the second output terminal from which the second scan signal SCAN2(n) is output. The sixth transistor T6 is turned on only when the first scan signal SCAN1(n) is not output, so as to transmit the first gate low voltage VGL1 to the second output terminal.

[0092] The seventh transistor T7 of the second output unit 123 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the seventh transistor T7 is connected to the QN node, and its source and drain electrodes are connected between the first high clock signal line and the second output terminal. The seventh transistor T7 can be turned on by the voltage at the QN node to transmit the first high clock signal HCLK1 to the second output terminal, and the first high clock signal HCLK1 can be output as the second scan signal SCAN2(n).

[0093] Furthermore, for another stage ST connected to the second high clock signal line instead of the first high clock signal line, such as stage ST in row (n+1), the second high clock signal HCLK2 can be transmitted to the second output terminal when the seventh transistor T7 is turned on.

[0094] The second auxiliary transistor Ta2 of the second output unit 123 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second auxiliary transistor Ta2 is connected to a first gate low line, and the source and drain electrodes are connected between the QB node and the QN node. The second auxiliary transistor Ta2, having a gate electrode connected to the first gate low line to remain always on, can transfer the voltage at the QB node to the voltage at the QN node. Furthermore, the second auxiliary transistor Ta2 can prevent the voltage at the QN node from leaking to the QB node.

[0095] The second capacitor CQN of the second output unit 123 is connected between the QN node and the second output terminal. The second capacitor CQN can store the voltage at the QN node. When the second scan signal SCAN2(n) is output, the second capacitor CQN can store the voltage at the QN node to keep the seventh transistor T7 in the on state.

[0096] Reference Figure 5The first output unit 122 can output a first scan signal SCAN1(n) from a first time t1 to a third time t3. Firstly, during the period when the high-level first scan signal SCAN1(n-1) is output in the previous stage ST(n-1), a first low clock signal LCLK1 is output at the first time t1. In this case, the third transistor T3, turned on by the first low clock signal LCLK1, can transmit the first scan signal SCAN1(n-1) from the previous stage ST(n-1) to the Q node. The high-level first scan signal SCAN1(n-1) can be stored in the first capacitor CQ. Furthermore, the fourth transistor T4, having a gate electrode connected to the Q node, is turned on by the first scan signal SCAN1(n-1) from the previous stage ST(n-1) to transmit the second gate low voltage VGL2 to the QB node. Therefore, the second transistor T2 of the first output unit 122 can be turned on by the second gate low voltage VGL2 transmitted to the QB node, and the turned-on second transistor T2 can output the gate high voltage VGH to the first output terminal.

[0097] Therefore, the first output unit 122 can output the gate high voltage VGH transmitted through the turned-on second transistor T2 until a third time t3 when the next first low clock signal LCLK1 is output as the first scan signal SCAN1(n) to the first output terminal. Therefore, the length of the first scan signal SCAN1(n) can be equal to the interval between outputting the first low clock signal LCLK1. For example, the interval from the time of outputting one first low clock signal LCLK2 to the time of outputting the next first low clock signal LCLK1 can be equal to the length of the first scan signal SCAN1(n).

[0098] Therefore, the second output unit 123 can output the first high clock signal HCLK1, which was output at the second time t2, as the second scan signal SCAN2(n). First, the first high clock signal HCLK1 is output at the second time t2, between the first time t1 and the third time t3, when the first scan signal SCAN1(n) is output. The second gate low voltage VGL2 applied to the QB node at the first time t1 can be transmitted to the QN node connected to the QB. Therefore, the seventh transistor T7, which has a gate electrode connected to the QN node, is turned on to transmit the first high clock signal HCLK1 to the second output terminal. In this case, the length of the second scan signal SCAN2(n) can be equal to the length of one first high clock signal HCLK1. Therefore, the second output unit 123 can output the first high clock pulse signal HCLK1, which was output at the second time t2, as the second scan signal SCAN2(n).

[0099] At this point, the QN node may change to a voltage lower than the second gate low voltage VGL2 due to the bootstrapping of the second capacitor CQN connected to the QN node. Therefore, the voltage at the QN node becomes lower, and the seventh transistor T7 can remain stably turned on when the second scan signal SCAN2(n) is output.

[0100] Furthermore, during the period from the first time t1 to the third time t3, the sixth transistor T6, which has a gate electrode connected to the first output terminal, can be kept off by the high-level first scan signal SCAN1(n). Therefore, when the second scan signal SCAN2(n) is output, the first gate low voltage VGL1 is not transmitted to the second output terminal.

[0101] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the first output unit 122 and the second output unit 123 of a single stage ST(n) of the gate driver 120 can share a single logic unit 121 to generate a first scan signal SCAN1(n) and a second scan signal SCAN2(n). The first output unit 122 can be connected to the logic unit 121 to output the first scan signal SCAN1(n). Specifically, the first transistor T1 of the first output unit 122 can be turned off based on the first scan signal SCAN1(n-1) transmitted from the logic unit 121 to the previous stage ST(n-1) of the Q node. At the same time, the second transistor T2 of the first output unit 122 can be turned on by the second gate low voltage VGL2 transmitted to the QB node through the fourth transistor T4 of the logic unit 121, and can transmit the gate high voltage VGH to the first output terminal to output the first scan signal SCAN1(n). Furthermore, when the sixth transistor T6 of the second output unit 123 is kept off by the first scan signal SCAN1(n) output from the first output unit 122, the seventh transistor T7 can be kept on by the second gate low voltage VGL2 transmitted from the QB node to the QN node, and can output the first high clock signal HCLK1 as the second scan signal SCAN2(n). Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the first scan signal SCAN1 and the second scan signal SCAN2 can be generated in a single stage ST including the logic unit 121, the first output unit 122 and the second output unit 123 connected to each other. Therefore, the first scan signal SCAN1 and the second scan signal SCAN2 can be generated in a single stage ST without additionally forming circuitry for generating the first scan signal SCAN1 and circuitry for generating the second scan signal SCAN2, making the structure of the gate driver 120 simpler and the bezel size easier to reduce.

[0102] In the display device 100 according to an exemplary embodiment of the present disclosure, the driving timing for outputting the first scan signal SCAN1 can be directly applied to outputting the second scan signal SCAN2, making it easier to drive the gate driver 120. First, in the first output unit 122 and logic unit 121, the first scan signal SCAN1(n) can be output using the first scan signal SCAN1(n-1) from the previous stage ST(n-1) and low clock signals LCLK1 and LCLK2. At this time, the second output unit 123 connected to the first output unit 122 and logic unit 121 can output the second scan signal SCAN2(n) based on the voltage transmitted from the first output unit 121 and logic unit 122. For example, the second output unit 123 can output the second scan signal SCAN2(n) based on the first scan signal SCAN1(n) transmitted from the first output unit 123 and the second gate low voltage VGL2 transmitted from the logic unit 121 to the QN node. Therefore, the sixth transistor T6 and the seventh transistor T7 of the second output unit 123 are turned on or off by the voltage of the first output unit 122 and the logic unit 121, thereby outputting the second scan signal SCAN2(n). As described above, in the display device 100 according to an exemplary embodiment of the present disclosure, the driving timing for outputting the first scan signal SCAN1 can be directly applied to the second output unit 123, making it easier to drive the gate driver 120.

[0103] Exemplary embodiments of this disclosure can also be described as follows:

[0104] According to one aspect of this disclosure, a display device is provided. The display device includes: a display panel defining a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; and a gate driver including a plurality of stages for supplying a high-level first scan signal and a second scan signal to each of the plurality of scan lines. Each of the plurality of stages includes a first output unit for outputting the first scan signal, a second output unit for outputting the second scan signal, a logic unit connected to the first output unit and the second output unit, a low clock signal line for outputting a low-level low clock signal and connected to the logic unit, and a high clock signal line for outputting a high-level high clock signal and connected to the second output unit.

[0105] The first output unit may include: a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a gate low line and a first output terminal from which a first scan signal is output; and a second transistor having a gate electrode connected to a QB node, and a source electrode and a drain electrode connected between a gate high line and the first output terminal.

[0106] The logic unit may include: a third transistor having a gate electrode connected to a low clock signal line, and a source electrode and a drain electrode connected between a Q node and a first output terminal of a preceding stage in a plurality of stages; a fourth transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a gate low line and a QB node; and a fifth transistor having a source electrode and a drain electrode connected between a gate high line and a QB node, wherein the third transistor and the fifth transistor are p-type transistors, and the fourth transistor is an n-type transistor.

[0107] When the third transistor is turned on and the first scan signal output from the previous stage is transmitted to the Q node, the fourth transistor can be turned on to transmit the gate low voltage from the gate low line to the QB node, and the second transistor can be turned on by the gate low voltage at the QB node to transmit the gate high voltage from the gate high line to the first output terminal.

[0108] The second output unit may include: a sixth transistor having a gate electrode connected to the first output terminal, and a source electrode and a drain electrode connected between the gate low line and the second output terminal from which the second scan signal is output; and a seventh transistor having a gate electrode connected to the QN node, and a source electrode and a drain electrode connected between the high clock signal line and the second output terminal, and the QN node may be electrically connected to the QB node.

[0109] When the first scan signal is output from the first output terminal and the sixth transistor is turned off, the seventh transistor can be turned on by the low gate voltage at the QB node to transmit the high clock signal to the second output terminal.

[0110] The length of the first scan signal can be equal to the interval of the output low clock signal, and the length of the second scan signal can be equal to the length of a single high clock signal.

[0111] The first output unit may further include a first capacitor connected between the Q node and the first output terminal, and when the first scan signal is output, the first capacitor may store the voltage at the Q node to keep the first transistor in the off state.

[0112] The second output unit may also include a second capacitor connected between the QN node and the second output terminal, and when the second scan signal is output, the second capacitor may store the voltage transmitted from the QB node to the QN node to keep the seventh transistor in the on state.

[0113] The low clock signal line may include: a first low clock signal line connected to odd-numbered stages among the multiple stages; and a second low clock signal line connected to even-numbered stages among the multiple stages. The third transistor of the logic unit may be turned on by a first low clock signal from the first low clock signal line or a second low clock signal from the second low clock signal line.

[0114] The high clock signal line may include: a first high clock signal line connected to the odd-numbered stage among the multiple stages; and a second high clock signal line connected to the even-numbered stage among the multiple stages, and the seventh transistor of the second output unit may output a first high clock signal from the first high clock signal line or a second high clock signal from the second high clock signal line as a second scan signal when the seventh transistor is turned on.

[0115] Each of the plurality of sub-pixels may include: a driving transistor having a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node; a first pixel transistor having a gate electrode connected to a plurality of scan lines, and a source electrode and a drain electrode connected between the first node and the third node; and a second pixel transistor having a gate electrode connected to a plurality of scan lines, and a source electrode and a drain electrode connected between the second node and a plurality of data lines. The first pixel transistor may be an n-type oxide semiconductor transistor turned on by a first scan signal output from the plurality of scan lines, and the second pixel transistor may be an n-type oxide semiconductor transistor turned on by a second scan signal output from the plurality of scan lines.

[0116] According to another aspect of this disclosure, a gate driver is provided, comprising a plurality of stages, wherein each of the plurality of stages is configured to output a first scan signal and a second scan signal, and comprising: a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a second gate low line and a first output terminal, wherein the first scan signal is output from the first output terminal; a second transistor having a gate electrode connected to a QB node, and a source electrode and a drain electrode connected between a gate high line and the first output terminal; a third transistor having a gate electrode connected to a low clock signal line, and a source electrode and a drain electrode connected between the Q node and a first output terminal of a previous stage of the plurality of stages; and a fourth transistor having a gate electrode connected to the Q node, and a source electrode and a drain electrode connected between the second gate low line and a first output terminal of a previous stage of the plurality of stages. The transistor comprises: a source electrode and a drain electrode between the gate low line and the QB node; a fifth transistor having a source electrode and a drain electrode connected between the gate high line and the QB node; a sixth transistor having a gate electrode connected to the first output terminal, and a source electrode and a drain electrode connected between the first gate low line and the second output terminal, wherein the second scan signal is output from the second output terminal; and a seventh transistor having a gate electrode connected to the QN node, and a source electrode and a drain electrode connected between the high clock signal line and the second output terminal, wherein the QN node is electrically connected to the QB node, wherein the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-type transistors, and the fourth transistor is an n-type transistor.

[0117] Each of the plurality of stages further includes: a first capacitor connected between the Q node and the first output terminal, and a second capacitor connected between the QN node and the second output terminal.

[0118] Each of the plurality of stages further includes: a first auxiliary transistor having a gate electrode connected to the first gate low line, and a source electrode and a drain electrode connected between the drain node and the Q node of the third transistor; and a second auxiliary transistor having a gate electrode connected to the first gate low line, and a source electrode and a drain electrode connected between the QB node and the QN node.

[0119] While exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of this disclosure.

Claims

1. A display device, comprising: A display panel is defined with a plurality of sub-pixels, the plurality of sub-pixels being connected to a plurality of scan lines and a plurality of data lines; as well as A gate driver comprising multiple stages for supplying a first scan signal and a second scan signal at a high level to each of the plurality of scan lines, wherein each of the plurality of stages comprises: A first output unit for outputting the first scan signal; A second output unit for outputting the second scan signal; A logic unit connected to the first output unit and the second output unit; A low clock signal line for outputting a low-level clock signal and connected to the logic unit; and This is used to output a high-level high clock signal and is connected to the high clock signal line of the second output unit. The first output unit includes: A first transistor has a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a second gate low line and a first output terminal, wherein the first scan signal is output from the first output terminal; and The second transistor has a gate electrode connected to the QB node, and a source electrode and a drain electrode connected between the gate high line and the first output terminal.

2. The display device according to claim 1, wherein, The logic unit includes: The third transistor has a gate electrode connected to the low clock signal line, and a source electrode and a drain electrode connected between the Q node and the first output terminal of the previous stage in the plurality of stages; A fourth transistor has a gate electrode connected to the Q node, and a source electrode and a drain electrode connected between the second gate low line and the QB node; and The fifth transistor has a source electrode and a drain electrode connected between the gate high line and the QB node. The third and fifth transistors are p-type transistors, and the fourth transistor is an n-type transistor.

3. The display device according to claim 2, wherein, When the third transistor is turned on and the first scan signal output from the previous stage is transmitted to the Q node, the fourth transistor is turned on to transmit the gate low voltage from the second gate low line to the QB node, and the second transistor is turned on by the gate low voltage at the QB node to transmit the gate high voltage from the gate high line to the first output terminal.

4. The display device according to claim 3, wherein, The second output unit includes: A sixth transistor has a gate electrode connected to the first output terminal, and a source electrode and a drain electrode connected between the first gate low line and the second output terminal, wherein the second scan signal is output from the second output terminal; and The seventh transistor has a gate electrode connected to the QN node, and a source electrode and a drain electrode connected between the high clock signal line and the second output terminal. The QN node is electrically connected to the QB node.

5. The display device according to claim 4, wherein, When the first scan signal is output from the first output terminal and the sixth transistor is turned off, the seventh transistor is turned on by the low gate voltage at the QB node to transmit the high clock signal to the second output terminal.

6. The display device according to claim 5, wherein, The length of the first scan signal is equal to the interval of the low clock signal output, and the length of the second scan signal is equal to the length of a single high clock signal.

7. The display device according to claim 4, wherein, The first output unit further includes a first capacitor connected between the Q node and the first output terminal, and When the first scan signal is output, the first capacitor stores the voltage at the Q node to keep the first transistor in the off state.

8. The display device according to claim 4, wherein, The second output unit further includes a second capacitor connected between the QN node and the second output terminal, and Specifically, when the second scan signal is output, the second capacitor stores the voltage transmitted from the QB node to the QN node to keep the seventh transistor in the on state.

9. The display device according to claim 4, wherein, The low clock signal line includes: The first low clock signal line is connected to the odd-numbered stage among the plurality of stages; and The second low clock signal line is connected to the even-numbered stage among the plurality of stages, and The third transistor of the logic unit is turned on by a first low clock signal from the first low clock signal line or a second low clock signal from the second low clock signal line.

10. The display device according to claim 4, wherein, The high clock signal line includes: The first high clock signal line is connected to the odd-numbered stage among the plurality of stages; and The second high clock signal line is connected to the even-numbered stage among the plurality of stages, and Wherein, when the seventh transistor of the second output unit is turned on, it outputs either the first high clock signal from the first high clock signal line or the second high clock signal from the second high clock signal line as the second scan signal.

11. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes: A driving transistor having a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node. A first pixel transistor has a gate electrode connected to the plurality of scan lines, and a source electrode and a drain electrode connected between the first node and the third node; and The second pixel transistor has a gate electrode connected to the plurality of scan lines, and a source electrode and a drain electrode connected between the second node and the plurality of data lines. Wherein, the first pixel transistor is an n-type oxide semiconductor transistor that is turned on by the first scan signal output from the plurality of scan lines, and The second pixel transistor is an n-type oxide semiconductor transistor that is turned on by the second scan signal output from the plurality of scan lines.

12. The display device according to claim 1, wherein, The second output unit is configured to output the second scan signal based on a first scan signal received from a first output unit of the same level and a voltage received from a logic unit of the same level.

13. A gate driver comprising multiple stages, wherein, Each of the plurality of stages is configured to output a first scan signal and a second scan signal, and includes: A first transistor has a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a second gate low line and a first output terminal, wherein the first scan signal is output from the first output terminal; The second transistor has a gate electrode connected to the QB node, and a source electrode and a drain electrode connected between the gate high line and the first output terminal. The third transistor has a gate electrode connected to a low clock signal line, and a source electrode and a drain electrode connected between the Q node and the first output terminal of the previous stage in the plurality of stages; The fourth transistor has a gate electrode connected to the Q node, and a source electrode and a drain electrode connected between the second gate low line and the QB node; The fifth transistor has a source electrode and a drain electrode connected between the gate high line and the QB node; A sixth transistor has a gate electrode connected to the first output terminal, and a source electrode and a drain electrode connected between the first gate low line and the second output terminal, wherein the second scan signal is output from the second output terminal; and The seventh transistor has a gate electrode connected to the QN node, and a source electrode and a drain electrode connected between the high clock signal line and the second output terminal. The QN node is electrically connected to the QB node. Wherein, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-type transistors, and the fourth transistor is an n-type transistor.

14. The gate driver of claim 13, wherein, Each of the plurality of levels also includes: The first capacitor connected between the Q node and the first output terminal, and A second capacitor is connected between the QN node and the second output terminal.

15. The gate driver according to claim 14, wherein, Each of the plurality of levels also includes: A first auxiliary transistor has a gate electrode connected to the first gate low line, and a source electrode and a drain electrode connected between the drain node and the Q node of the third transistor; and The second auxiliary transistor has a gate electrode connected to the first gate low line, and a source electrode and a drain electrode connected between the QB node and the QN node.

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