Mram chip

Abstract

The application provides a MRAM chip, which comprises one or more arrays, the array comprises row-column distributed memory cells and a plurality of word lines, a plurality of bit lines and a plurality of source lines connected with the memory cells, and a power supply end control circuit is arranged at the power supply end of each bit line and each source line in the array structure, the power supply end control circuit has three different channels, and the power supply mode of each bit line and source line is changed when a write 0, write 1 or read operation is performed on any memory cell.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to an MRAM chip. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a promising new type of memory with advantages such as simple circuit design, fast read and write speed, unlimited erase and write cycles, and no data loss when power is off.

[0003] The core memory cell of MRAM consists of one magnetic tunnel junction (MTJ) and one field-effect transistor (CMOS). During the manufacturing process of the MTJs, a contact short circuit may occur between some adjacent locations, known as a bottom short. In this case, all MTJs on the black border (BL) containing the two shorted MTJs (excluding the two shorted MTJs themselves) will be misread. Simultaneously, the shorted MTJs will also be prone to write errors, leading to inaccurate test results and affecting yield assessment. For example, Figure 1 The diagram illustrates the MRAM array structure, where read and write operations on the MTJs are controlled by disabling SL, BL, and WL. In the diagram, ①, ②, ③, and ④ represent four MTJs. A bottom short occurs between MTJs ① and ②, which can lead to miswrites or misreads.

[0004] For ease of understanding, Figure 2a The equivalent circuit diagram is shown when MTJ ③ is written with a 0. When MTJ ③ is written with a 0, BL <1> Write voltage VW, SL <1> Following GND, WL <2> If the unselected SL and BL are grounded, then MTJs ① and ② may be written incorrectly. Figure 2b The equivalent circuit diagram after writing a 1 to MTJ ① is shown. When writing a 1 to MTJ ①, BL... <1> Connect to GND, SL <1> Write voltage VW, WL <1> If the unselected SL and BL are grounded, then MTJ ② may be written incorrectly. Figure 2c The equivalent circuit diagram for misreading occurs when reading 0 or 1 from MTJ ③. When performing a read operation on MTJ ③, BL... <1> Connect to read voltage VR, SL <1> Following GND, WL <2> If the selected pins SL and BL are grounded, the resistance read is ③ / / ①+②. The states of ① and ② affect the reading result of ③, which may result in an incorrect reading. Branch A is the normal writing path to MTJ, and branch B is the rewriting path caused by the extra path due to the Bottom Short.

[0005] This shows that a bottom short circuit between two MTJs will directly affect the normal operation of the chip. However, simply rendering the entire MRAM chip unusable due to a bottom short circuit would be a huge waste. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides an MRAM chip that can tolerate bottom short-circuit failures between some MTJs, preventing the MTJs from being miswritten or misread, thus enabling the memory chip to function normally.

[0007] This invention provides an MRAM chip, comprising one or more arrays, each array further comprising:

[0008] The memory cells are arranged in rows and columns, and each memory cell includes a magnetic tunnel junction and a MOS transistor connected in series;

[0009] Multiple letter lines;

[0010] Pairs of multiple bit lines and multiple source lines; and,

[0011] Multiple power supply control circuits are connected to the power supply terminals of each bit line and each source line. Each power supply control circuit has three different paths, which are used to change the power supply mode of each bit line and source line when performing a write 0, write 1 or read operation on any memory cell.

[0012] Optionally, the power supply control circuit connected to one of the bit lines includes:

[0013] The first gating transistor is connected between the bit line and the power line, which is used to input write voltage or read voltage;

[0014] The second gating transistor is connected between the bit line and the ground line;

[0015] The third gate transistor and the first resistive device, connected in series, are connected between the bit line and the ground line;

[0016] The power supply control circuit connected to the corresponding source line of this bit line has the same circuit structure, including:

[0017] The fourth gating transistor is connected between the source line and the power line, which is used to input write voltage or read voltage;

[0018] The fifth select transistor is connected between the source line and the ground line;

[0019] The sixth gate transistor and the second resistive device, connected in series, are connected between the source line and the ground line.

[0020] Optionally, the first gating transistor and the fourth gating transistor are PMOS transistors;

[0021] The second, third, fifth, and sixth gating transistors are NMOS transistors.

[0022] Optionally, the first resistive device and the second resistive device are implemented using polysilicon resistors or magnetic tunnel junctions.

[0023] Optionally, the resistance values ​​of the first resistive device and the second resistive device are n*Rap, where n≥2, and Rap represents the resistance value when the magnetic tunnel junction of the memory cell is in an antiparallel state.

[0024] Optionally, it also includes a column address selector and a column address decoder, used to select the bit line and source line of the target memory cell based on the column address during write and read operations.

[0025] Optionally, it also includes a row address selector and a row address decoder, used to select the word line of the target memory cell based on the row address during write and read operations.

[0026] This invention provides an MRAM chip with power supply control circuits at the power supply terminals of each bit line and each source line in the array structure. When writing a 0 to any memory cell in the array, the selected bit line is connected to the write voltage, the selected source line is grounded, and the remaining unselected bit lines and source lines are grounded through resistive devices. When writing a 1 to any memory cell in the array, the selected bit line is grounded, the selected source line is connected to the write voltage, and the remaining unselected bit lines and source lines are grounded through resistive devices. When performing a read operation on any memory cell in the array, the selected bit line is connected to the read voltage, the selected source line is grounded, and the remaining unselected bit lines and source lines are grounded through resistive devices. Compared with the prior art, the array structure of this invention can tolerate bottom short-circuit failures between some MTJs, avoiding the problems of incorrect writing and reading of related MTJs, and enabling the memory chip to work normally. Attached Figure Description

[0027] Figure 1 This refers to the array structure of MRAM chips in the prior art;

[0028] Figure 2a for Figure 1 A schematic diagram of the equivalent circuit for a write operation on an array structure;

[0029] Figure 2b for Figure 1 A schematic diagram of the equivalent circuit for a write operation on an array structure;

[0030] Figure 2c for Figure 1 A schematic diagram of the equivalent circuit for a read operation on an array structure;

[0031] Figure 3 This is an example of an MRAM chip array structure according to an embodiment of the present invention;

[0032] Figure 4aThis is a schematic diagram of an array structure for a write operation according to an embodiment of the present invention;

[0033] Figure 4b This is a schematic diagram of an array structure for a write operation according to an embodiment of the present invention;

[0034] Figure 4c This is a schematic diagram of an array structure for a read operation according to an embodiment of the present invention;

[0035] Figure 5a for Figure 4a Equivalent circuit diagram for write operation;

[0036] Figure 5b for Figure 4b Equivalent circuit diagram for write operation;

[0037] Figure 5c for Figure 4c Equivalent circuit diagram for read operation;

[0038] Figure 6 This is an array structure of an MRAM chip according to another embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0042] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0043] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0044] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] One embodiment of the present invention provides an MRAM chip, the MRAM chip comprising one or more arrays, such as... Figure 3 As shown, each array further includes:

[0046] The memory cells are arranged in rows and columns, each memory cell including a magnetic tunnel junction and a MOS transistor connected in series, with one end of the magnetic tunnel junction connected to the drain of the MOS transistor;

[0047] Multiple word lines WL <0> ~WL <n>Each word line is connected to the gate of the MOS transistor contained in one of the multiple memory cells in a row;

[0048] Paired multi-bit lines BL <0> ~BL <n>and multiple source lines SL <0> ~SL <n>Each bit line is connected to the other end of a magnetic tunnel junction contained in one of the columns of memory cells, and each source line is connected to the source of a MOS transistor contained in one of the columns of memory cells; and,

[0049] Multiple power supply control circuits are connected to the power supply terminals of each bit line and each source line. Each power supply control circuit has three different paths, which are used to change the power supply mode of each bit line and source line when performing a write 0, write 1 or read operation on any memory cell.

[0050] Specifically, the power supply control circuit is used to control the power supply mode of each bit line and each source line as follows:

[0051] When writing 0 to any memory cell in the array, the selected bit line is connected to the write voltage, the selected source line is grounded, and the remaining unselected bit lines and source lines are grounded through resistive devices.

[0052] When writing 1 to any memory cell in the array, the selected bit line is grounded, the selected source line is connected to the write voltage, and the remaining unselected bit lines and source lines are grounded through resistive devices.

[0053] When a read operation is performed on any memory cell of the array, the selected bit line is connected to the read voltage, the selected source line is grounded, and the remaining unselected bit lines and source lines are grounded through resistive devices.

[0054] As one implementation method, Figure 3 This diagram illustrates one circuit structure for the power supply control circuit. Each bit line and each source line connected to the power supply control circuit has the same circuit structure. The explanation focuses on one bit line and one source line.

[0055] Connected to bit line BL <0> The power supply control circuit includes:

[0056] The first selection transistor M1 is connected between the bit line and the power line. The power line is used to input the write voltage VW or the read voltage VR. That is, the write voltage and the read voltage share the same power line. The voltage on the power line is different through the read and write control circuit.

[0057] The second gating transistor M2 is connected between the bit line and the ground line;

[0058] The third gating transistor M3 and the first resistive device R1, connected in series, are connected between the bit line and the ground line;

[0059] Connected to source line SL <0> The power supply control circuit includes:

[0060] The fourth gating transistor M4 is connected between the source line and the power line, which is used to input the write voltage VW or the read voltage VR.

[0061] The fifth selector transistor M5 is connected between the source line and the ground line;

[0062] The sixth gate transistor M6 and the second resistive device R2, connected in series, are connected between the source line and the ground line.

[0063] In this embodiment, M1 and M4 are PMOS transistors, while M2, M3, M5, and M6 are NMOS transistors.

[0064] Although the power supply control circuits for the bit line and source line have the same structure, the control signals for the gating transistors are different. Specifically, M1 and M2 have the gate input signal DATA, and M4 and M5 have the gate input DATA_N. DATA_N is a signal with the opposite level to DATA. Therefore, this circuit controls the BL... <0> and SL <0> When a 0 is written to a memory cell, M1 and M5 are turned on; when a 1 is written, M4 and M2 are turned on. When BL_N and SL_N are low, M3 and M6 are turned off. The control signals BL and SL on other columns are high. The bit lines and source lines are grounded through resistive devices. Additionally, the gate input signal BL_N for M3 and the gate input signal SL_N for M6 turn on M3 and M6 when data is written to memory cells in other columns.

[0065] It should also be noted that the control process of the power supply terminal control circuits on other bit lines and source lines is similar and will not be described in detail here.

[0066] In summary, the above circuit structure can achieve the following: when writing 0 to any MTJ, the BL of the selected MTJ is connected to the write voltage VW, SL is connected to GND, WL is enabled, and the SL and BL of the other memory cells are connected to GND in series with resistive devices, and WL is connected to GND.

[0067] When writing 1 to any MTJ, the SL of the selected MTJ is connected to the write voltage VW, BL is connected to GND, and WL is enabled. For the other memory cells, the SL and BL are connected to GND in series with resistive devices, and WL is connected to GND.

[0068] When performing a read operation on any MTJ, select the MTJ and connect BL to the read voltage VR, SL to GND, and WL to enable. For the remaining SL and BL, connect the series resistive devices to GND, and connect WL to GND.

[0069] To illustrate the effects of the present invention, it is still denoted as Figure 1 Take the array structure as an example.

[0070] like Figure 4a As shown, based on this invention, when writing 0 to MTJ in array ③, the selected BL... <1> Connect the write voltage VW, and select SL. <1> Connect to GND; unselected SL and BL are grounded through resistive devices.

[0071] like Figure 4b As shown, based on this invention, when writing 1 to MTJ ① in the array, the selected BL... <1> Connect to GND, select SL <1> Connect the write voltage VW, and ground the unselected SL and BL through resistive devices;

[0072] like Figure 4c As shown, when reading data from MTJ in array ③, the selected BL <1> Connect to read voltage VR, select SL <1> Connect to GND. Unselected SL and BL are grounded through resistive devices.

[0073] Correspondingly, Figure 5a It shows Figure 4a Equivalent circuit diagram when writing 0 to MTJ in array ③. Figure 5b It shows Figure 4b Equivalent circuit diagram when writing 1 to MTJ ① in the array. Figure 5c It shows Figure 4c Equivalent circuit diagram for reading MTJ #3. Analysis. Figure 5a and Figure 5b A large resistor is connected in series with ground at the unselected SL and BL terminals, causing a very small current to flow through branch B. When a 0 is written to MTJ ③, MTJs ① and ② will not be overwritten due to insufficient voltage division; when a 1 is written to MTJ ①, MTJ ② will not be overwritten due to insufficient voltage division. Additionally, if... Figure 5c When reading MTJ ③, if the series resistor is large enough, the resistance read is ③ / / ①+②+R≈③.

[0074] The present invention provides an MRAM chip whose array structure can tolerate bottom short-circuit failures between some MTJs, avoiding the problems of miswriting and misreading of related MTJs, so that the memory chip can work normally.

[0075] Furthermore, in the above embodiments, the resistive device used in the power supply control circuit can be implemented using a polysilicon resistor or a magnetic tunnel junction (MTJ). The resistance value of the resistive device is n*Rap, where n≥2, and Rap represents the resistance value when the magnetic tunnel junction of the memory cell is in an antiparallel state.

[0076] Additionally, in another embodiment, such as Figure 6 As shown, the MRAM chip may further include a column address selector and a column address decoder for selecting the bit line and source line of the target memory cell based on the column address during write and read operations. Additionally, it includes a row address selector and a row address decoder for selecting the word line of the target memory cell based on the row address during write and read operations.

[0077] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.< / n> < / n> < / n>

Claims

1. An MRAM chip, characterized in that, Includes one or more arrays, each array further including: The memory cells are arranged in rows and columns, and each memory cell includes a magnetic tunnel junction and a MOS transistor connected in series; Multiple letter lines; Pairs of multiple bit lines and multiple source lines; and, Multiple power supply control circuits are connected to the power supply terminals of each bit line and each source line. Each power supply control circuit has three different paths, which are used to change the power supply mode of each bit line and source line when performing a write 0, write 1 or read operation on any memory cell. The power supply control circuit connected to one of the bit lines includes: The first gating transistor is connected between the bit line and the power line, which is used to input write voltage or read voltage; The second gating transistor is connected between the bit line and the ground line; The third gating transistor and the first resistive device, connected in series, are connected between the bit line and the ground line; The power supply control circuit connected to the corresponding source line of this bit line has the same circuit structure, including: The fourth gating transistor is connected between the source line and the power line, which is used to input write voltage or read voltage; The fifth select transistor is connected between the source line and the ground line; The sixth gate transistor and the second resistive device, connected in series, are connected between the source line and the ground line; When writing 0 to any memory cell, the selected bit line is connected to the write voltage, the selected source line is grounded, the remaining unselected bit lines are grounded through their respective first resistive devices, and the remaining unselected source lines are grounded through their respective second resistive devices. When writing 1 to any memory cell, the selected bit line is grounded, the selected source line is connected to the write voltage, the remaining unselected bit lines are grounded through their respective first resistive devices, and the remaining unselected source lines are grounded through their respective second resistive devices. When a read operation is performed on any memory cell, the selected bit line is connected to the read voltage, the selected source line is grounded, the remaining unselected bit lines are grounded through their respective first resistive devices, and the remaining unselected source lines are grounded through their respective second resistive devices.

2. The MRAM chip according to claim 1, characterized in that, The first gating transistor and the fourth gating transistor are PMOS transistors; The second, third, fifth, and sixth gating transistors are NMOS transistors.

3. The MRAM chip according to claim 1, characterized in that, The first resistive device and the second resistive device are implemented using polysilicon resistors or magnetic tunnel junctions.

4. The MRAM chip according to claim 1, characterized in that, The resistance values ​​of the first resistive device and the second resistive device are n. Rap, n≥2, Rap represents the resistance value of the magnetic tunnel junction of the memory cell when it is in an antiparallel state.

5. The MRAM chip according to claim 1, characterized in that, Also includes: Column address selectors and column address decoders are used to select the bit line and source line of the target memory cell based on the column address during write and read operations.

6. The MRAM chip according to claim 1, characterized in that, Also includes: Row address selectors and row address decoders are used to select the word line of the target memory cell based on the row address during write and read operations.

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