Setting module for synchronous dynamic random access memory and setting method thereof

Abstract

A setting module for SDRAM and a setting method thereof. The setting module includes at least one register and a controller. The controller is configured to control the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used to initialize the SDRAM; set a value of the at least one register in the initialization setting mode; and set the SDRAM according to the value of the at least one register.

Description

Technical Field

[0001] This invention relates to a setting module and setting method for a memory, and more particularly to a setting module and setting method for a synchronous dynamic random access memory. Background Technology

[0002] In Synchronous Dynamic Random Access Memory (SDRAM) architectures, SDRAM needs to be initialized through an SDRAM controller. Known SDRAM controllers are typically developed specifically for the instructions and operational sequence required during manufacturing. Given a complete SDRAM controller, any defects, flaws, or errors in the initialization settings or their order are difficult to verify or otherwise correct. Summary of the Invention

[0003] The purpose of this invention is to provide a method for setting up a Synchronous Dynamic Random Access Memory (SDRAM), comprising: controlling the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used to initialize the SDRAM; setting the value of at least one register in the initialization setting mode; and setting the SDRAM according to the value of at least one register.

[0004] The present invention also provides a setting module for SDRAM, including at least one register and a controller. The at least one register is electrically connected to the SDRAM. The controller is electrically connected to the SDRAM and the at least one register, and is used to: control the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used to initialize the SDRAM; set the value of the at least one register in the initialization setting mode; and set the SDRAM according to the value of the at least one register. Attached Figure Description

[0005] The embodiments of the invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 This is a block diagram of the setting module according to some embodiments of the present invention.

[0007] Figure 2A This is a block diagram of the setting module according to some embodiments of the present invention.

[0008] Figure 2B This is a block diagram of the setting module according to some embodiments of the present invention.

[0009] Figure 3 This is a flowchart illustrating the setup method for some embodiments of the present invention.

[0010] Figure 4 This is a flowchart illustrating the setup method for some embodiments of the present invention. Detailed Implementation

[0011] Embodiments of the invention are discussed in more detail below. However, it should be understood that the invention provides many applicable concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the invention.

[0012] The known Synchronous Dynamic Random Access Memory (SDRAM) architecture lacks operational flexibility. Any defects, flaws, or errors in the initialization settings or the order of settings for SDRAM are difficult to verify or correct by other means. To increase the operational flexibility of the SDRAM architecture, this invention provides a setup module and its setup method.

[0013] Please see Figure 1 This is a block diagram of the setting module 1 according to some embodiments of the present invention. The setting module 1 includes at least one register 11 and a controller 13, with the register 11 and controller 13 electrically connected. The setting module 1 is electrically connected to a Synchronous Dynamic Random Access Memory (SDRAM) 9. Data and signals are transmitted between components via electrical connections. Related control operations will be further described below.

[0014] In some embodiments, SDRAM 9 exchanges data with a device (e.g., a computer host) via a general-purpose bus. When initialization settings for SDRAM 9 are required, controller 13 switches SDRAM 9 to initialization setting mode based on user instructions. The initialization setting mode is used to initialize SDRAM 9.

[0015] In initialization mode, the user can set the value of at least one register 11 through the controller 13. Subsequently, after the value of at least one register 11 is set, the controller 13 sets the SDRAM 9 according to the value of at least one register 11. Furthermore, when the user needs to perform initialization settings for the SDRAM 9, it is usually necessary to set different instruction types for the SDRAM 9 to complete the initialization settings of the SDRAM 9.

[0016] In some embodiments, the instruction types of SDRAM 9 include: (1) macro command types, such as instruction type set CMD_TYPE set, Refresh, Pre-charge allbanks and No operation; (2) mode address types, such as mode register address; (3) mode data types, such as mode register access data; and (4) timing types, such as the time interval between two instructions.

[0017] At least one register 11 has different values ​​corresponding to different instruction types of SDRAM 9. Therefore, the user can fill in the corresponding values ​​in at least one register 11 for different instruction types. In this way, after the values ​​of at least one register 11 are set, the controller 13 can set SDRAM 9 according to the values ​​of at least one register 11 to complete the initialization setting of SDRAM 9.

[0018] Please see Figure 2A This is a block diagram of the setting module 2 according to some embodiments of the present invention. The setting module 2 includes multiple registers 21A and 21B and a controller 23, with registers 21A and 21B electrically connected to the controller 23. In some embodiments, register 21A includes an instruction index register, the stored values ​​of which correspond to the index and time-related instructions of the SDRAM 8. Register 21B includes a macro instruction and mode information register, the stored values ​​of which correspond to the macro instructions, mode address, and mode data of the SDRAM 8.

[0019] Setting module 2 is electrically connected to SDRAM 8 via demultiplexer 7. Multiple outputs of demultiplexer 7 correspond to multiple pins of SDRAM 8. Demultiplexer 7 decodes the values ​​provided by setting module 2 and triggers the corresponding pins of SDRAM 8 based on the decoded values, thereby setting SDRAM 8. Data and signals are transmitted between components via electrical links. Related control operations will be further described below.

[0020] In some embodiments, when SDRAM 8 is in bus data access mode (i.e., SDRAM 8 exchanges data with the device (e.g., computer host) via a general-purpose bus) and initialization settings are required for SDRAM 8, controller 23 stops the bus data access mode of SDRAM 8 based on user instructions and switches SDRAM 8 to initialization setting mode. The initialization setting mode is used to initialize SDRAM 8. More specifically, in the initialization setting mode, the relevant initialization settings are mainly performed on the instruction types and their operation order required for SDRAM 8 operation.

[0021] In initialization mode, the user can set the values ​​of registers 21A and 21B through controller 23. After the values ​​of registers 21A and 21B are set, controller 23 configures SDRAM 8 according to these values. Furthermore, when the user needs to perform initialization settings for SDRAM 8, it typically needs to configure different instruction types for SDRAM 8 to complete the initialization process.

[0022] Different values ​​in registers 21A and 21B correspond to different combinations of instruction types in SDRAM 8. Therefore, the user can first fill in the corresponding values ​​in registers 21A and 21B for different instruction types. In this way, after the values ​​in registers 21A and 21B are set, the controller 23 can configure SDRAM 8 according to the values ​​in registers 21A and 21B to complete the initialization of SDRAM 8. The technology of this invention will be further illustrated below through various examples.

[0023] In some examples, the value of register 21A corresponds to the index and time-related instructions of SDRAM 8. Specifically, the user can set the corresponding value in register 21A through controller 23, and the value set in register 21A is used to trigger the initialization settings of the index and time-related instructions of SDRAM 8 accordingly. After the setting is completed, controller 23 directly sets SDRAM 8 according to the value of register 21A.

[0024] In some examples, the value of register 21B corresponds to the macro instruction related instructions of SDRAM 8. Specifically, the user can set the corresponding value in register 21B through controller 23, and the value set in register 21B is used to trigger the initialization settings of SDRAM 8 macro instructions accordingly. After the setting is completed, controller 23 directly sets SDRAM 8 according to the value of register 21B.

[0025] In some examples, the value of register 21B corresponds to the mode address and mode data related instructions of SDRAM 8. Specifically, the user can set the corresponding value in register 21B through controller 23. The value set in register 21B is used to trigger the initialization settings of the mode address and mode data of SDRAM 8 accordingly. After the setting is completed, controller 23 directly sets SDRAM 8 according to the value of register 21B.

[0026] In some examples, the value of register 21B corresponds to the relevant instruction for the mode register read (MRR) check status of SDRAM 8. Specifically, the user can set the corresponding value in register 21B through controller 23, and the value set in register 21B is used to trigger the status check of the SDRAM 8 MRR instruction accordingly. After the setting is completed, controller 23 directly sets the SDRAM 8 according to the value of register 21B.

[0027] It should be noted that the aforementioned SDRAM 8 initialization settings can be executed individually or in various combinations as needed. For example, the value of register 21B can simultaneously correspond to the SDRAM 8's macro instruction related instructions, as well as mode address and mode data related instructions. The user can set the corresponding value in register 21B through controller 23. The value set in register 21B is used to trigger the initialization settings of the SDRAM 8's macro instruction related instructions, as well as mode address and mode data related instructions. After the settings are complete, controller 23 directly sets the SDRAM 8 according to the value of register 21B.

[0028] In some embodiments, if it is necessary to complete the initialization settings of different SDRAM 8 simultaneously (e.g., to simultaneously complete the initialization settings of SDRAM 8 index and time-related instructions, macro instruction-related instructions, and mode address and mode data-related instructions), this can be done by accessing synchronization registers 21A and 21B. Specifically, the aforementioned SDRAM 8 initialization settings can be triggered using an additional synchronization control register. Please refer to [link to relevant documentation]. Figure 2B This is another block diagram of the setting module 2 in some embodiments of the present invention. The setting module 2 also includes a synchronization control register 21C, used to: (1) mark whether the SDRAM 8 has switched to the initialization setting mode; and (2) access the synchronization trigger registers 21A and 21B.

[0029] Some embodiments of the present invention include a method for setting up SDRAM, the flowchart of which is shown below. Figure 3 As shown.

[0030] The setting methods in these embodiments are implemented by a setting module (such as the setting module in the aforementioned embodiments), and the detailed operation of the method is as follows. First, step S301 is executed to control the SDRAM to switch to the initialization setting mode. The initialization setting mode is used to initialize the SDRAM. Step S302 is executed to set the value of at least one register in the initialization setting mode. Step S303 is executed to set the SDRAM according to the value of at least one register.

[0031] Some embodiments of the present invention include a method for setting up SDRAM, the flowchart of which is shown below. Figure 4 As shown. The setting methods of these embodiments are implemented by a setting module (such as the setting module in the aforementioned embodiments), and the detailed operation of the methods is as follows.

[0032] First, step S401 is executed to stop the SDRAM's bus data access mode and switch the SDRAM to the initialization setting mode. The initialization setting mode is used to initialize the SDRAM. Step S402 is executed to set the values ​​of the instruction index register and the macro instruction and mode information register in the initialization setting mode. Step S403 is executed to trigger an initialization operation based on the value of the synchronization control register, so that the interpreter decodes the values ​​of the instruction index register and the macro instruction and mode information register, and sets the SDRAM's instruction index, instruction execution time, macro instructions, mode address, mode data, MRR check status, or any combination thereof, according to the decoded values.

[0033] Execute step S404 to determine whether the initialization setup mode has ended. If yes, execute step S405 to control the SDRAM to switch to bus data access mode. If no, repeat step S402.

[0034] In summary, the SDRAM setup module and method provided by this invention can control the SDRAM through additional registers and control circuitry to verify or correct defects, flaws, or errors in the design and sequence of SDRAM initialization operations. It should be noted that in some embodiments, the controller includes logic circuitry capable of executing operations and instructions, but this is not intended to limit the implementation of the hardware components of this invention.

[0035] The foregoing description briefly outlines the features of certain embodiments of the present invention, enabling those skilled in the art to more fully understand the various embodiments of the invention. Those skilled in the art will readily recognize that the present invention can serve as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of the present invention, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1: Settings Module

[0038] 11: Register

[0039] 13: Controller

[0040] 2: Settings Module

[0041] 21A~21C: ​​Registers

[0042] 23: Controller

[0043] 7: Demultiplexer

[0044] 8: SDRAM

[0045] 9: SDRAM

[0046] S301~S303: Steps

[0047] S401~S405: Steps

Claims

1. A method for setting up a synchronous dynamic random access memory (SDRAM), the method comprising: Control the SDRAM to switch to the initialization setting mode, wherein the initialization setting mode is used to initialize the SDRAM; For different instruction types of the SDRAM, the value of at least one register is set in this initialization setting mode; and The initialization operation is triggered based on the value of the synchronization control register to set the SDRAM according to the value of the at least one register.

2. The setting method as described in claim 1, wherein, The step of setting the SDRAM according to the value of the at least one register further includes: The value of at least one register is decoded by a decoder, and the SDRAM is set according to the decoded value.

3. The setting method as described in claim 1, wherein, The at least one register includes an instruction index register, and the step of setting the SDRAM according to the value of the at least one register further includes: The instruction index and instruction execution time of the SDRAM are set according to the value of the instruction index register.

4. The setting method as described in claim 1, wherein, The at least one register includes a macro instruction and mode information register, and the step of setting the SDRAM according to the value of the at least one register further includes: The macro instruction, mode address, and mode data of the SDRAM are set according to the value of the macro instruction and mode information register.

5. The setting method as described in claim 1, wherein, The at least one register includes a macro instruction and mode information register, and the step of setting the SDRAM according to the value of the at least one register further includes: The SDRAM's mode register read check state is set according to the macro instruction and the value of the mode information register.

6. The setting method as described in claim 1, wherein, The steps for controlling the SDRAM to switch to this initialization setting mode also include: Stop the bus data access mode of the SDRAM and control the SDRAM to switch to the initialization setting mode.

7. The setting method as described in claim 1, further comprising: Determine whether to end the initialization setup mode.

8. The setting method as described in claim 7, further comprising: When it is determined that the initialization setting mode has ended, the SDRAM is switched to bus data access mode.

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