A method, device and medium for reducing read error correction failure probability

Abstract

The application discloses a method, device and medium for reducing read error correction failure probability, relates to the field of NAND, and aims to reduce the influence of initial voltage threshold offset and reduce read error correction failure probability. In the application, the divided experimental temperature values and experimental wear values are combined at will, and the voltage offset values after the initial voltage threshold offset are collected under each combination. One of the voltage offset values is selected as a working voltage offset value. A read task is received. The read task is performed according to the working voltage offset value and a default voltage value, and NAND is read. Through the influence of the temperature factor and the wear factor on the NAND, the influence degree of the initial voltage threshold offset of the NAND is analyzed, and a suitable working voltage offset value is obtained. When the NAND is read, the default voltage value is calibrated through the working voltage offset value, so as to reduce the influence of the initial voltage threshold offset and reduce the read error correction failure probability, improve the probability of successful error correction of the first read NAND, and avoid entering the error correction process.

Description

Technical Field

[0001] This application relates to the field of NAND, and in particular to a method, apparatus and medium for reducing the probability of read error correction failure. Background Technology

[0002] NAND flash memory is a superior storage device compared to hard disk drives, especially in low-capacity applications of up to 4GB. As the demand for products with lower power consumption, lighter weight, and better performance continues, NAND has proven extremely attractive. NAND flash memory is a non-volatile storage technology, meaning it retains data even after power is lost. Its development aims to reduce the cost per bit of storage and increase storage capacity.

[0003] In human life, massive amounts of data are generated constantly that require processing and storage. The rapid development of information technology has placed higher demands on the performance of storage systems. Solid-state drives (SSDs) are widely used due to their fast read and write speeds and low power consumption. However, with the increase of power-on hours (PE), NAND flash memory is susceptible to factors such as read interference, write interference, and data retention time. Therefore, the reliability of NAND flash memory itself is crucial for solid-state drives (SSDs).

[0004] In NAND flash memory based on charge trap flash (CTF) technology, a phenomenon occurs where an initial threshold voltage shift (IVS) appears within a very short time (100ms to 1s) after data is written to the NAND. The degree to which different manufacturers' NAND is affected by this initial threshold voltage shift varies slightly. If data is immediately read using a normal voltage at this point, a high probability of bit error ratio (BER) will occur, and error correction may even fail. The initial threshold voltage shift is a significant factor affecting the reliability of NAND flash memory.

[0005] Therefore, how to reduce the impact of initial voltage threshold offset to reduce the probability of read error correction failure is a technical problem that urgently needs to be solved by those in this field. Summary of the Invention

[0006] The purpose of this application is to provide a method, apparatus, and medium for reducing the probability of read error correction failure by reducing the impact of initial voltage threshold offset.

[0007] To address the aforementioned technical problems, this application provides a method for reducing the probability of read error correction failure, comprising:

[0008] Obtain the operating temperature range and wear level range of the NAND flash memory;

[0009] The working temperature range is divided into a first preset number to generate multiple experimental temperature values;

[0010] The wear degree range is divided into a second preset number to generate multiple experimental wear values;

[0011] Arbitrarily combine the experimental temperature value and the experimental wear value, and collect the voltage offset value after the initial voltage threshold offset under each combination;

[0012] Select one of the voltage offset values ​​as the working voltage offset value;

[0013] Receive read task;

[0014] The read task is performed based on the operating voltage offset value and the default voltage value to read the NAND.

[0015] As a preferred embodiment, in the above method for reducing the probability of read error correction failure, the step of reading the NAND based on the above-mentioned operating voltage offset value includes:

[0016] Determine whether the address to be read in the read task is an open block;

[0017] If so, perform the read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0018] As a preferred embodiment, in the above method for reducing the probability of read error correction failure, if the address to be read in the read task is not an open block, the method further includes:

[0019] Determine whether the address to be read in the reading task is a block address in the preset latest closed block array;

[0020] If the address to be read in the read task is a block address in the preset latest closed block array, the read task is executed according to the default operating voltage to read the NAND.

[0021] Determine if the read was successful;

[0022] If the read operation fails, the read task is performed based on the operating voltage offset value and the default voltage value to read the NAND.

[0023] As a preferred solution, the above methods for reducing the probability of read error correction failure further include the following if the address to be read in the read task is not a block address in the preset latest closed block array:

[0024] The read task is performed based on the default operating voltage to read the NAND.

[0025] As a preferred embodiment, in the above method for reducing the probability of read error correction failure, selecting one of the voltage offset values ​​as the working voltage offset value includes:

[0026] The median of the voltage offset values ​​is selected as the operating voltage offset value.

[0027] As a preferred embodiment, in the above method for reducing the probability of read error correction failure, after performing the read task based on the operating voltage offset value and the default voltage value to read the NAND, the method further includes:

[0028] If reading the NAND fails, the error correction process will begin.

[0029] As a preferred option, the above methods for reducing the probability of read error correction failure also include:

[0030] When an open block is closed, its block address is written into the preset array of latest closed blocks;

[0031] If the number of blocks stored in the preset latest closed block array reaches the preset storage limit, the address of the block that was first written into the preset latest closed block array will be deleted.

[0032] To address the aforementioned technical problems, this application also provides an apparatus for reducing the probability of read error correction failure, comprising:

[0033] The acquisition module is used to acquire the operating temperature range and wear level range of the NAND flash memory.

[0034] The first division module is used to divide the working temperature range according to a first preset number of values ​​to generate multiple experimental temperature values.

[0035] The second division module is used to divide the wear degree range according to a second preset number of intervals to generate multiple experimental wear values;

[0036] The acquisition module is used to arbitrarily combine the experimental temperature value and the experimental wear value, and acquire the voltage offset value after the initial voltage threshold offset under each combination;

[0037] The selection module is used to select one of the voltage offset values ​​as the working voltage offset value;

[0038] The receiving module is used to receive reading tasks;

[0039] The read module is used to perform the read task based on the operating voltage offset value and the default voltage value, and to read the NAND.

[0040] The first judgment subunit is used to determine whether the address to be read in the reading task is an open block; if yes, the first reading subunit is triggered; if no, the second judgment subunit is triggered.

[0041] The first read subunit is used to perform the read task based on the operating voltage offset value and the default voltage value, and read the NAND.

[0042] The second judgment subunit is used to determine whether the address to be read in the reading task is a block address in the preset latest closed block array; if the address to be read in the reading task is a block address in the preset latest closed block array, the second reading subunit is triggered;

[0043] The second read subunit is used to perform the read task according to the default operating voltage and read the NAND;

[0044] The third judgment subunit is used to determine whether the reading was successful; if the reading was unsuccessful, the third reading subunit is triggered.

[0045] The third read subunit is used to perform the read task based on the operating voltage offset value and the default voltage value, and read the NAND.

[0046] The default module is used to perform the read task based on the default operating voltage, and to read the NAND.

[0047] The error correction module is used to initiate the error correction process if reading the NAND fails.

[0048] The storage module is used to write the block address of an open block to the preset array of latest closed blocks when the open block is closed.

[0049] The deletion module is used to delete the address of the earliest block written into the preset latest closed block array if the number of blocks stored in the preset latest closed block array reaches the preset number of blocks stored.

[0050] To address the aforementioned technical problems, this application also provides an apparatus for reducing the probability of read error correction failure, comprising:

[0051] Memory, used to store computer programs;

[0052] A processor, used to implement the steps of the method for reducing the probability of read error correction failure described above when executing the computer program.

[0053] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for reducing the probability of read error correction failure described above.

[0054] The method for reducing the probability of read error correction failure provided in this application includes: obtaining the operating temperature range and wear level range of the NAND; dividing the operating temperature range into a first preset number to generate multiple experimental temperature values; dividing the wear level range into a second preset number to generate multiple experimental wear values; arbitrarily combining the experimental temperature values ​​and experimental wear values, and collecting the voltage offset value after the initial voltage threshold offset under each combination; selecting one of the voltage offset values ​​as the operating voltage offset value; receiving a read task; and executing the read task based on the operating voltage offset value and the default voltage value to read the NAND. Since there is a certain probability of error correction failure when reading from CTF3D NAND chips during the initial voltage threshold offset stage, it is necessary to trigger error correction processes such as detection tables and software decoding, which will affect the performance of the SSD. Therefore, this application analyzes the impact of the initial voltage threshold offset of NAND by comprehensively considering the influence of temperature and wear factors on NAND, obtains a suitable operating voltage offset value, and calibrates the default voltage value using the operating voltage offset value when reading NAND to reduce the impact of the initial voltage threshold offset and thus reduce the probability of read error correction failure. This effectively increases the probability of successful NAND error correction on the first read, thus avoiding the need to enter the error correction process.

[0055] In addition, this application also provides an apparatus and a medium that correspond to the above method and have the same effect. Attached Figure Description

[0056] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A flowchart illustrating a method for reducing the probability of read error correction failure provided in an embodiment of this application;

[0058] Figure 2 A structural diagram of a device for reducing the probability of read error correction failure provided in an embodiment of this application;

[0059] Figure 3 This is a structural diagram of another device for reducing the probability of read error correction failure provided in an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0061] The core of this application is to provide a method, apparatus, and medium for reducing the probability of read error correction failure.

[0062] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] In the era of big data, the storage of massive amounts of data is becoming increasingly important. While the speed of computing components such as CPUs is constantly increasing, data storage and retrieval rates remain a system bottleneck. Currently, with the gradual decline in NAND flash memory prices, the number of solid-state drives (SSDs) in use is also increasing year by year. Unlike traditional hard drives, SSDs use NAND flash memory as their storage unit. The data storage capacity of NAND flash memory increases with the number of pre- and post-processing (PE) cycles, data read cycles, and data retention time, leading to a higher probability of read errors. This makes error handling a crucial component of SSDs. Due to the inherent characteristics of NAND, after read disturbances, write disturbances, or data retention, the charge stored in the physical blocks will change, increase, or be lost, resulting in hardware decoding failures and thus read errors during the data reading process.

[0064] Current error handling uses a test table provided by the NAND manufacturer for error correction to obtain correct user data. Specifically, it attempts to read data from the hard drive sequentially according to the read voltage values ​​in the test table provided by the NAND manufacturer. This method requires trying each read voltage in order in the test table until the data is successfully read. However, the test table includes a large number of read voltages, which increases the time consumed by the entire ERF (Error Recovery Flow) and reduces the hard drive's data reading efficiency.

[0065] In CTF 3D NAND (flash memory using a charge-fetching three-dimensional structure), a phenomenon exists where an initial voltage offset occurs within a very short time (100ms to 1s) after data is written to the NAND. This phenomenon is simply called initial voltage threshold offset. The degree to which NAND from different manufacturers is affected by initial voltage threshold offset varies slightly. If normal voltage is applied immediately after this, a high bit error rate (BER) will occur, and error correction may even fail. Initial voltage threshold offset is a significant factor affecting the reliability of NAND.

[0066] Based on the above problem analysis, this invention proposes a method that reduces the probability of error correction failure by minimizing the impact of initial voltage threshold offset while ensuring performance. Figure 1 A flowchart illustrating a method for reducing the probability of read error correction failure provided in an embodiment of this application is shown below. Figure 1 As shown, methods to reduce the probability of read error correction failure include:

[0067] S11: Obtain the operating temperature range and wear level range of the NAND flash memory;

[0068] S12: Divide the working temperature range according to the first preset number to generate multiple experimental temperature values;

[0069] S13: Divide the wear degree range according to the second preset number to generate multiple experimental wear values;

[0070] S14: Arbitrarily combine the experimental temperature value and the experimental wear value, and collect the voltage offset value after the initial voltage threshold offset under each combination.

[0071] S15: Select one of the voltage offset values ​​as the working voltage offset value;

[0072] S16: Receive read task;

[0073] S17: Perform a read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0074] In this embodiment, it is necessary to obtain the operating temperature range of the NAND flash memory. NAND flash memory supports an operating temperature range of -40℃ to +105℃. However, in actual operation, depending on the specific work content and environment, the operating temperature is often fixed within a certain range. This embodiment does not limit the range of the NAND flash memory's operating temperature range; it can be set according to the actual working environment. The operating temperature range is then divided into multiple experimental temperature values ​​according to a first preset number. The experimental temperature values ​​mentioned in this embodiment can be fixed individual temperature values ​​or a range of temperature values, depending on actual needs. For example, the commonly used operating temperature range for NAND flash memory is 40℃ to 70℃, which can be divided into three segments in 10℃ increments. This embodiment does not limit the specific value of the first preset number; it can be set according to actual needs.

[0075] In this embodiment, it is necessary to obtain the wear level range of the NAND flash memory, i.e., the wear rating of the NAND flash memory. Each page of the NAND flash memory includes an additional storage space, which is a 64-byte free area (16 bytes per 512-byte sector). This area can store error correction code (ECC) codes and other information such as wear ratings or logic-to-physical block mappings. The wear level range is divided into multiple experimental wear values ​​according to a second preset number. For example, the NAND wear stage is 0-7K, divided into seven segments of 1K units. This embodiment does not limit the specific value of the second preset number; it can be set according to actual needs.

[0076] It should be noted that steps S12 and S13 are not sequential and can be performed simultaneously.

[0077] Arbitrarily combine the experimental temperature value and the experimental wear value, and collect the voltage offset value after the initial voltage threshold shift under each combination. The experimental temperature value and experimental wear value after the above division are used as experimental conditions for collecting voltage offset values. In addition, preferably, multiple logical unit numbers (LUNs) are selected to collect the voltage offset value after the initial voltage threshold shift under each combination.

[0078] For example, the commonly used operating temperature range of NAND is 40℃~70℃, which can be divided into three segments in 10℃ increments. The NAND wear stage is 0~7K, which can be divided into seven segments in 1K increments, resulting in a total of 21 combinations. A voltage offset table was collected from 30 LUNs under the above combinations after the initial voltage threshold offset.

[0079] The collected voltage offset values ​​were analyzed, and one of them was selected as the working voltage offset value. Since these offset voltages are relatively close, the median of the collected voltage offset data was chosen as the working voltage offset value.

[0080] If a read task is received, the default voltage value can be calibrated using the working voltage offset value to reduce the impact of the initial voltage threshold offset and thus reduce the probability of read error correction failure.

[0081] The specific reading process involves first sending the read task identifier to the Flash Channel Controller (FCC), and then the FCC reads the NAND based on the voltage value.

[0082] Flash Channel Controller: Each channel corresponds to a flash channel controller. Based on the unique structural characteristics of flash memory, multiple FCC parallel technologies are used in the design of solid-state drives to realize concurrent read and write operations of multi-channel data, thus effectively improving the overall read and write performance of solid-state drives.

[0083] The method for reducing the probability of read error correction failure provided in this embodiment includes: obtaining the operating temperature range and wear level range of the NAND; dividing the operating temperature range into a first preset number to generate multiple experimental temperature values; dividing the wear level range into a second preset number to generate multiple experimental wear values; arbitrarily combining the experimental temperature values ​​and the experimental wear values, and collecting the voltage offset value after the initial voltage threshold offset under each combination; selecting one of the voltage offset values ​​as the operating voltage offset value; receiving a read task; and executing the read task according to the operating voltage offset value and the default voltage value to read the NAND. Since there is a certain probability of error correction failure when reading on CTF 3D NAND chips during the initial voltage threshold offset stage, it is necessary to trigger error correction processes such as detection tables and software decoding, which will affect the performance of the SSD. Therefore, this application analyzes the impact of the initial voltage threshold offset of NAND by comprehensively considering the influence of temperature and wear factors on NAND, obtains a suitable operating voltage offset value, and calibrates the default voltage value using the operating voltage offset value when reading NAND to reduce the impact of the initial voltage threshold offset and thus reduce the probability of read error correction failure. This effectively increases the probability of successful NAND error correction on the first read, thus avoiding the need to enter the error correction process.

[0084] According to the above embodiments, reading open blocks is more likely to be affected by the initial voltage threshold offset. Therefore, this embodiment provides a preferred solution to reduce the probability of read error correction failure. The step of performing the read task based on the working voltage offset value and the default voltage value to read the NAND includes:

[0085] Determine whether the address to be read in the read task is an open block;

[0086] If so, perform the read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0087] In this embodiment, it is first determined whether the address to be read in the read task is an open block; if so, the read task is executed according to the working voltage offset value and the default voltage value to read the NAND. The default voltage value is calibrated by the working voltage offset value to reduce the impact of the initial voltage threshold offset and reduce the probability of read error correction failure, effectively increasing the probability of successful NAND error correction on the first read, that is, avoiding entering the error correction process.

[0088] According to the above embodiments, even a newly closed block may be affected by the initial voltage threshold offset. Therefore, this embodiment provides a preferred solution to reduce the probability of read error correction failure. If the address to be read in the read task is not an open block, the method further includes:

[0089] Determine whether the address to be read in the reading task is a block address in the preset latest closed block array;

[0090] If the address to be read in the read task is a block address in the preset latest closed block array, the read task is executed according to the default operating voltage to read the NAND;

[0091] Determine if the read was successful;

[0092] If the read operation fails, the read task is performed based on the operating voltage offset value and the default voltage value to read the NAND.

[0093] If the address to be read in the reading task is not an open block, then it is determined whether it is a block address in the preset latest closed block array. The preset latest closed block array mentioned in this embodiment refers to a value preset according to user needs, used to store the latest closed blocks. This value can limit the maximum number stored, or it can be set according to the closing time, depending on actual needs.

[0094] If the address to be read in the read task is a block address in the latest closed block array, the NAND is first read according to the default operating voltage. If the read fails, the read task is then performed using the operating voltage offset value and the default voltage value to read the NAND. The default voltage value is calibrated by the operating voltage offset value to reduce the impact of the initial voltage threshold offset and reduce the probability of read error correction failure. This effectively increases the probability of successful NAND error correction on the first read, thus avoiding entering the error correction process.

[0095] If the address to be read in the reading task is not a block address in the preset latest closed block array, then it also includes:

[0096] The read task is performed based on the default operating voltage to read the NAND.

[0097] If the address to be read in the read task is not a block address in the preset latest closed block array, that is, a block that has been closed for a period of time, the probability of initial voltage threshold offset during reading is very low. Therefore, the read task is executed directly using the default operating voltage to read NAND, which effectively improves the probability of successful NAND error correction on the first read.

[0098] According to the above embodiments, even after calibration, NAND read failure may still occur. Therefore, the method for reducing the probability of read error correction failure includes, after performing the read task based on the operating voltage offset value and the default voltage value to read the NAND, further comprising:

[0099] If reading the NAND fails, the error correction process will begin.

[0100] Error correction is performed using a test table provided by the NAND manufacturer to obtain correct user data. Specifically, this involves attempting to read data from the hard drive sequentially according to the read voltage values ​​in the test table provided by the NAND manufacturer. This method requires trying each read voltage in the order listed in the test table until the data is successfully read.

[0101] According to the above embodiments, the preset latest closed block array can be limited by quantity or by time. If a fixed quantity is used, this embodiment provides a preferred solution to reduce the probability of read error correction failure, which further includes:

[0102] When an open block is closed, its block address is written into the preset array of latest closed blocks;

[0103] If the number of blocks stored in the preset latest closed block array reaches the preset storage limit, the address of the block that was first written into the preset latest closed block array will be deleted.

[0104] For each open block that is closed, its block address is written into a preset array of the latest closed blocks. If the array reaches its maximum capacity, the oldest stored block address is deleted. Subsequently, when storing the address of the latest closed block, the oldest stored block address is deleted at the same time.

[0105] To enable those skilled in the art to understand this solution efficiently, a specific embodiment is provided below:

[0106] S11: Obtain the operating temperature range and wear level range of the NAND flash memory;

[0107] S12: Divide the working temperature range according to the first preset number to generate multiple experimental temperature values;

[0108] S13: Divide the wear degree range according to the second preset number to generate multiple experimental wear values;

[0109] S14: Arbitrarily combine the experimental temperature value and the experimental wear value, and collect the voltage offset value after the initial voltage threshold offset under each combination.

[0110] S15: Select one of the voltage offset values ​​as the working voltage offset value;

[0111] S16: Receive read task;

[0112] S171: Determine whether the address to be read in the reading task is an open block; if yes, proceed to S172; if no, proceed to S173.

[0113] S172: Execute the read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0114] S173: Determine whether the address to be read in the reading task is a block address in the preset latest closed block array; if so, proceed to S174:

[0115] S174: Execute the read task according to the default operating voltage to read the NAND;

[0116] S175: Determine if the read was successful; if the read was unsuccessful, proceed to S176.

[0117] S176: Execute the read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0118] S18: If reading the NAND fails, proceed with the error correction process.

[0119] This application analyzes the impact of temperature and wear factors on NAND flash memory, determining the degree of initial voltage threshold offset to obtain a suitable operating voltage offset value. During NAND reading, the default voltage value is calibrated using this operating voltage offset value to reduce the impact of the initial voltage threshold offset and lower the probability of read error correction failure. This effectively increases the probability of successful NAND read error correction on the first attempt, thus avoiding the need to enter the error correction process.

[0120] In the above embodiments, the method for reducing the probability of read error correction failure has been described in detail. This application also provides embodiments of a device for reducing the probability of read error correction failure. It should be noted that this application describes the embodiments of the device from two perspectives: one is based on functional modules, and the other is based on hardware.

[0121] From the perspective of functional modules Figure 2 A structural diagram of a device for reducing the probability of read error correction failure provided in an embodiment of this application is shown below. Figure 2As shown, the apparatus for reducing the probability of read error correction failure includes:

[0122] Module 21 is used to acquire the operating temperature range and wear level range of the NAND flash memory.

[0123] The first division module 22 is used to divide the working temperature range according to a first preset number of values ​​to generate multiple experimental temperature values.

[0124] The second division module 23 is used to divide the wear degree range according to a second preset number of intervals to generate multiple experimental wear values;

[0125] The acquisition module 24 is used to arbitrarily combine the experimental temperature value and the experimental wear value, and acquire the voltage offset value after the initial voltage threshold offset under each combination.

[0126] Selection module 25 is used to select one of the voltage offset values ​​as the working voltage offset value;

[0127] Receiver module 26 is used to receive read tasks;

[0128] The read module 27 is used to perform the read task based on the operating voltage offset value and the default voltage value to read the NAND.

[0129] Specifically, the acquisition module 21 acquires the operating temperature range and wear level range of the NAND flash memory; the first division module 22 divides the operating temperature range into a first preset number of values, generating multiple experimental temperature values; the second division module 23 divides the wear level range into a second preset number of values, generating multiple experimental wear values; the acquisition module 24 arbitrarily combines the experimental temperature values ​​and the experimental wear values, acquiring the voltage offset value after the initial voltage threshold offset under each combination; the selection module 25 selects one of the voltage offset values ​​as the operating voltage offset value; the receiving module 26 receives the read task; and the reading module 27 executes the read task based on the operating voltage offset value and the default voltage value, reading the NAND flash memory. Since there is a certain probability of error correction failure when reading from the initial voltage threshold offset stage on CTF 3D NAND flash memory, it is necessary to trigger error correction processes such as detection tables and software decoding, which will affect the performance of the SSD. Therefore, this application analyzes the impact of temperature and wear factors on NAND flash memory, determines the degree of initial voltage threshold offset, and obtains a suitable operating voltage offset value. During NAND flash memory reading, the default voltage value is calibrated using this operating voltage offset value to reduce the impact of the initial voltage threshold offset and thus lower the probability of read error correction failure. This effectively increases the probability of successful NAND flash memory error correction on the first read, thus avoiding the need to enter the error correction process.

[0130] In addition, it also includes:

[0131] The first judgment subunit is used to determine whether the address to be read in the reading task is an open block; if yes, the first reading subunit is triggered; if no, the second judgment subunit is triggered.

[0132] The first read subunit is used to perform the read task based on the operating voltage offset value and the default voltage value, and read the NAND.

[0133] The second judgment subunit is used to determine whether the address to be read in the reading task is a block address in the preset latest closed block array; if the address to be read in the reading task is a block address in the preset latest closed block array, the second reading subunit is triggered;

[0134] The second read subunit is used to perform the read task according to the default operating voltage and read the NAND;

[0135] The third judgment subunit is used to determine whether the reading was successful; if the reading was unsuccessful, the third reading subunit is triggered.

[0136] The third read subunit is used to perform the read task based on the operating voltage offset value and the default voltage value, and read the NAND.

[0137] The default module is used to perform the read task based on the default operating voltage, and to read the NAND.

[0138] The error correction module is used to initiate the error correction process if reading the NAND fails.

[0139] The storage module is used to write the block address of an open block to the preset array of latest closed blocks when the open block is closed.

[0140] The deletion module is used to delete the address of the earliest block written into the preset latest closed block array if the number of blocks stored in the preset latest closed block array reaches the preset number of blocks stored.

[0141] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0142] Figure 3 A structural diagram of another device for reducing the probability of read error correction failure provided in an embodiment of this application is shown below. Figure 3 As shown, the device for reducing the probability of read error correction failure includes: a memory 30 for storing computer programs;

[0143] The processor 31 is configured to implement, when executing a computer program, the steps of the method for obtaining user operation habit information as described in the above embodiment (method for reducing the probability of read error correction failure).

[0144] The device for reducing the probability of read error correction failure provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0145] The processor 31 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 31 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 31 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 31 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 31 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0146] The memory 30 may include one or more computer-readable storage media, which may be non-transitory. The memory 30 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 30 is used to store at least the following computer program 301, which, after being loaded and executed by the processor 31, is capable of implementing the relevant steps of the method for reducing the probability of read error correction failure disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 30 may also include an operating system 302 and data 303, and the storage method may be temporary storage or permanent storage. The operating system 302 may include Windows, Unix, Linux, etc. The data 303 may include, but is not limited to, data involved in implementing the method for reducing the probability of read error correction failure.

[0147] In some embodiments, the device for reducing the probability of read error correction failure may further include a display screen 32, an input / output interface 33, a communication interface 34, a power supply 35, and a communication bus 36.

[0148] Those skilled in the art will understand that Figure 3The structure shown does not constitute a limitation on the means of reducing the probability of read error correction failure, and may include more or fewer components than shown.

[0149] The apparatus for reducing the probability of read error correction failure provided in this application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a method for reducing the probability of read error correction failure, including: obtaining the operating temperature range and wear level range of the NAND; dividing the operating temperature range into a first preset number to generate multiple experimental temperature values; dividing the wear level range into a second preset number to generate multiple experimental wear values; arbitrarily combining the experimental temperature values ​​and the experimental wear values, and collecting voltage offset values ​​after initial voltage threshold offset under each combination; selecting one of the voltage offset values ​​as the operating voltage offset value; receiving a read task; and executing the read task according to the operating voltage offset value and a default voltage value to read the NAND. Since there is a certain probability of error correction failure when reading on CTF 3D NAND chips during the initial voltage threshold offset stage, error correction processes such as detection tables and software decoding need to be triggered, which will affect the performance of the SSD. Therefore, this application analyzes the impact of temperature and wear factors on NAND flash memory, determines the degree of initial voltage threshold offset, and obtains a suitable operating voltage offset value. During NAND flash memory reading, the default voltage value is calibrated using this operating voltage offset value to reduce the impact of the initial voltage threshold offset and thus lower the probability of read error correction failure. This effectively increases the probability of successful NAND flash memory error correction on the first read, thus avoiding the need to enter the error correction process.

[0150] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above embodiment of the method for reducing the probability of read error correction failure.

[0151] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0152] The computer-readable storage medium provided in this embodiment stores a computer program. When the processor executes the program, it can implement the following method: a method to reduce the probability of read error correction failure, including: obtaining the operating temperature range and wear level range of the NAND; dividing the operating temperature range into a first preset number to generate multiple experimental temperature values; dividing the wear level range into a second preset number to generate multiple experimental wear values; arbitrarily combining the experimental temperature values ​​and the experimental wear values, and collecting the voltage offset value after the initial voltage threshold offset under each combination; selecting one of the voltage offset values ​​as the operating voltage offset value; receiving a read task; and executing the read task according to the operating voltage offset value and the default voltage value to read the NAND. Since there is a certain probability of error correction failure when reading on CTF 3D NAND chips during the initial voltage threshold offset stage, it is necessary to trigger error correction processes such as detection tables and software decoding, which will affect the performance of the SSD. Therefore, this application analyzes the impact of temperature and wear factors on NAND flash memory, determines the degree of initial voltage threshold offset, and obtains a suitable operating voltage offset value. During NAND flash memory reading, the default voltage value is calibrated using this operating voltage offset value to reduce the impact of the initial voltage threshold offset and thus lower the probability of read error correction failure. This effectively increases the probability of successful NAND flash memory error correction on the first read, thus avoiding the need to enter the error correction process.

[0153] The method, apparatus, and medium for reducing the probability of read error correction failure provided in this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0154] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for reducing the probability of read error correction failure, characterized in that, include: Obtain the operating temperature range and wear level range of the NAND flash memory; The working temperature range is divided into a first preset number to generate multiple experimental temperature values; The wear degree range is divided into a second preset number to generate multiple experimental wear values; Arbitrarily combine the experimental temperature value and the experimental wear value, and collect the voltage offset value after the initial voltage threshold offset under each combination; Select one of the voltage offset values ​​as the working voltage offset value; Receive read task; The read task is performed based on the operating voltage offset value and the default voltage value to read the NAND; Correspondingly, the step of performing the read task based on the operating voltage offset value and the default voltage value to read the NAND includes: Determine whether the address to be read in the read task is an open block; If so, perform the read task based on the operating voltage offset value and the default voltage value to read the NAND; Correspondingly, if the address to be read in the reading task is not an open block, then it also includes: Determine whether the address to be read in the reading task is a block address in the preset latest closed block array; If the address to be read in the read task is a block address in the preset latest closed block array, the read task is executed according to the default operating voltage to read the NAND; Determine if the read was successful; If the read operation fails, the read task is performed based on the operating voltage offset value and the default voltage value to read the NAND.

2. The method for reducing the probability of read error correction failure according to claim 1, characterized in that, If the address to be read in the reading task is not a block address in the preset latest closed block array, then it also includes: The read task is performed based on the default operating voltage to read the NAND.

3. The method for reducing the probability of read error correction failure according to claim 1, characterized in that, Selecting one of the voltage offset values ​​as the operating voltage offset value includes: The median of the voltage offset values ​​is selected as the operating voltage offset value.

4. The method for reducing the probability of read error correction failure according to claim 1, characterized in that, The step of performing the read task based on the operating voltage offset value and the default voltage value to read the NAND flash memory further includes: If reading the NAND fails, the error correction process will begin.

5. The method for reducing the probability of read error correction failure according to claim 1, characterized in that, Also includes: When an open block is closed, its block address is written into the preset array of latest closed blocks; If the number of blocks stored in the preset latest closed block array reaches the preset storage limit, the address of the block that was first written into the preset latest closed block array will be deleted.

6. A device for reducing the probability of read error correction failure, characterized in that, include: The acquisition module is used to acquire the operating temperature range and wear level range of the NAND flash memory. The first division module is used to divide the working temperature range according to a first preset number of values ​​to generate multiple experimental temperature values. The second division module is used to divide the wear degree range according to a second preset number of intervals to generate multiple experimental wear values; The acquisition module is used to arbitrarily combine the experimental temperature value and the experimental wear value, and acquire the voltage offset value after the initial voltage threshold offset under each combination; The selection module is used to select one of the voltage offset values ​​as the working voltage offset value; The receiving module is used to receive reading tasks; The read module is used to perform the read task based on the operating voltage offset value and the default voltage value, and to read the NAND flash memory. Correspondingly, the step of performing the read task based on the operating voltage offset value and the default voltage value to read the NAND includes: Determine whether the address to be read in the read task is an open block; If so, perform the read task based on the operating voltage offset value and the default voltage value to read the NAND; Correspondingly, if the address to be read in the reading task is not an open block, then it also includes: Determine whether the address to be read in the reading task is a block address in the preset latest closed block array; If the address to be read in the read task is a block address in the preset latest closed block array, the read task is executed according to the default operating voltage to read the NAND; Determine if the read was successful; If the read operation fails, the read task is performed based on the operating voltage offset value and the default voltage value to read the NAND.

7. A device for reducing the probability of read error correction failure, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for reducing the probability of read error correction failure as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for reducing the probability of read error correction failure as described in any one of claims 1 to 5.

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