Non-volatile memory and voltage detection circuit therefor

Abstract

The present invention is a non-volatile memory and a voltage detection circuit thereof. When an inactive standby signal is received, a power supply unit of the non-volatile memory generates an array voltage to a first node. The voltage detection circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected to a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected to the second node, and an output terminal of the latch is connected to a third node. An input terminal of the combinational logic circuit is connected to the third node, and an output terminal of the combinational logic circuit generates the enable signal.

Description

Technical Field

[0001] This invention relates to a non-volatile memory and its internal circuitry, and particularly to a non-volatile memory capable of operating in idle mode and its associated voltage detection circuitry. Background Technology

[0002] As is well known, non-volatile memory is widely used in various electronic products. In low-power electronic products, non-volatile memory enters idle mode to prevent excessive power consumption.

[0003] Please refer to Figure 1 The diagram illustrates a non-volatile memory in a known electronic product. The non-volatile memory 100 includes a memory module 120, a processing unit 112, and a power supply unit 114. The memory module 120 includes a drive circuit 122 and a memory array 124.

[0004] Non-volatile memory 100 is connected to a host 180 and receives a supply voltage V. DD For example, the battery in an electronic product provides a supply voltage V. DD This allows the non-volatile memory 100 to receive the supplied voltage V. DD And it operates.

[0005] Processing unit 112 is connected to host 180 and memory module 120. When non-volatile memory 100 is in normal mode, processing unit 112 receives access command from host 180 and generates control signal Ctrl to access data in memory module 120.

[0006] Furthermore, the power supply unit 114 will supply voltage V DD Converted to array voltage V ARRAY The data is then transmitted to the drive circuit 122 of the memory module 120. For example, the drive circuit 122 includes at least one word line driver. The word line driver receives the array voltage V. ARRAY Furthermore, the word line drivers are connected to multiple word lines WL1~WLn of the memory array 124.

[0007] When the processing unit 112 accesses data in the memory module 120, the word line driver applies the array voltage V.ARRAY It is converted to word line voltage and driven by a specific word line in the memory array 124 according to the control signal Ctrl.

[0008] After a certain period of inactivity between the host 180 and the non-volatile memory 100, the non-volatile memory 100 switches to idle mode. In idle mode, the processing unit 112 asserts the standby signal (STB) and maintains a small portion of its internal circuitry. Meanwhile, the power supply unit 114 stops operating based on the STB. Therefore, the power supply unit 114 stops generating the array voltage V. ARRAY This causes the memory module 120 to also stop operating.

[0009] When the host 180 accesses the non-volatile memory 100 again, the non-volatile memory 100 will switch from idle mode to normal mode again. At this time, the processing unit 112 deasserts the standby signal STB, and the power supply unit 114 will restart and generate the array voltage V. ARRAY .

[0010] However, due to the excessively long startup time of the power supply unit 114, the array voltage V... ARRAY Not yet ready; drive circuit 122 cannot receive array voltage V in time. ARRAY To quickly drive the word lines. That is, when the non-volatile memory 100 switches from idle mode to normal mode, the power supply unit 114 cannot immediately supply the array voltage V. ARRAY This will cause the processing unit 112 to be unable to access the data in the memory module 120 in a timely manner, resulting in a decrease in the access efficiency (performance) of the non-volatile memory 100.

[0011] To address the shortcoming of the processing unit 112's inability to immediately access the memory module 120 during the initial transition of the non-volatile memory 100 from idle mode to normal mode, a feature can be designed in the non-volatile memory 100 that has a short startup time and can quickly prepare the array voltage V. ARRAY The power supply unit 114.

[0012] However, the power supply unit 114 includes at least a bandgap reference circuit, a voltage regulator, and a charge pump. In order to shorten the startup time of the power supply unit 114, the required charge pump size would be very large, occupying a large layout area of ​​the power supply unit 114.

[0013] Please refer to Figure 2 The diagram shown is a schematic of another known non-volatile memory. Compared to Figure 1 The non-volatile memory 100 and the non-volatile memory 200 also include an auxiliary power supply unit 210.

[0014] Auxiliary power supply unit 210 receives supply voltage V DD And the standby signal STB, and generate array voltage V. ARRAY In normal mode, the standby signal STB is invalid, the auxiliary power supply unit 210 is not operational, and the array voltage V is generated by the power supply unit 114. ARRAY In idle mode, the standby signal STB is active, the power supply unit 114 is not operational, and the array voltage V is generated by the auxiliary power supply unit 210. ARRAY .

[0015] As described above, regardless of whether it is in idle mode or normal mode, the memory module 120 in the non-volatile memory 200 can receive the array voltage V. ARRAY Therefore, when the non-volatile memory 200 switches from idle mode to normal mode, since the memory module 120 has already received the array voltage V... ARRAY Therefore, the processing unit 112 can immediately access the data in the memory module 120.

[0016] However, adding an auxiliary power supply unit 210 to the non-volatile memory 200 also increases the layout area and generates additional power consumption. Summary of the Invention

[0017] This invention relates to a non-volatile memory, comprising: a processing unit that generates a standby signal; a power supply unit connected to a first node, the power supply unit receiving the standby signal, wherein when the standby signal is invalid, the power supply unit converts a supply voltage into an array voltage of a first value and outputs the array voltage to the first node, and when the standby signal is valid, the power supply unit stops generating the array voltage; a voltage detection circuit connected to the first node and receiving the standby signal, wherein when the standby signal is valid, the voltage detection circuit detects the array voltage on the first node; and a memory module connected to the first node and receiving the array voltage; wherein when the array voltage decreases from the first value to a second value, the voltage detection circuit effectively enables a power signal to enable the processing unit, causing the processing unit to invalidate the standby signal; wherein when the array voltage increases from the second value to the first value, the processing unit enables the standby signal, and the voltage detection circuit invalidates the power signal.

[0018] This invention relates to a voltage detection circuit in a non-volatile memory. The non-volatile memory includes a power supply unit connected to a first node. When a standby signal is invalid, the power supply unit outputs an array voltage of a first value to the first node. When the standby signal is valid, the power supply unit stops outputting the array voltage. The voltage detection circuit includes: an initial voltage generator that receives an inverted standby signal and an enable signal, and an output terminal of the initial voltage generator is connected to a second node; a capacitor, with a first terminal coupled to the first node and a second terminal coupled to the second node; a latch, with an input terminal connected to the second node and an output terminal connected to a third node, a first power supply terminal of the latch coupled to a supply voltage, and a second power supply terminal coupled to a ground terminal; and a combinational logic circuit, with an input terminal connected to the third node and an output terminal of the combinational logic circuit generating the enable signal.

[0019] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0020] Figure 1 A schematic diagram of a known non-volatile memory in an electronic product;

[0021] Figure 2 This is a schematic diagram of another known non-volatile memory;

[0022] Figure 3A and Figure 3BThis is a schematic diagram of the non-volatile memory and related signals of the present invention;

[0023] Figure 4A This is a schematic diagram of the voltage detection circuit of the present invention;

[0024] Figure 4B for Figure 4A Schematic diagram of relevant signals in the voltage detection circuit;

[0025] Figure 5 This shows the detailed structure of the voltage detection circuit;

[0026] Figure 6A This is a schematic diagram of the voltage detection circuit operating during charging.

[0027] Figure 6B This is a schematic diagram of the voltage detection circuit during the initial stage of detection.

[0028] Figure 6C A schematic diagram of the voltage detection circuit operating in the later stages of the detection period; and

[0029] Figure 6D for Figure 5 A schematic diagram of the relevant signals of the voltage detection circuit.

[0030] [Symbol Explanation]

[0031] 100, 200, 300: Non-volatile memory

[0032] 112, 312: Processing Units

[0033] 114, 314: Power supply unit

[0034] 120, 320: Memory modules

[0035] 122, 322: Drive circuit

[0036] 124, 324: Memory array

[0037] 180, 380: Host

[0038] 210: Auxiliary power supply unit

[0039] 330: Voltage detection circuit

[0040] 400: Initial Voltage Generator

[0041] 410: Latch

[0042] 420: Combinational Logic Circuits

[0043] 422: NOT gate

[0044] 426: NAND gate Detailed Implementation

[0045] Please refer to Figure 3A and Figure 3B The diagram illustrates the non-volatile memory and related signals of the present invention. The non-volatile memory 300 is connected to a host 380, which can generate access commands to the non-volatile memory 300 to access data within it. Detailed operation of this process will not be elaborated further.

[0046] The non-volatile memory 300 includes a memory module 320, a processing unit 312, a power supply unit 314, and a voltage detection circuit 330. The memory module 320 includes a drive circuit 322 and a memory array 324. The non-volatile memory 300 receives a supply voltage V. DD For example, the battery in an electronic product provides a supply voltage V. DD This allows the non-volatile memory 300 to receive the supplied voltage V. DD And it operates.

[0047] The power supply unit 314 will supply voltage V DD Converted to array voltage V ARRAY The output of power supply unit 314 is connected to node a. For example, power supply unit 314 supplies a 3.3V supply voltage V. DD Converted to 9V array voltage V ARRAY .

[0048] Additionally, the drive circuit 322 of the memory module 320 is connected to node a, causing the array voltage V to... ARRAY A drive circuit 322 can be transmitted to the memory module 320. For example, the drive circuit 322 includes at least one word line driver (not shown). The word line driver receives the array voltage V. ARRAY Furthermore, the word line drivers are connected to multiple word lines WL1~WLn of the memory array 324.

[0049] When the non-volatile memory 300 is in normal mode, the processing unit 312 can generate a control signal Ctrl to access data in the memory module 320. Furthermore, when the processing unit 312 accesses data in the memory module 320, the word line driver will adjust the array voltage V. ARRAY It is converted to word line voltage and driven by the control signal Ctrl to drive a specific word line in the memory array 324.

[0050] When the non-volatile memory 300 enters idle mode, the processing unit 312 switches to standby state and asserts the standby signal STB. At this time, only a small portion of the circuitry within the processing unit 312 is operational. Additionally, the power supply unit 314 stops operating based on the standby signal STB, thus ceasing to generate the array voltage V. ARRAY In other words, when the standby signal STB is valid, the power supply unit 314 stops generating the array voltage V. ARRAY Therefore, the array voltage V at node a ARRAY Gradually decreasing.

[0051] According to an embodiment of the present invention, the voltage detection circuit 330 is connected to node a and receives a standby signal STB. When the standby signal STB is valid, it indicates that the processing unit 312 has switched to a standby state, and the voltage detection circuit 330 begins to detect the array voltage V on node a. ARRAY When the standby signal STB is invalid, it indicates that the processing unit 312 has left the standby state, and the voltage detection circuit 330 has not detected the array voltage V on node a. ARRAY .

[0052] like Figure 3B As shown, when the non-volatile memory 300 is in idle mode, the array voltage V on node a is... ARRAY It will vary between the first value V1 and the second value V2. That is, the first value V1 is the array voltage V. ARRAY The maximum value, and the second value V2 is the array voltage V. ARRAY The minimum value. Wherein, the first value V1 is the array voltage V generated by the power supply unit 314. ARRAY The first value is the stable value, and the second value, V2, is the array voltage V. ARRAY The low threshold value. For example, the array voltage V. ARRAY The resulting stable value is 9V, and the array voltage V ARRAY The lower threshold value is 8.7V, that is, the first value V1 is 9V and the second value V2 is 8.7V.

[0053] At time point ta, the array voltage V ARRAYThe voltage drops and reaches the second value V2. At this time, the voltage detection circuit 330 asserts the enable signal EN and switches the enable signal EN to a logic high level to enable the processing unit 312. Therefore, the processing unit 312 is enabled and leaves the standby state. Therefore, the processing unit 312 deasserts the standby signal STB and switches the standby signal STB to a logic low level.

[0054] The period from time point ta to time point tb is the charging period T. CHG Processing unit 312 exits standby mode, and the standby signal STB remains at a logic low level, while the enable signal remains at a logic high level. Since the standby signal STB is at a logic low level, power supply unit 314 operates and charges node a. Therefore, the array voltage V on node a... ARRAY It rises, from the lowest second value V2 to the highest first value V1.

[0055] At time point tb, the array voltage V ARRAY Upon reaching the first value V1, the processing unit 312 switches back to standby mode. At this time, the processing unit 312 enables the standby signal STB, switching it to a logic high level, causing the power supply unit 314 to stop operating. Additionally, the voltage detection circuit 330 disables the enable signal EN, switching it to a logic low level, and begins detecting the array voltage V on node a. ARRAY .

[0056] The period from time point tb to time point tc is the detection period T. DET The standby signal STB remains at a logic high level, and the enable signal EN remains at a logic low level. Therefore, the array voltage V ARRAY The value decreases from the highest first value V1 to the lowest second value V2. In other words, during the detection period T... DET The voltage detection circuit 330 continuously detects the array voltage V on node a. ARRAY .

[0057] At time point tc, the array voltage V ARRAYThe voltage drops to the second value V2. At this time, the voltage detection circuit 330 asserts the enable signal EN and switches the enable signal EN to a logic high level to enable the processing unit 312. Therefore, the processing unit 312 deasserts the standby signal STB and switches the standby signal STB to a logic low level, causing the processing unit 312 to leave the standby state. The period from time point tc to time point td is another charging period. During the charging cycle from time point tc to time point td, the array voltage V... ARRAY It rose again to the first value, V1.

[0058] As can be seen from the above description, when the non-volatile memory 300 of the present invention is in idle mode, the voltage detection circuit 330 can detect the array voltage V on the output terminal of the power supply unit 314. ARRAY Size. During the detection period T DET When the array voltage V ARRAY When the voltage drops to the second value V2, the voltage detection circuit 330 enables the enable signal EN, causing the processing unit 312 to leave the standby state and enter the charging period T. CHG During charging, T CHG The voltage supply unit 314 generates the array voltage V. ARRAY This makes the array voltage V ARRAY The value increases from the second value V2 to the first value V1. After that, the processing unit 312 enters standby mode again and enters another detection period.

[0059] In other words, when the non-volatile memory 300 of the present invention is in idle mode, it uses the voltage detection circuit 330 to detect the array voltage V. ARRAY Size, and control array voltage V ARRAY It remains within a specific range. Therefore, when the non-volatile memory 300 switches from idle mode to normal mode, since the memory module 320 has already received the array voltage V... ARRAY Therefore, the processing unit 312 can access the data in the memory module 320 in real time, which can greatly improve the access performance of the non-volatile memory 300.

[0060] Additionally, during charging, T CHG The processing unit 312 leaves the standby state. At this time, the processing unit 312 will confirm the array voltage V. ARRAY After rising to the first value V1, it enters standby mode again. For example, processing unit 312 can directly receive array voltage V. ARRAY And determine the array voltage V ARRAY Has the first value V1 been reached? When the array voltage V ARRAYWhen the first value V1 is reached, the processing unit 312 asserts the standby signal STB and enters the standby state.

[0061] Alternatively, the processing unit 312 can determine the array voltage V based on the startup time of the power supply unit 314. ARRAY Whether the first value V1 has been reached. For example, the restart time of the power supply unit 314 is approximately 1.5 μs. That is, 1.5 μs after startup, the array voltage V generated by the power supply unit 314... ARRAY A stable first value V1 can be reached. Therefore, the processing unit 312 can assert the standby signal STB and enter the standby state after the enable signal EN has been valid for more than 1.5 μs (for example, when the enable signal EN has been valid for 2.0 μs).

[0062] Of course, the present invention does not limit the processing unit 312 to determine the array voltage V. ARRAY Whether the first value V1 has been reached. That is, when the array voltage V... ARRAY When the first value V1 is reached, the processing unit 312 makes the standby signal STB valid and enters the standby state.

[0063] Furthermore, in the above description, when the processing unit 312 asserts the standby signal STB, it switches the standby signal STB from a logic low level to a logic high level; when the processing unit 312 deasserts the standby signal STB, it switches the standby signal STB from a logic high level to a logic low level. Of course, this invention is not limited thereto, and those skilled in the art can define the logic level of the standby signal STB themselves. Similarly, those skilled in the art can also define the logic level of the enable signal EN according to actual requirements.

[0064] Furthermore, the present invention is not limited to the array voltage V. ARRAY The first value V1 and the second value V2. For example, a person skilled in the art can design the power supply unit 314 and provide other array voltages V based on the characteristics of the memory array 324 in the memory module 320. ARRAY (e.g., 12V), to drive circuit 322, and define array voltage V. ARRAY The first value V1 and the second value V2 are 12V and 11.5V, respectively.

[0065] Please refer to Figure 4AThe diagram shown is a schematic of the voltage detection circuit of the present invention. The voltage detection circuit 330 includes: a NOT gate 430, an initial voltage generator 400, a latch 410, a capacitor C, transistors M1, M2, and Ma, and combinational logic circuit 420. Transistor M1 is a P-type transistor, while transistors M2 and Ma are N-type transistors.

[0066] The NOT gate 430 receives the standby signal STB at its input and generates an inverted standby signal STB at its output. b Of course, NOT gate 430 can also be designed within processing unit 312, so that processing unit 312 generates complementary standby signals STB and inverted standby signals STB. b To voltage detection circuit 330.

[0067] The initial voltage generator 400 receives the enable signal EN and the inverted standby signal STB at its two input terminals. b The output of the initial voltage generator 400 is connected to node c. The initial voltage generator 400 can operate based on the enable signal EN and the inverted standby signal STB. b To generate the initial voltage (V) INI Based on the enable signal EN and the inverted standby signal STB b The initial voltage generator 400 during charging T CHG The operation ensures that the voltage at node c is equal to the initial voltage V. INI Furthermore, based on the enable signal EN and the inverted standby signal STB... b The initial voltage generator 400 during the detection period T DET Not operating, causing the voltage at node c to change from the initial voltage V. INI It has begun to descend.

[0068] The first terminal of capacitor C is coupled to node a to receive array voltage V. ARRAY The second end of the capacitor is coupled to node c.

[0069] The input terminal in of latch 410 is connected to node c, and the output terminal out of latch 410 is connected to node d. The first power terminal (pw1) of latch 410 is coupled to the supply voltage V via transistor M1. DD The second power supply terminal pw2 of latch 410 is coupled to ground terminal GND via transistor M2, and the output terminal out of latch 410 is coupled to ground terminal GND via transistor Ma.

[0070] In addition, the source terminal of transistor M1 receives the supply voltage V. DD The drain terminal of transistor M1 is connected to the first power supply terminal pw1 of latch 410, and the gate terminal of transistor M1 receives the bias voltage V. BS1 This keeps transistor M1 in the turn-on state. The drain of transistor M2 is connected to the second power supply terminal pw2 of latch 410, the gate of transistor M2 receives the standby signal STB, and the source of transistor M2 is connected to ground GND. The drain of transistor Ma is connected to the output terminal out of latch 410, and the gate of transistor Ma is connected to an inverted standby signal STB. b The source terminal of transistor Ma is connected to ground GND. Of course, in other embodiments, the first power supply terminal pw1 of latch 410 can also directly receive the supply voltage V. DD It does not require receiving the supply voltage V via transistor M1. DD .

[0071] During charging cycle T CHG When transistor M2 is turned off, latch 410 is not in operation, while transistor Ma is turned on, causing the output terminal out of latch 410 to be reset to ground voltage (0V). That is, the voltage at node d is ground voltage.

[0072] During the detection period T DET When transistor M2 is turned on and transistor Ma is turned off, latch 410 operates. At this time, based on the voltage change at input terminal in of latch 410, latch 410 can generate a trigger signal S at output terminal out. TR .

[0073] In addition, the input of combinational logic circuit 420 is connected to node d, and the output of combinational logic circuit 420 generates an enable signal EN.

[0074] According to an embodiment of the present invention, during charging cycle T CHG The initial voltage generator 400 is operational, while the latch 410 is not operational. During the detection period T... DET The initial voltage generator 400 is not operating, while the latch 410 is operating.

[0075] Please refer to Figure 4B The drawing shows Figure 4A A schematic diagram of the relevant signals from the voltage detection circuit. Compared to... Figure 3B , Figure 4B Furthermore, signals on nodes c and d are added. For example... Figure 4B As shown, during the charging period from time point ta to time point tb, T CHGThe enable signal EN is at a logic high level, and the standby signal STB is at a logic low level. Therefore, the voltage at node c is charged to the initial voltage V. INI Additionally, the array voltage V at node a ARRAY It rises to the first value, V1.

[0076] During the detection period from time point tb to time point tc, T DET The enable signal EN is at logic low, the standby signal STB is at logic high, and the voltage at node c is determined by the initial voltage V. INI It begins to decline. Since capacitor C is connected between node a and node c, it will decrease during the detection period T. DET The voltages at nodes a and c will have the same falling rate.

[0077] At time point tc, the array voltage V ARRAY The voltage level drops to less than or equal to the second value V2, and the voltage at node c (i.e., the input terminal in of latch 410) drops to less than or equal to the trigger voltage (V). TR The voltage level of ) . At this time, latch 410 is triggered, causing the output terminal out of latch 410 (i.e., node d) to change state, and triggering a trigger signal (S TR ) Valid. Based on the valid trigger signal S TR The combinational logic circuit 420 enables the enable signal EN. That is, when the array voltage V... ARRAY When the value is less than or equal to the second value V2, the trigger signal S is activated. TR Effective. Additionally, when the array voltage V... ARRAY When the second value V2 is reached, the combinational logic circuit 420 triggers the signal S. TR To enable the enable signal EN, and represent the detection period T DET Finish.

[0078] Please refer to Figure 5 The diagram illustrates the detailed structure of the voltage detection circuit. The initial voltage generator 400 includes: a switch SW, transistors M3, M4, and M5, and a resistor R. Transistor M3 is a P-type transistor, while transistors M4 and M5 are N-type transistors.

[0079] The first terminal of switch SW is connected to node b, and the control terminal of switch SW receives the enable signal EN. The second terminal of the switch is the output terminal of the initial voltage generator 400 and is connected to node c. Based on the enable signal EN, switch SW operates during charging T... CHG It becomes a closed state, with an initial voltage V.INI The signal is transmitted from node b to node c. Based on the enable signal EN, switch SW is activated during the detection period T. DET When node c becomes open, it cannot receive the initial voltage V generated by the output of the initial voltage generator 400. INI .

[0080] The source terminal of transistor M3 receives the supply voltage V. DD The drain of transistor M3 is connected to node b. The first terminal of resistor R is connected to node b, and the second terminal of resistor R is connected to the gate of transistor M3. The drain of transistor M4 is connected to the second terminal of resistor R, and the gate of transistor M4 receives a bias voltage V. BS2 The drain terminal of transistor M5 is connected to the source terminal of transistor M4, and the source terminal of transistor M5 is connected to ground GND. The gate terminal of transistor M5 is the input terminal of the initial voltage generator 400 and receives the inverted standby signal STB. b .

[0081] The latch 410 includes transistors M6 and M7. Transistor M7 is a P-type transistor, and transistor M6 is an N-type transistor. The drain terminal of transistor M6 is the input terminal in of latch 410, and the drain terminal of transistor M7 is the output terminal out of latch 410.

[0082] In latch 410, the drain terminal of transistor M6 is connected to node c, the gate terminal of transistor M6 is connected to node d, and the source terminal of transistor M6 is the second power supply terminal pw2 of latch 410. Furthermore, the source terminal of transistor M7 is the first power supply terminal pw1 of latch 410, the gate terminal of transistor M7 is connected to node c, and the drain terminal of transistor M7 is connected to node d.

[0083] The combinational logic circuit 420 can respond to the trigger signal S TR The standby signal STB is used to generate the enable signal EN. The combinational logic circuit 420 includes a NOT gate 422 and a NAND gate 426. The input of the NOT gate 422 is connected to node d, the output of the NOT gate 422 is connected to the first input of the NAND gate 426, the second input of the NAND gate 426 receives the standby signal STB, and the output of the NAND gate 426 generates the enable signal EN.

[0084] The NOT gate 422 also includes a transistor Mp and a transistor Mn. The gate of transistor Mp is connected to node d, and the drain of transistor Mp is connected to the drain of transistor Mn. The source of transistor Mp receives the supply voltage V. DDThe source terminal of transistor Mn is connected to ground voltage GND. According to an embodiment of the present invention, the threshold voltage of transistor Mn is greater than the threshold voltage of transistor M6.

[0085] Furthermore, the combinational logic circuit 420 of the present invention is designed based on the logic levels of the enable signal EN and the standby signal STB. That is to say, the present invention is not limited to... Figure 5 The combinational logic circuit 420 can be designed by those skilled in the art based on the actual logic levels.

[0086] Please refer to Figure 6A The diagram shown illustrates the operation of the voltage detection circuit during charging. Please refer to... Figure 6B The diagram shown illustrates the initial operation of the voltage detection circuit during the detection period. Please refer to... Figure 6C The diagram shown illustrates the operation of the voltage detection circuit during the later stages of the detection process. Please refer to... Figure 6D The drawing shows Figure 5 A schematic diagram of the relevant signals from the voltage detection circuit. Additionally, in Figure 6A , Figure 6B and Figure 6C In this circuit, NOT gate 422 is no longer represented by the actual circuit of transistors Mp and Mn, but only by a simplified circuit symbol.

[0087] like Figure 6A and Figure 6D As shown, during the charging period from time point ta to time point tb, T CHG The standby signal STB is at a logic low level, and the inverted standby signal STB... b When the logic level is high, the enable signal EN is also high, and switch SW is closed. At this time, transistor M2 is off, and latch 410 is inactive. Furthermore, transistor Ma is on, and the voltage at node d is reset to ground (0V). Combinational logic circuit 420 generates a logic high enable signal EN. Additionally, the initial voltage generator 400 operates. The operating principle of the initial voltage generator 400 is explained in detail below.

[0088] Because the enable signal EN and the inverted standby signal STB b When the logic level is high, transistor M5 is turned on, and the initial voltage generator 400 operates. At this time, transistor M4 receives the bias voltage V. BS2 Generate bias current I BS And bias current I BS From the supply voltage V DD The current flows to the ground terminal GND through transistor M3, resistor R, transistor M4, and transistor M5.

[0089] Furthermore, when transistor M3 is turned on, the voltage V at the gate of transistor M3... G Equal to (V) DD -V THP ), that is, V G = V DD -V THP Additionally, the initial voltage V at node b INI That is (V) G +R×I BS ), where V THP V is the threshold voltage of transistor M3. G This can be considered as the turn-on voltage of transistor M3. In other words, during the charging cycle T... CHG Since switch SW is in the closed state, node c is charged to the initial voltage V at time point tb. INI Additionally, the array voltage V at node a ARRAY Charge to the first value V1.

[0090] like Figure 6B and Figure 6D As shown, time point tb to time point tc is the detection period T. DET During the testing period, T DET Initially (at time tb), the standby signal STB switches to a logic high level, inverting the standby signal STB. b The logic level is switched to low, causing combinational logic circuit 420 to switch the enable signal EN to low. Therefore, the initial voltage generator 400 is not operational, switch SW is open, and the voltage at node c is equal to the initial voltage V. INI Additionally, transistor M2 is turned on, and latch 410 is active. Furthermore, transistor Ma is turned off, and the voltage at node d is ground (0V).

[0091] In other words, the voltage detection circuit 330 during the detection period T DET In the initial stage, at time point tb, the array voltage V of node a ARRAY The voltage at node c is equal to the first value V1, and the voltage at node c is equal to the initial voltage. VINI Among them, the initial voltage V INI =(V G +R×I BS ).

[0092] Figure 6D As shown, time point tb to time point tc is the detection period T. DET Initially, voltage generator 400 is not operating, switch SW is in the open state, latch 410 is activated, and array voltage V at node a... ARRAYAnd the voltage at node c gradually decreases at the same falling rate.

[0093] like Figure 6C and Figure 6D As shown, during the detection period T DET In the later stages (at time tc), the array voltage V of node a ARRAY When the voltage drops to the second value V2, the voltage at node c drops to V. G Among them, V G =V DD -V THP For example, when transistor M3 and transistor M7 have the same size, V G This can be considered as the turn-on voltage of transistor M7. That is, the trigger voltage V of latch 410. TR Equal to the turn-on voltage V of transistor M7 G .

[0094] In other words, at time point tc, the voltage at node c drops to the trigger voltage V. TR (V TR = V G When the transistor M7 in latch 410 is turned on, latch 410 is triggered. Therefore, the voltage at node d (triggered by the signal S) increases. TR The logic level switches from low to high, enabling the combinational logic circuit 420 to activate the enable signal EN, switching the enable signal EN from low to high. Then, within a very short time, the processing unit 312 deactivates the standby signal STB. Therefore, the processing unit 312 re-enters the charging period T. CHG This causes transistor Ma to turn on, resetting the voltage at node d to ground (0V).

[0095] In other embodiments, as the voltage at node c gradually decreases, transistor M7 begins to turn on slightly, increasing the voltage at node c. Additionally, transistor M6, with a lower threshold voltage, also turns on slightly, pulling down the voltage at node d. This operation allows the voltage at node d to rise rapidly and prevents leakage current.

[0096] As explained above, at time point tc, the enable signal EN is valid, the standby signal STB is invalid, and during the detection period T... DET The voltage detection circuit 330 has ended and is now entering the next charging period T. CHG Its subsequent operation is similar and will not be elaborated further.

[0097] Furthermore, by Figure 6D It can be seen that the voltage at node c is determined by the initial voltage V. INI Drop to trigger voltage VTR Among them, V INI =(V G +R×I BS V TR = V G Therefore, the initial voltage V INI With trigger voltage V TR The voltage difference ΔV is R×I BS Similarly, the array voltage V ARRAY The voltage difference ΔV between the first value V1 and the second value V2 is also R×I. BS In other words, the resistor R and the bias current I in the initial voltage generator 400 are controlled. BS The size of the array voltage V determines the array voltage. ARRAY Peak-to-peak value of a medium ripple.

[0098] For example, array voltage V ARRAY The first value V1 is 9V. This controls the resistor R and bias current I in the initial voltage generator 400. BS When the product of the two is 0.3V, the second value V2 can be determined to be 8.7V.

[0099] Furthermore, as explained above, when transistor M3 and transistor M7 have the same dimensions, transistor M3 and transistor M7 will have the same turn-on voltage V. G This causes the trigger voltage V of latch 410 to... TR equals V G In fact, those skilled in the art can also design transistors M3 and M7 with different sizes, and use the size ratio between transistors M3 and M7 to calculate the turn-on voltage of transistor M7, which serves as the trigger voltage V of latch 410. TR .

[0100] Furthermore, in actual operation, when the non-volatile memory 300 is in idle mode, the detection period T... DET Approximately 1000 μs, during the charging period T CHG The duration is approximately 2μs. In other words, by utilizing the voltage detection circuit 330, the non-volatile memory 300 can temporarily control the operation of the power supply unit 314 during idle mode, continuously providing the array voltage V. ARRAY To the memory module.

[0101] Furthermore, since the voltage detection circuit 330 consists of only a few electronic components, its layout area is very small. Additionally, the voltage detection circuit 330 of this invention is only used during charging T... CHG An electric current will be generated during charging. During charging, T... CHGIn addition, the voltage detection circuit 330 does not generate any leakage current, thus reducing the power consumption of the non-volatile memory 300.

[0102] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A non-volatile memory, comprising: The processing unit generates a standby signal; A power supply unit is connected to the first node. The power supply unit receives the standby signal. When the standby signal is invalid, the power supply unit converts the supply voltage into an array voltage of a first value and outputs the array voltage to the first node. When the standby signal is valid, the power supply unit stops generating the array voltage. A voltage detection circuit is connected to the first node and receives the standby signal, wherein when the standby signal is valid, the voltage detection circuit detects the array voltage on the first node; as well as The memory module is connected to the first node and receives the array voltage; When the array voltage decreases from the first value to the second value, the voltage detection circuit enables the enable signal to enable the processing unit, so that the processing unit disables the standby signal. Specifically, when the array voltage rises from the second value to the first value, the processing unit enables the standby signal, and the voltage detection circuit disables the enable signal.

2. The non-volatile memory of claim 1, wherein the memory module includes a driving circuit and a memory array, the driving circuit includes a word line driver connected to multiple word lines of the memory array; when the processing unit accesses the memory module, the word line driver converts the array voltage into a word line voltage and drives a specific word line in the memory array.

3. The non-volatile memory of claim 1, wherein the voltage detection circuit comprises: The NOT gate receives the standby signal and generates an inverted standby signal; An initial voltage generator generates an initial voltage to the second node based on the inverted standby signal and the enable signal; A capacitor, wherein a first end of the capacitor is coupled to the first node, and a second end of the capacitor is coupled to the second node; A latch is connected to the second node and the third node; wherein, during the detection period, the trigger signal is activated when the array voltage is less than or equal to the second value; as well as The combinational logic circuit generates the enable signal based on the standby signal and the trigger signal.

4. The non-volatile memory of claim 3, wherein during charging, the standby signal is invalid, the inverted standby signal is valid, the enable signal is valid, and the trigger signal is reset to ground voltage.

5. The non-volatile memory of claim 4, wherein during the detection period, when the array voltage drops from the first value, the standby signal is valid, the inverted standby signal is invalid, the enable signal is invalid, the initial voltage generator is not operating, and the latch is operating.

6. The non-volatile memory as described in claim 5, wherein, When the array voltage reaches the second value, the combinational logic circuit enables the enable signal according to the trigger signal and ends the detection period.

7. The non-volatile memory of claim 6, wherein during the detection period, the array voltage and the voltage of the second node have the same rate of voltage drop.

8. A voltage detection circuit in a non-volatile memory, the non-volatile memory including a power supply unit connected to a first node, wherein when a standby signal is invalid, the power supply unit outputs an array voltage of a first value to the first node, and when the standby signal is valid, the power supply unit stops outputting the array voltage, the voltage detection circuit comprising: An initial voltage generator receives an inverted standby signal and an enable signal, and the output of the initial voltage generator is connected to a second node. A capacitor, wherein a first end of the capacitor is coupled to the first node, and a second end of the capacitor is coupled to the second node; A latch, the input of which is connected to the second node, the output of which is connected to the third node, the first power supply of which is coupled to the supply voltage, and the second power supply of which is coupled to the ground. as well as A combinational logic circuit, the input of which is connected to the third node, and the output of which generates the enable signal.

9. The voltage detection circuit of claim 8, wherein during charging, the standby signal is invalid, the inverted standby signal is valid, the enable signal is valid, the initial voltage generator generates an initial voltage to the second node, and the output of the latch is reset to ground voltage.

10. The voltage detection circuit of claim 9, wherein during the detection period, the standby signal is valid, the inverted standby signal is invalid, the enable signal is invalid, the initial voltage generator is not operating, the latch is operating, the voltage of the second node begins to decrease from the initial voltage, and the array voltage of the first node begins to decrease from the first value.

11. The voltage detection circuit as described in claim 10, wherein, When the voltage of the second node drops to the trigger voltage, the latch is triggered and the trigger signal is enabled, causing the combinational logic circuit to enable the enable signal and end the detection period.

12. The voltage detection circuit of claim 11, wherein at the end of the detection period, the array voltage of the first node drops to less than or equal to a second value.

13. The voltage detection circuit of claim 8 further includes a first transistor and a second transistor, wherein the source terminal of the first transistor receives the supply voltage, the gate terminal of the first transistor receives a first bias voltage, the drain terminal of the first transistor is connected to the first power supply terminal of the latch, the drain terminal of the second transistor is connected to the second power supply terminal of the latch, the gate terminal of the second transistor receives the standby signal, and the source terminal of the second transistor is connected to the ground terminal.

14. The voltage detection circuit of claim 8, wherein the initial voltage generator comprises: The third transistor, whose source terminal receives the supply voltage, and whose drain terminal is connected to the fourth node; A resistor, the first end of which is connected to the fourth node, and the second end of which is connected to the gate of the third transistor; A fourth transistor, the drain of which is connected to the second terminal of the resistor, and the gate of which receives a second bias voltage. The fifth transistor has its drain terminal connected to the source terminal of the fourth transistor, its gate terminal receiving the inverted standby signal, and its source terminal coupled to ground voltage. as well as A switch, the first end of which is connected to the fourth node, the second end of which is connected to the second node, and the control terminal of which receives the enable signal; During charging, the standby signal is invalid, the inverted standby signal is valid, the enable signal is valid, the switch is closed, and the initial voltage generator generates the initial voltage to the second node. During the detection period, the standby signal is valid, the inverted standby signal is invalid, the enable signal is invalid, and the switch is in the off state.

15. The voltage detection circuit of claim 8, wherein the latch comprises: The sixth transistor has its drain terminal connected to the second node, its gate terminal connected to the third node, and its source terminal being the second power supply terminal of the latch. as well as The seventh transistor has its source terminal connected to the first power supply terminal of the latch, its gate terminal connected to the second node, and its drain terminal connected to the third node. During charging, the second node is charged to the initial voltage, and the array voltage of the first node is the first value. During the detection period, when the voltage of the second node drops to the trigger voltage, the latch is triggered and the trigger signal is valid.

16. The voltage detection circuit of claim 15, wherein the combinational logic circuit comprises: A NOT gate, the input of which is connected to the third node; as well as A NAND gate, wherein the first input of the NAND gate is connected to the output of the NAND gate, the second input of the NAND gate receives the standby signal, and the output of the NAND gate generates the enable signal; When the latch generates the trigger signal, the combinational logic circuit enables the enable signal.

17. The voltage detection circuit of claim 16, wherein the NOT gate comprises: The eighth transistor receives the supply voltage at its source terminal, its gate terminal is connected to the third node, and its drain terminal is connected to the first input terminal of the NAND gate. as well as The ninth transistor has its drain terminal connected to the first input terminal of the NAND gate, its gate terminal connected to the third node, and its source terminal receiving a ground voltage. The threshold voltage of the ninth transistor is greater than that of the sixth transistor.

18. The voltage detection circuit of claim 8 further includes a tenth transistor, the drain of which is connected to the third node, the gate of which receives the inverted standby signal, and the source of which is coupled to ground voltage, wherein when the inverted standby signal is valid, the tenth transistor resets the output of the latch to the ground voltage.

19. The voltage detection circuit of claim 8, wherein the non-volatile memory further includes a processing unit that receives the enable signal, wherein when the enable signal is valid, the processing unit disables the standby signal, and when the array voltage of the first node is charged to the first value, the processing unit enables the standby signal.

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