Memory bad block scanning method and circuitry therefor

Abstract

A memory bad block scanning method and its circuit system, in the program of scanning memory bad block, the circuit system uses a cache read instruction, the cache read instruction is suitable for the program of continuously reading memory storage page, can load the memory storage page data into a cache in advance, read out the data in the next instruction cycle, then load the next storage page data into the cache, and so on, until the program of scanning memory bad block is completed, in the process, the time of preparing the next data of the memory can be effectively reduced, and the influence of the memory reading busy time on time efficiency is reduced.

Description

Technical Field

[0001] The specification proposes a method for scanning bad blocks in memory, and in particular a memory bad block scanning method and its circuit system that effectively shortens the bad block scanning time by changing the memory read instructions. Background Technology

[0002] Flash memory in the category of non-volatile memory includes two types: NAND flash memory and NOR flash memory.

[0003] In an electronic device, the controller IC that uses the anti-gate flash memory needs to perform a bad block scan on the anti-gate flash memory during the first power-on. Only after establishing a bad block table can the subsequent power-on process continue. This process takes a considerable amount of time because it requires reading all the data from the entire flash memory. The prior art proposes improvements in two directions, as described below.

[0004] One way to improve this is to quickly identify good and bad blocks after data is read from the flash memory. When a bit error occurs, the error-correcting code (ECC) circuit will take a long time to calculate the result. Therefore, if there is a pipeline mechanism inside the hardware, the data in the flash memory will not be congested and wasted time in the error correction process.

[0005] Another improvement method is to speed up the reading of data from the flash memory. The read speed depends on how quickly the flash memory controller can send out flash commands. Speeding up data reading from flash memory generally involves reducing processor processing time, for example, by allowing hardware to handle the process automatically, or by reducing the impact of the flash memory's read busy time. It's worth noting that after sending a read page command, there is a waiting period before data can be read from the flash memory; this period is called the read busy time.

[0006] Based on the current methods for handling bad blocks in flash memory in electronic devices, there are no other effective ways to further shorten the scanning time for the function of scanning bad blocks, except for hardware acceleration. Summary of the Invention

[0007] Given that conventional technologies do not offer effective solutions to shorten the scanning time during flash memory bad block scanning, apart from hardware acceleration, this invention proposes a memory bad block scanning method and circuit, which employs different flash read commands to effectively reduce the impact of read busy time. Furthermore, the use of a hardware design without a processor (such as a CPU) can significantly improve the bad block scanning time.

[0008] According to an embodiment, the memory bad block scanning method operates within a memory control circuit. In the main steps of the method, the control circuit issues a cache read instruction to the memory, causing the memory to enter a memory busy period. Simultaneously, a page of data is pre-loaded into the memory cache. Then, while executing the aforementioned cache read instruction to read the page data from the cache, the control circuit issues another cache read instruction to the memory, allowing the next page of data to be pre-loaded into the cache during another memory busy period. This process is repeated until the memory bad block scanning procedure is complete.

[0009] Furthermore, before executing this memory bad block scanning method, the control circuit sets the starting address of the memory pages, the size of each memory page, and the size of the memory blocks. In the method steps, before the control circuit issues a cache read instruction to the memory, the control circuit first issues a memory page read instruction to the memory to read the data of the first memory page.

[0010] Preferably, the control circuit obtains the memory page data through an error correction code circuit, that is, it determines whether there are bad blocks based on the error correction codes written in each memory page. When a bad block is found in the memory, the control circuit will build a bad block lookup table based on the address of the bad block.

[0011] According to another embodiment of the memory bad block scanning method, the proposed circuit system includes a control circuit, which includes an error correction code circuit and a register area. The control circuit is connected to a memory to run the memory bad block scanning method.

[0012] In the method operated by the control circuit, a memory page read instruction is issued according to the address and size of the first memory page. The system then enters the memory busy time corresponding to the memory page read instruction, allowing the memory to prepare data. Next, the Nth (N is an integer greater than or equal to 1) cache read instruction is sent, entering the Nth memory busy time, and the Nth memory page data is pre-loaded into the memory cache. Then, the memory page read instruction is executed, reading the first memory page data according to its starting address. Next, the (N+1)th cache read instruction is sent, entering the (N+1)th memory busy time, and the (N+1)th memory page data is pre-loaded into the memory cache. Then, the Nth cache read instruction is executed to read the Nth memory page data from the cache. After completion, N = N+1. This process is repeated until the bad block scan of the memory is complete.

[0013] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0014] Figure 1 The diagram shows an embodiment of the circuit system architecture proposed in the specification. Figure 2 The flowchart shows the circuit system executing the bad block scanning program; Figure 3 A flowchart illustrating an embodiment of the memory bad block scanning method is shown; Figure 4 This diagram illustrates the timing of the memory bad block scanning method operating in memory; and Figure 5 This shows a flowchart illustrating an example of establishing a bad block lookup table. Detailed Implementation

[0015] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention.

[0016] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0017] After an electronic device (such as a computer system or various devices using flash memory) is powered on, the system will execute a bad block scan program on the memory (such as a NAND flash memory) to find bad blocks formed during the manufacturing process or as the number of read / write and erase operations increases. Based on this, a bad block table is built, which serves as the basis for the electronic device to exclude bad blocks when accessing the memory. However, scanning bad blocks takes time. In addition to hardware acceleration, this invention proposes a memory bad block scanning method and circuit using a modified flash read command. The method can effectively reduce the impact of read busy time when scanning the memory and improve the bad block scanning time. In particular, there is no hardware intervention of the processor (such as the CPU) in the process.

[0018] Figure 1 The diagram shows an embodiment of the circuit system architecture proposed in this disclosure. The circuit system can be applied in an electronic device. The main components of the circuit system include a memory 12 and its control circuit 10. The memory 12 can be a NAND flash memory.

[0019] The memory 12 can be formed by multiple flash memory cells. Taking anti-ghost flash memory as an example, a flash memory cell consists of multiple storage blocks (e.g., 4096 blocks), and a storage block consists of multiple storage pages (e.g., 1 block = 128 pages). A storage page is the basic unit for storing data, meaning that each read / write operation of the flash memory is performed on a page-by-page basis. A storage page is further subdivided into several sectors. Furthermore, the memory 12 has a cache 121 space for storing data that is ready to be read by the cache read command issued by the control circuit 10.

[0020] The control circuit 10 includes several circuit units implemented in hardware. The register interface 107 is connected to the register in the control circuit 10, which is the register that records the bad block lookup table 101. The register is also used to record the memory 12 access information such as the address of each memory page, the number of memory pages and the number of blocks of the memory 12 connected to the control circuit 10.

[0021] The control circuit 10 is connected to the memory 12 through the memory interface 105, that is, it transmits memory control commands to the memory 12 through the memory interface 105. After the error correction code circuit 103 obtains the data from the memory 12, it can send the bad block information obtained by scanning back to the bad block lookup table 101 and update the bad block lookup table 101. Accordingly, the bad block lookup table 101 records the block and memory page size of the bad block and records the result of the processing by the error correction code circuit 103.

[0022] The circuit system can simultaneously refer to the bad block scanning program during execution. Figure 2 The flowchart shown is as follows. When the electronic device is powered on (step S201), the central processing unit 15 in the electronic device controls the register circuit in the connection control circuit 10 via the register interface 107 to start the control circuit 10 of the memory (step S203). First, it reads the bad block lookup table 101 in the register of the control circuit 10 and prepares to read the data in the memory 12.

[0023] In particular, a bad block scan procedure needs to be executed after the first boot (step S205). This is done by the firmware program in the control circuit 10 sequentially writing and reading each storage block in the connected memory 12. The error correction code circuit 103 determines whether each block is a good block or a bad block based on the sequentially read data (step S207). The error correction code circuit 103 determines the presence of bad blocks based on the error-correcting code (ECC) written to each storage page in the memory 12. Furthermore, it should be noted that during normal operation of the circuit system, because the anti-gate flash memory may develop bit errors after a period of use, the error correction code circuit 103 in the control circuit 10 will perform a certain degree of bit error repair, giving the control circuit 10 a certain fault tolerance capability.

[0024] For example, control circuit 10 uses a 6-bit error correction code circuit 103. A sector in memory 12 is 512 bytes in size; therefore, each sector requires 10 bytes of error correction code (ECC) data for protection. When 512 + 10 bytes of data are read from memory 12, if there are no more than 6 error bits, it is considered a good sector. The 512 bytes represent the data read from memory 12, and the additional 10 bytes represent the data generated during the error correction process.

[0025] In the bad block scanning procedure, when a bad block is detected, the control circuit 10 marks the address of the bad block through a register area and establishes a bad block lookup table 101 as shown in the figure (step S209). The bad block lookup table 101 is used to record the memory address range of the bad block and mark which memory blocks are unusable, so that when the central processing unit 15 accesses the memory 12 in the future, the control circuit 10 will prevent data from being written to the bad block according to the bad block lookup table 101.

[0026] In particular, the bad block scanning program described above reads data from each memory page when scanning the memory, thus generating read busy time. In order to reduce the impact of this read busy time, the bad block scanning method proposed in the specification modifies the flash read command. The main concept is to use a cache read command in the program that reads data in memory 12 page by page. This allows the system to automatically pre-read the data of the next memory page while reading the data of the current memory page, thereby reducing the impact of read busy time.

[0027] In one embodiment, reference may be made to Figure 3The flowchart illustrates an embodiment of a memory bad block scanning method implemented in the control circuit of a memory. In the main technical means of the process, besides using a page read command to read the first memory page data, the control circuit 10 continues the scanning of bad blocks in the memory 12 via a cache read command. Specifically, it sends a cache read command (in the following embodiment, the Nth cache read command) to the memory 12, causing the memory to enter a memory busy period (in the following embodiment, the Nth memory busy period). This allows a memory page data (in the following embodiment, the Nth memory page data) to be pre-loaded into the cache of the memory 12. Then, when executing a cache read command to read the memory page data from the cache, the control circuit sends the next cache read command (in the following embodiment, the N+1th cache read command) to the memory. During another memory busy period (in the following embodiment, the N+1th memory busy period), the next memory page data (in the following embodiment, the N+1th memory page data) is pre-loaded into the cache of the memory 12. Repeat the above steps until the program for scanning bad blocks in memory 12 is complete.

[0028] Figure 3 A flowchart illustrating an embodiment of a memory bad block scanning method is provided, along with reference to... Figure 4 The diagram illustrates the timing of the operation of the display method in memory. It is worth noting that after the memory bad block scanning method is executed, the circuit system establishes a bad block lookup table in the control circuit. Alternatively, before executing the process, the control circuit loads an existing bad block lookup table, which can then be updated based on the new bad block addresses obtained during the scan.

[0029] exist Figure 3 In the process, as in step S301, after the electronic device is powered on, the central processing unit in the device starts the memory control circuit. The control circuit executes the memory bad block scanning program. First, the size of the memory block and memory page in the memory is set by firmware means, including the starting address of the memory page, so that the process can be executed automatically according to this information until the memory bad block scanning work is completed.

[0030] For example, in step S303, the central processing unit of the electronic device using this circuit system triggers this automatic execution cache read program. In this memory bad block scan program, as in step S305, it is first determined whether the first memory page is being read. If so, this indicates the start of the memory bad block scan program. As in step S307, the control circuit will issue a memory page read instruction to the memory through the memory interface based on the address and size of the first memory page. Figure 4The timing diagram shows a memory page read instruction 401, which includes a starting address of the first memory page. Then, as in step S309, the memory is driven into a busy period, as... Figure 4 The displayed memory busy time is 402, which is the time it takes for the memory to prepare to read data.

[0031] It is worth mentioning that the process will continue to step S311 to execute a storage page read instruction to read the data of the first storage page, such as... Figure 4 The displayed data 405 indicates the route (41) for reading the data of the first storage page. However, before reading the data of the first storage page, according to the embodiment of the invention, the control circuit sends a cache read instruction to the connected memory through the memory interface to preload the data of the next storage page into the memory cache, which can reduce the time that the memory prepares the next piece of data when it receives the next read instruction.

[0032] Returning to step S305 of the process, if it is not currently reading the first memory page (No), step S313 is executed, and the control circuit sends the Nth cache read instruction (if it is after the aforementioned memory page read instruction, then N=1). Figure 4 The displayed cache read instructions are 403, 406, and 409, etc. For example, in step S315, the memory will enter the Nth memory busy period, such as... Figure 4 The displayed memory busy times 404, 407, and 410 indicate the time during which the memory prepares to read data. During this time, the corresponding Nth page data is pre-loaded into the cache so that the control circuit can read the Nth page data from the cache in step S317. Figure 4 The displayed data 408 and 411 represent the routes (42) for reading data from the Nth memory page and (43) for reading data from the (N+1)th memory page. The value N is an integer greater than or equal to 1.

[0033] Next, the firmware program executed in the control circuit sets N to N+1 (step S319), and enters the next instruction cycle. The process returns to step S313, and the control circuit continues to send the N+1th cache read instruction, so that the memory enters the N+1th memory busy time. At the same time, the N+1th memory page data is cached, and the N+1th memory page data is preloaded into the cache (step S315) to facilitate reading the N+1th memory page data in step S317. In step S319, the control circuit continues the process of reading subsequent memory pages. The process will repeatedly execute steps S313 to S319 until all memory blocks are scanned.

[0034] As can be seen from the above process, according to the embodiment of the memory bad block scanning method, in order to reduce the impact of busy time when reading memory data, in addition to initially reading the first memory page data with a memory page read instruction, subsequent memory pages are read through newly added cache read instructions. This is achieved by pre-loading the next memory page data into the memory cache to reduce the time the memory spends preparing for the next data entry after receiving a read instruction. Specifically, as described in the above steps, when the Nth cache read instruction is sent, the memory enters the Nth memory busy time, simultaneously caching the Nth memory page data. Before executing the Nth cache read instruction to read the Nth memory page data, the next cache read instruction (N+1th cache read instruction) is sent first, causing the memory to enter the N+1th memory busy time and cache the N+1th memory page data. Only then is the previous Nth cache read instruction executed to read the Nth memory page data. This entire process is applicable to continuous memory page reads. By repeatedly executing steps S313 to S319, the process of scanning memory bad blocks can be accelerated. Notably, the process only requires setting the starting address of the memory page and the size of each memory block and page to read the entire memory data. No central processing unit of the electronic device needs to be involved in the operation, thus achieving the purpose of hardware acceleration.

[0035] As described in the above embodiments, by introducing a cache read instruction to preload the next storage page into the memory cache, the time the memory spends preparing the next storage page data is reduced, which in turn reduces the impact of the memory's busy time in preparing data on the overall time performance.

[0036] exist Figure 5 The flowchart illustrating an embodiment for establishing a bad block lookup table shows that when the control circuit scans for bad blocks in the memory, as in step S501, the error correction code circuit reads memory page data, such as the data of the Nth memory page, through a memory page read instruction or a cache read instruction, where N is an integer of 1 or higher. Then, as in step S503, the error correction code circuit determines whether there are bad blocks based on the error correction codes (ECCs) written to each memory page. As in step S505, it determines whether there are error bits. If the error correction code circuit determines that the Nth memory page has no error bits (No), as in step S507, the control circuit will not record the relevant data; conversely, if the read data does not match the stored error correction code (Yes), as in step S509, the error correction code circuit can perform bit correction, determine that there are unrepairable memory pages, mark them as bad blocks, and set the block bit associated with the Nth memory page to establish a bad block lookup table. Then, the control circuit sets N=N+1 (step S511), that is, it performs the bad block judgment of the next storage page until the bad block scan of all storage pages is completed.

[0037] In summary, based on the embodiments of the memory bad block scanning method and its circuit system described above, the inventive concept is to add a cache read instruction in addition to the memory page read instruction in the program for scanning bad blocks in memory. In the program for scanning bad blocks in memory, the data of the next memory page can be preloaded into the memory cache. The cache read instruction is applicable to applications that read consecutive memory pages, which can effectively reduce the time for memory to prepare the next piece of data and reduce the impact of memory busy time. This will improve the time for scanning bad blocks. In particular, there is no hardware intervention of the processor in the process.

[0038] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0039] [Symbol Explanation]

[0040] 10: Control Circuit

[0041] 101: Bad Block Lookup Table

[0042] 103: Error Correction Code Circuit

[0043] 105: Memory Interface

[0044] 107: Register Interface

[0045] 12: Memory

[0046] 121: Cache

[0047] 15: Central Processing Unit

[0048] 401: Memory page read instruction

[0049] 402: Memory busy time

[0050] 403: Cache fetch instruction

[0051] 404: Memory Busy Time

[0052] 405: Data

[0053] 406: Cache fetch instruction

[0054] 407: Memory Busy Time

[0055] 408: Data

[0056] 409: Cache Fetch Instruction

[0057] 410: Memory busy time

[0058] 411: Data

[0059] 41: Read data from the first memory page

[0060] 42: Read data from the Nth memory page

[0061] 43: Read data from the (N+1)th memory page

[0062] Steps S201-S209: Flowchart of the circuit system executing the bad block scanning program

[0063] Steps S301 to S319: Memory Bad Block Scanning Process

[0064] Steps S501 to S511 establish the bad block lookup table process.

Claims

1. A method for scanning bad blocks in a memory, operating in a control circuit of a memory, wherein, The memory includes multiple flash memory cells, each flash memory cell consisting of multiple memory blocks, each memory block consisting of multiple memory pages, and the memory includes a cache space for storing data to be read by a cache read instruction issued by the control circuit. The method includes: The control circuit is activated to prepare to read the data from the memory. The control circuit is configured to sequentially write and read each memory block in the memory, and the error correction circuit determines whether each memory block is a good block or a bad block by performing the following steps based on the sequentially read data: a. The control circuit sends the cache read instruction to the memory, causing the memory to enter a memory busy time, and at the same time preloads a memory page data into a cache of the memory. b. When executing the cache read instruction to read the memory page data in the cache, the control circuit issues the next cache read instruction to the memory, preloading the next memory page data into the cache during another memory busy period; and c. Repeat steps a and b until the program for scanning bad blocks in the memory is complete.

2. The memory bad block scanning method according to claim 1, wherein, Before the control circuit sends the cache read instruction to the memory, the control circuit first sends a memory page read instruction to the memory to read the data of a first memory page.

3. The memory bad block scanning method according to claim 2, wherein the control circuit sends the memory page read instruction and the cache read instruction to the memory through a memory interface in the control circuit.

4. The memory bad block scan method of claim 2, wherein, Before executing the memory bad block scanning method, the control circuit sets the starting address of a memory page, the size of each memory page, and the size of the memory block.

5. The memory bad block scanning method according to any one of claims 1 to 4, wherein, When a bad block is detected in the memory during scanning, the control circuit creates a bad block lookup table based on the address of the bad block.

6. The memory bad block scanning method according to claim 5, wherein after obtaining the memory page data, the error correction code circuit in the control circuit determines whether there are bad blocks based on the error correction codes written in each memory page.

7. A method for scanning bad blocks in a memory, operating in a control circuit of a memory, wherein, The memory includes multiple flash memory cells, each flash memory cell consisting of multiple memory blocks, each memory block consisting of multiple memory pages, and the memory includes a cache space for storing data to be read by a cache read instruction issued by the control circuit. The method includes: The control circuit is activated to prepare to read the data from the memory. The control circuit is configured to sequentially write and read each memory block in the memory, and the error correction circuit determines whether each memory block is a good block or a bad block by performing the following steps based on the sequentially read data: a. Issue a memory page read instruction based on the address and size of the first memory page, enter the busy time of a memory corresponding to the memory page read instruction, and allow the memory to prepare data, wherein the memory page read instruction records a starting address of the first memory page; b. Send the Nth cache read instruction, enter the Nth memory busy time, and preload the Nth memory page data into a cache of that memory, where N is an integer equal to or greater than 1; c. Execute the memory page read instruction to read the data of the first memory page according to the starting address of the first memory page; d. Send the N+1th cache read instruction, enter the N+1th memory busy time, and preload the N+1th memory page data into the cache of that memory; e. Execute the Nth cache read instruction to read the Nth memory page data in the cache; and f. Set N=N+1, and repeat steps d to f until the bad block scan procedure for the memory is completed.

8. The memory bad block scanning method according to claim 7, wherein the control circuit sends the memory page read instruction and the cache read instruction to the memory through one of the memory interfaces.

9. The memory bad block scanning method according to claim 8, wherein after obtaining the memory page data, the error correction code circuit in the control circuit determines whether there are bad blocks based on the error correction codes written in each memory page.

10. A circuit system comprising: A control circuit, including an error correction code circuit and a register area, is connected to a memory to run a memory bad block scanning method. The memory includes multiple flash memory cells, each flash memory cell consisting of multiple memory blocks, and each memory block consisting of multiple memory pages. The memory also includes a cache space for storing data to be read by a cache read instruction issued by the control circuit. The method includes: The control circuit is activated to prepare to read the data from the memory. The control circuit is configured to sequentially write and read each memory block in the memory, and the error correction circuit determines whether each memory block is a good block or a bad block by performing the following steps based on the sequentially read data: a. The control circuit sends the cache read instruction to the memory, causing the memory to enter a memory busy time, and at the same time preloads a memory page data into a cache of the memory. b. When executing the cache read instruction to read the memory page data in the cache, the control circuit issues the next cache read instruction to the memory, preloading the next memory page data into the cache during another memory busy period; and c. Repeat steps a and b until the program for scanning bad blocks in the memory is complete.

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