Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region; forming dummy gates on the substrate, a distance between each dummy gate on the first region being less than a distance between each dummy gate on the second region; forming an initial dielectric layer on the substrate, a thickness of the initial dielectric layer on the first region being greater than a thickness of the initial dielectric layer on the second region; performing a plurality of cycle thinning processes on the initial dielectric layer to form a dielectric layer, the dielectric layer on the first region being flush with the dielectric layer on the second region, the cycle thinning process including: forming a sacrificial layer on the initial dielectric layer, a thickness of the sacrificial layer on the first region being less than a thickness of the sacrificial layer on the second region; removing the sacrificial layer and a portion of the initial dielectric layer. The method for forming a semiconductor structure improves uniformity of the dielectric layer and the etch stop layer, and improves performance of a semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology

[0002] In a field-effect transistor (FET), the gate controls the current flow by creating or eliminating a channel between the source and drain, allowing or hindering the flow of electrons. The uniformity of the gate height has a significant impact on the overall performance of the device. Non-uniform gate height typically leads to increased capacitance and decreased reliability, thereby reducing device performance.

[0003] In existing semiconductor technologies, the gate formation process typically includes: forming a dummy gate on the substrate, an etch stop layer on the sidewall surface of the dummy gate, and a dielectric layer on the substrate; removing the dummy gate and filling it with metal to form the gate. The formation of the dielectric layer typically employs a spin-coating process, which is low-cost and fast.

[0004] During the gate formation process, the uniformity of the dielectric layer has a significant impact on the uniformity of the etch stop layer height, and the uniformity of the height of the dielectric layer and the etch stop layer directly affects the uniformity of the gate height.

[0005] However, in the prior art, the dielectric layer formed by spin coating process has poor uniformity, which in turn leads to poor uniformity of the etch stop layer and uneven gate height, thus reducing the performance of semiconductor devices. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the uniformity of the dielectric layer, thereby improving the uniformity of the etch stop layer and the gate height, and improving the performance of the semiconductor device.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming dummy gates on the substrate, wherein the spacing between each dummy gate on the first region is smaller than the spacing between each dummy gate on the second region; forming an initial dielectric layer on the substrate, wherein the thickness of the initial dielectric layer on the first region is greater than the thickness of the initial dielectric layer on the second region; performing a series of cyclic thinning processes on the initial dielectric layer to form a dielectric layer, wherein the dielectric layer on the first region is flush with the dielectric layer on the second region, the cyclic thinning process comprising: forming a sacrificial layer on the initial dielectric layer, wherein the thickness of the sacrificial layer on the first region is smaller than the thickness of the sacrificial layer on the second region; and removing the sacrificial layer and a portion of the initial dielectric layer.

[0008] Optionally, the substrate includes: a base and a fin structure located on the base.

[0009] Optionally, after forming the dummy gate and before forming the initial dielectric layer, the method for forming the semiconductor structure further includes forming an epitaxial layer in the substrate on both sides of the dummy gate.

[0010] Optionally, the method for forming the dummy gate includes: forming a dummy gate material layer on the substrate; forming a mask layer on the dummy gate material layer, the mask layer exposing a portion of the surface of the dummy gate material layer; and etching the dummy gate material layer using the mask layer as a mask to form the dummy gate.

[0011] Optionally, the difference between the thickness of the initial dielectric layer in the first region and the thickness of the initial dielectric layer in the second region is in the range of 600 angstroms to 700 angstroms.

[0012] Optionally, the difference between the thickness of the sacrificial layer in the second region and the thickness of the sacrificial layer in the first region is in the range of 100 angstroms to 150 angstroms.

[0013] Optionally, the material of the initial dielectric layer includes a carbon-containing material.

[0014] Optionally, the initial dielectric layer is formed by a spin coating process.

[0015] Optionally, the material of the sacrificial layer may include carbon-containing organic matter.

[0016] Optionally, the method for forming the sacrificial layer includes chemical vapor deposition.

[0017] Optionally, the method for removing the sacrificial layer and part of the initial dielectric layer includes an electron beam etching process.

[0018] Optionally, the electron beam etching process includes: a multi-point rapid temperature-controlled electron beam etching process.

[0019] Optionally, before performing several cycles of thinning on the initial dielectric layer, the method for forming the semiconductor structure further includes performing an initial thinning process on the initial dielectric layer.

[0020] Optionally, the initial thinning process includes: a multi-point rapid temperature-controlled electron beam etching process.

[0021] Optionally, after forming the dummy gate and before forming the initial dielectric layer, the method for forming the semiconductor structure further includes forming an initial etch stop layer on the substrate surface and the dummy gate sidewall surface.

[0022] Optionally, the initial etch stop layer includes: an initial gate sidewall located on the surface of the dummy gate sidewall, and an initial contact etch stop layer located on the surface of the initial gate sidewall.

[0023] Optionally, the material of the initial contact etch stop layer includes silicon nitride.

[0024] Optionally, the material of the initial gate sidewall includes nitrides.

[0025] Optionally, the top surface of the dielectric layer is higher than the top surface of the pseudo-gate.

[0026] Optionally, after forming the dielectric layer, the method for forming the semiconductor structure further includes: removing a portion of the initial etch stop layer to form an etch stop layer, wherein the etch stop layer is flush with the dielectric layer.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] In the semiconductor structure formation method provided by the present invention, during the process of performing several cycles of thinning treatment on the initial dielectric layer, the sacrificial layer formed on the first region is thinner, while the sacrificial layer formed on the second region is thicker. The thickness difference between the sacrificial layers on the first and second regions is opposite to the thickness difference between the initial dielectric layers on the first and second regions. Therefore, when removing the sacrificial layer and part of the initial dielectric layer, the thickness of the removed initial dielectric layer on the first and second regions can be adjusted using the sacrificial layer, making the thinning thickness of the initial dielectric layer on the first region greater than that on the second region, thereby reducing the thickness difference between the initial dielectric layers on the first and second regions. After performing several cycles of thinning treatment on the initial dielectric layer, the thickness of the dielectric layer formed on the first region is equal to that on the second region, thereby improving the uniformity of the dielectric layer thickness in each region of the semiconductor structure. This is beneficial for improving the process window of the subsequent semiconductor device formation process and improving the performance of the semiconductor device.

[0029] Furthermore, in the method for forming the semiconductor structure, the method for initial thinning of the initial dielectric layer includes a multi-point rapid temperature-controlled assisted electron beam etching process. This multi-point rapid temperature-controlled assisted electron beam etching process can precisely control the temperature of each region on the initial dielectric layer, thereby precisely controlling the etching rate of each region of the initial dielectric layer, improving the global uniformity of the processed initial dielectric layer, and consequently, enabling the initial etch stop layer to have better global uniformity after the initial thinning process, thus improving the process window for semiconductor device formation. Attached Figure Description

[0030] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0031] Figures 4 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0032] As described in the background section, in the prior art, the dielectric layer formed by spin coating process has poor uniformity, which in turn leads to poor uniformity of the etch stop layer and uneven gate height, thus reducing the performance of semiconductor devices.

[0033] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0034] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a dummy gate 102 is formed on the substrate 100, the spacing between each dummy gate 102 on the first region I is smaller than the spacing between each dummy gate 102 on the second region II; a mask layer 103 is formed on the dummy gate 102; an initial etch stop layer 104 is formed on the sidewall surface of the dummy gate 102, the sidewall surface of the mask layer 103 and the substrate 100.

[0035] Please refer to Figure 2 An initial dielectric layer 105 is formed on the substrate 100. The material of the initial dielectric layer 105 is a carbon-containing material. The initial dielectric layer 105 is formed by spin coating. The height of the initial dielectric layer 105 on the first region I is greater than the height of the initial dielectric layer 105 on the second region II.

[0036] Please refer to Figure 3 A portion of the initial dielectric layer 105 is removed to form a dielectric layer 106, wherein the height of the dielectric layer 106 on the first region I is greater than the height of the dielectric layer 106 on the second region II; a portion of the initial etch stop layer 104 is removed until it is flush with the dielectric layer 106 to form an etch stop layer 107.

[0037] During the formation of the initial dielectric layer 105, a spin coating process was used to spin-coat the reactants onto the substrate 100. Due to the different adhesion and flowability of the reactants at the center and edge of the substrate 100 during the spin coating process, the initial dielectric layer 105 formed at the edge region of the substrate 100 is thicker, while the initial dielectric layer 105 formed at the center region of the substrate 100 is thinner. This results in a global thickness difference in the initial dielectric layer 105, which in turn causes a global thickness difference in the subsequently formed dielectric layer 106.

[0038] Furthermore, during the process of forming the initial dielectric layer 105 on the substrate 100 by spin coating, since the spacing between each dummy gate 102 on the first region I is smaller than the spacing between each dummy gate 102 on the second region II, the thickness of the reactant coated on the first region I is higher than the thickness coated on the second region II. This results in inconsistent thicknesses of the initial dielectric layer 105 in different patterned regions on the substrate 100, which in turn leads to local thickness differences in the subsequently formed dielectric layer 106.

[0039] The global and local height differences of the dielectric layer 106 cause the subsequent etch stop layer 107 to also have global and local height differences, thereby reducing the height uniformity of the etch stop layer 107 after planarization, which in turn leads to poor height uniformity of the subsequently formed gate structure, thus reducing the performance of the device.

[0040] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. By forming a sacrificial layer on an initial dielectric layer, wherein the thickness difference of the sacrificial layer in the first region and the second region is opposite to the thickness difference of the initial dielectric layer in the first region and the second region, the thinning thickness of the initial dielectric layer in the first region and the second region is adjusted by the sacrificial layer, thereby reducing the thickness difference of the initial dielectric layer in the first region and the second region. This improves the uniformity of the dielectric layer in each region of the semiconductor structure, thereby improving the performance of the semiconductor device.

[0041] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0043] Please refer to Figure 4 Substrate 200 is provided.

[0044] The substrate 200 provides a platform for the subsequent formation of semiconductor structures.

[0045] In this embodiment, the substrate 200 is circular. From the perspective of the global position of the substrate 200, since the different regions on the surface of the substrate 200 are located at different positions, the substrate 200 includes a central region 201 and an edge region 202.

[0046] Furthermore, from the perspective of a local location of the substrate 200, the substrate 200 includes a first region and a second region, which are used to form different types of device structures.

[0047] In this embodiment, based on the composition of the substrate 200, the substrate 200 includes: a substrate (not shown) and a fin structure (not shown) located on the substrate.

[0048] Specifically, the substrate material includes silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. In this embodiment, the substrate material is silicon.

[0049] Please Figure 4 Based on reference Figure 5 , Figure 4 for Figure 5 Top view along the X direction, Figure 5 for Figure 4 A schematic cross-sectional view of region A along the SS' direction.

[0050] like Figure 5 As shown, a pseudo gate 211 is formed on the substrate 200.

[0051] Region A is located within the central region 201 of substrate 200. The substrate 200 of region A includes only the first region I, and the spacing between each dummy gate 211 formed on the substrate 200 of region A is the same.

[0052] Specifically, the method for forming the dummy gate 211 includes: forming a dummy gate material layer (not shown) on the substrate 200; forming a mask layer 212 on the dummy gate material layer, the mask layer 212 exposing a portion of the surface of the dummy gate material layer; and etching the dummy gate material layer using the mask layer 212 as a mask to form the dummy gate 211.

[0053] In this embodiment, the mask layer 212 includes a first mask layer 215 and a second mask layer 214 located on the first mask layer 215. The material of the first mask layer 215 includes silicon nitride; the material of the second mask layer 214 includes silicon oxide.

[0054] The mask layer 212 serves as a protective layer for the dummy gate 211, ensuring that it remains unaffected during the subsequent formation of the initial dielectric layer and the cyclic thinning process, thereby ensuring the uniformity and integrity of the subsequently formed gate structure.

[0055] After forming the dummy gate 211, an epitaxial layer 210 is formed in the substrate 200 on both sides of the dummy gate 211. The epitaxial layer 210 is used to adjust the electrical properties to enhance the mobility of charge carriers.

[0056] After the epitaxial layer 210 is formed, an initial etch stop layer 213 is formed on the surface of the substrate 200 and the sidewall surface of the dummy gate 211.

[0057] The initial etch stop layer 213 helps control the position and height of the subsequently formed gate structure.

[0058] In this embodiment, the initial etch stop layer 213 is higher than the top surface of the dummy gate 211, and the top of the initial etch stop layer 213 is flush with the top of the mask layer 212, thereby ensuring that the gate structure formed subsequently has sufficient height.

[0059] Specifically, the initial etch stop layer 213 includes: an initial gate sidewall 217 located on the sidewall surface of the dummy gate 211, and an initial contact etch stop layer 216 located on the surface of the initial gate sidewall 217. The initial contact etch stop layer 216 is made of silicon nitride; the initial gate sidewall 217 is made of nitride.

[0060] Please Figure 4 Based on reference Figure 6 , Figure 4 for Figure 6 Top view along the X direction, Figure 6 for Figure 4 A schematic cross-sectional view of region B along the SS' direction.

[0061] Region B is located within the edge region 202 of substrate 200. The substrate 200 of region B includes only the first region I, and the spacing between each dummy gate 221 formed on the substrate 200 of region B is the same.

[0062] Figure 6 The dummy gate 221, mask layer 222, epitaxial layer 220, and initial etch stop layer 223 shown are respectively with Figure 5 The dummy gate 211, mask layer 212, epitaxial layer 210, and initial etch stop layer 213 shown are formed simultaneously, and Figure 6 The materials and structures of the dummy gate 221, mask layer 222, epitaxial layer 220, and initial etch stop layer 223 shown are respectively related to... Figure 5 The dummy gate 211, mask layer 212, epitaxial layer 210 and initial etch stop layer 213 shown are made of the same material and have the same structure.

[0063] Specifically, Figure 6 The mask layer 222 shown includes a first mask layer 225 and a second mask layer 224, which are respectively connected to... Figure 5 The first mask layer 215 and the second mask layer 214 shown are formed simultaneously and have the same structure and material.

[0064] Figure 6 The initial etch stop layer 223 shown includes the initial gate sidewall 227 and the initial contact etch stop layer 226, which are respectively connected to... Figure 5The initial gate sidewall 217 and the initial contact etch stop layer 216 shown are formed simultaneously and have the same structure and material.

[0065] Please Figure 4 Based on reference Figure 7 , Figure 4 for Figure 7 Top view along the X direction, Figure 7 for Figure 4 A schematic cross-sectional view of the central region C along the SS' direction.

[0066] The substrate 200 of region C includes a first region I and a second region II. The spacing between each dummy gate 231 on the first region I is smaller than the spacing between each dummy gate 231 on the second region, so as to facilitate the subsequent formation of different gate structures on the first region I and the second region II respectively.

[0067] Figure 7 The dummy gate 231, mask layer 232, epitaxial layer 230, and initial etch stop layer 233 shown are respectively with Figure 5 The pseudo gate 211, mask layer 212, epitaxial layer 210 and initial etch stop layer 213 shown are formed simultaneously.

[0068] Specifically, Figure 7 The mask layer 232 shown includes a first mask layer 235 and a second mask layer 234, which are respectively connected to... Figure 5 The first mask layer 215 and the second mask layer 214 shown are formed simultaneously.

[0069] Figure 7 The initial etch stop layer 233 shown includes an initial gate sidewall 237 and an initial contact etch stop layer 236, which are respectively connected to... Figure 5 The initial gate sidewall 217 shown is formed simultaneously with the initial contact etch stop layer 216.

[0070] It is important to note that Figures 5 to 7 Only for Figure 4 The cross-sectional structures of regions A, B, and C along the SS' direction are illustrated. In this embodiment, the dummy gate, mask layer, epitaxial layer, and initial etch stop layer are simultaneously formed on... Figure 4 The entire area of ​​the substrate 200 in the middle.

[0071] Please Figures 5 to 7 Based on reference Figures 8 to 10 , Figures 8 to 10 respectively with Figures 5 to 7 Correspondingly, an initial dielectric layer 218 is formed on the substrate 200.

[0072] The initial dielectric layer 218 is used to control the thinning height of the subsequent initial etch stop layer 213, thereby helping to control the height of the subsequently formed gate structure.

[0073] In this embodiment, the material of the initial dielectric layer 218 includes a carbon-containing material. The formation process of the initial dielectric layer 218 includes a spin coating process.

[0074] Please continue to refer to this. Figure 8 and Figure 9 The thickness H2 of the initial dielectric layer 218 on the edge region 202 is greater than the thickness H1 of the initial dielectric layer 218 on the center region 201.

[0075] Because a spin-coating process was used to spin-coat the reactants onto the substrate 200 during the formation of the initial dielectric layer 218, and the reactants exhibit different adhesion and flow properties in the central region 201 and the edge region 202 of the substrate 200 during spin-coating, the reactants are more likely to accumulate in the edge region 202, resulting in a thicker initial dielectric layer 218 H2 formed in the edge region 202 (e.g., ...). Figure 9 As shown), the initial dielectric layer 218 formed on the central region 201 has a relatively thin thickness H1 (as shown). Figure 8 As shown in the figure, this results in a global thickness difference in the initial dielectric layer 218 on the substrate 200.

[0076] Please continue to refer to this. Figure 10 The thickness H3 of the initial dielectric layer 218 on the first region I is greater than the thickness H4 of the initial dielectric layer 218 on the second region II.

[0077] During the process of forming the initial dielectric layer 218 on the substrate 200 by spin coating, since the spacing between each dummy gate 231 on the first region I is smaller than the spacing between each dummy gate 231 on the second region II, the reactants tend to accumulate more in the smaller gaps on the first region I. As a result, the thickness H3 of the reactants coated on the first region I is higher than the thickness H4 of the reactants coated on the second region II, resulting in local thickness differences in the initial dielectric layer 218 of different patterned regions on the substrate 200.

[0078] Specifically, the difference between the thickness H3 of the initial dielectric layer 218 on the first region I and the thickness H4 of the initial dielectric layer 218 on the second region II is in the range of 600 angstroms to 700 angstroms.

[0079] Please Figures 8 to 10 Based on reference Figures 11 to 13 , Figures 11 to 13 respectively with Figures 8 to 10 Correspondingly, the initial dielectric layer 218 is subjected to an initial thinning process.

[0080] The purpose of the initial thinning process is to adjust the thickness of the initial dielectric layer 218 at different locations on the substrate 200, so as to reduce the global thickness difference of the initial dielectric layer 218.

[0081] Specifically, the initial thinning process includes an electron beam etching process assisted by multi-point fast temperature control (Fast Hydra).

[0082] Please refer to Figure 11 and Figure 12 After the initial thinning process, the thickness L1 of the initial dielectric layer 218 on the central region 201 of the substrate 200 is equal to the thickness L2 of the initial dielectric layer 218 on the edge region 202.

[0083] The multi-point rapid temperature-controlled assisted electron beam etching process can precisely control the temperature of the initial dielectric layer 218 in different regions of the substrate 200, thereby precisely controlling the etching rate of the initial dielectric layer 218 in each region. Therefore, by adjusting the temperature of the central region 201 and the edge region 202 differently, the etching rates of the initial dielectric layer 218 on the central region 201 and the edge region 202 are made different. This allows for precise adjustment and reduction of the thickness difference of the initial dielectric layer 218 on the central region 201 and the edge region 202, ensuring that after the initial thinning process, the thickness L1 of the initial dielectric layer 218 on the central region 201 is equal to the thickness L2 of the initial dielectric layer 218 on the edge region 202. This initial thinning process significantly reduces the global thickness difference of the initial dielectric layer 218, resulting in superior global thickness uniformity of the processed initial dielectric layer 218. This, in turn, improves the high uniformity of the subsequently formed gate structure, optimizing the process window and device performance of the semiconductor device formation process.

[0084] Furthermore, compared with existing electron beam etching processes, the multi-point rapid temperature-controlled assisted electron beam etching process has a smaller impact on the semiconductor device fabrication efficiency and does not require additional process equipment. Therefore, it can improve device performance while ensuring production efficiency and process cost.

[0085] Please refer to Figure 13 After the initial thinning process, the thickness L3 of the initial dielectric layer 218 on the first region I is greater than the thickness L4 of the initial dielectric layer 218 on the second region II.

[0086] Before the initial thinning process, the thickness H3 of the initial dielectric layer 218 on the first region I is greater than the thickness H4 of the initial dielectric layer 218 on the second region II. Since the multi-point rapid temperature-controlled assisted electron beam etching process used in the initial thinning process has the same degree of thinning for the initial dielectric layer 218 in the same region (such as region C), after the initial thinning process, the thickness L3 of the initial dielectric layer 218 on the first region I is still greater than the thickness L4 of the initial dielectric layer 218 on the second region II. Therefore, the local thickness difference of the initial dielectric layer 218 caused by the different device structures in the same region still exists.

[0087] After the initial thinning process is performed on the initial dielectric layer 218, the initial dielectric layer 218 is subjected to several cycles of thinning process to form a dielectric layer, wherein the dielectric layer on the first region I is flush with the dielectric layer on the second region II.

[0088] The cyclic thinning process includes: forming a sacrificial layer on the initial dielectric layer 218, wherein the thickness of the sacrificial layer on the first region is less than the thickness of the sacrificial layer on the second region; and removing the sacrificial layer and a portion of the initial dielectric layer 218.

[0089] A cross-sectional structural diagram of the cyclic thinning process is shown below. Figures 14 to 16 As shown.

[0090] Please Figure 13 Based on reference Figure 14 A sacrificial layer 239 is formed on the initial dielectric layer 218, wherein the thickness of the sacrificial layer 239 on the first region I is less than the thickness of the sacrificial layer 239 on the second region II.

[0091] By forming sacrificial layers 239 of different thicknesses on the first region I and the second region II, the thickness of the initial dielectric layer 218 on the first region I and the second region II can be adjusted separately with the aid of the sacrificial layers 239, so as to reduce the local thickness difference of the initial dielectric layer 218 on the first region I and the second region II.

[0092] In this embodiment, the material of the sacrificial layer 239 includes a carbon-containing organic compound. The method for forming the sacrificial layer 239 includes chemical vapor deposition.

[0093] Because the spacing between each dummy gate 231 on the first region I is smaller than the spacing between each dummy gate 231 on the second region II, the reactive gas used in the chemical vapor deposition reaction to form the sacrificial layer 239 is less likely to enter the narrow spacing on the first region I, resulting in a thinner sacrificial layer 239 deposited on the initial dielectric layer 218 of the first region I; while the spacing between the dummy gates 211 on the second region II is larger, so the reactive gas can more easily enter the spacing on the second region II, thereby making the sacrificial layer 239 deposited on the initial dielectric layer 218 of the second region II thicker, thus making the thickness of the sacrificial layer 239 on the first region I less than the thickness of the sacrificial layer 239 on the second region II.

[0094] In this embodiment, the difference between the thickness of the sacrificial layer 239 on the second region II and the thickness of the sacrificial layer 239 on the first region I is in the range of 100 angstroms to 150 angstroms.

[0095] Please refer to Figure 15 Remove the sacrificial layer 239 and part of the initial dielectric layer 218.

[0096] Since the thickness of the sacrificial layer 239 on the first region I is less than the thickness of the sacrificial layer 239 on the second region II, and the thickness difference of the sacrificial layer 239 on the first region I and the second region II is opposite to the thickness difference of the initial dielectric layer 218 on the first region I and the second region II, when removing the sacrificial layer 239 and part of the initial dielectric layer 218, the thickness of the removed initial dielectric layer 218 on the first region I and the second region II can be adjusted using the sacrificial layer 239, so that the thinning thickness of the initial dielectric layer 218 on the first region I is greater than the thinning thickness of the initial dielectric layer 218 on the second region II. Therefore, after removing the sacrificial layer 239 and part of the initial dielectric layer 218, the difference between the thickness W3 of the initial dielectric layer 218 on the first region I and the thickness W4 of the initial dielectric layer 218 on the second region II is less than the difference between the thickness L3 of the initial dielectric layer 218 on the first region I and the thickness L4 of the initial dielectric layer 218 on the second region before the cyclic thinning process.

[0097] Please refer to Figure 16 The initial dielectric layer 218 is subjected to several cycles as described above. Figure 13 and Figure 14 The cyclic thinning process shown is used to form a dielectric layer 250, wherein the dielectric layer 250 on the first region I is flush with the dielectric layer 250 on the second region II.

[0098] Through several cycles of thinning, the thickness difference of the initial dielectric layer 218 on the first region II and the second region II is continuously reduced, thereby giving the formed dielectric layer 250 better local thickness uniformity, which in turn helps to improve the high uniformity of the gate structure formed subsequently, and optimizes the process window and device performance of the semiconductor device formation process.

[0099] In this embodiment, the method for removing the sacrificial layer 239 and a portion of the initial dielectric layer 218 includes an electron beam etching process. Preferably, the electron beam etching process includes a multi-point rapid temperature-controlled assisted electron beam etching process.

[0100] The electron beam etching process with multi-point rapid temperature control is used in the process of removing the sacrificial layer 239 and part of the initial dielectric layer 218. Therefore, it is possible to reduce the local thickness difference of the initial dielectric layer 218 while continuing to reduce the global thickness difference of the initial dielectric layer 218, so that the formed dielectric layer 250 has both better local thickness uniformity and global thickness uniformity.

[0101] In this embodiment, the number of cyclic thinning processes ranges from 2 to 10. More cyclic thinning processes result in better uniformity of the formed dielectric layer 250, but also higher process costs and lower device fabrication efficiency. Preferably, the cyclic thinning process is performed 4 times, thereby improving the uniformity of the dielectric layer 250 while controlling process costs and ensuring efficient device fabrication.

[0102] In this embodiment, the top surface of the dielectric layer 250 is higher than the top surface of the dummy gate 231, thereby ensuring that the gate structure formed subsequently has sufficient height.

[0103] Please continue to refer to this. Figure 16 After the dielectric layer 250 is formed, a portion of the initial etch stop layer 233 is removed to form an etch stop layer 251, which is flush with the dielectric layer 250.

[0104] It should be noted that, in this embodiment, the initial dielectric layer on all areas of the substrate 200 is simultaneously subjected to... Figures 14 to 16 The aforementioned cyclic thinning process is used to form a dielectric layer. After the dielectric layer is formed, an etch stop layer is simultaneously formed over the entire area of ​​the substrate 200, the etch stop layer being flush with the dielectric layer.

[0105] Because the dielectric layer has superior local and global thickness uniformity, the height of the etch stop layer also has superior local and global uniformity. This is beneficial for improving the height uniformity of the subsequently formed gate structure, and optimizes the process window and device performance of the semiconductor device formation process.

[0106] In this embodiment, after the etching stop layer is formed, the etching stop layer and the dielectric layer are planarized.

[0107] Since both the etching stop layer and the dielectric layer have excellent local and global uniformity, the planarization effect is good, further improving the process window for subsequent device fabrication.

[0108] After planarizing the etch stop layer and dielectric layer, the dummy gate and mask layer are removed to form a gate opening; a gate structure (not shown) is filled in the gate opening, and the gate structure is flush with the etch stop layer and dielectric layer.

[0109] Because the etch stop layer and dielectric layer have good uniformity, the height of the formed gate structure is more uniform, thereby improving the performance of the semiconductor device.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A dummy gate is formed on the substrate, wherein the spacing between each dummy gate in the first region is smaller than the spacing between each dummy gate in the second region; An initial dielectric layer is formed on the substrate, wherein the thickness of the initial dielectric layer on the first region is greater than the thickness of the initial dielectric layer on the second region; the initial dielectric layer covers the top and sidewalls of each pseudogate. The initial dielectric layer is subjected to several cycles of thinning to form a dielectric layer, wherein the dielectric layer on the first region is flush with the dielectric layer on the second region. The cyclic thinning process includes: forming a sacrificial layer on the initial dielectric layer, wherein the thickness of the sacrificial layer on the first region is less than the thickness of the sacrificial layer on the second region; and removing the sacrificial layer and a portion of the initial dielectric layer. The initial dielectric layer is formed by a spin coating process.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes: a base and a fin structure located on the base.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, After forming the dummy gate and before forming the initial dielectric layer, the method further includes forming an epitaxial layer in the substrate on both sides of the dummy gate.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the dummy gate includes: forming a dummy gate material layer on the substrate; forming a mask layer on the dummy gate material layer, the mask layer exposing a portion of the surface of the dummy gate material layer; and etching the dummy gate material layer using the mask layer as a mask to form the dummy gate.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The difference between the thickness of the initial dielectric layer in the first region and the thickness of the initial dielectric layer in the second region is in the range of 600 angstroms to 700 angstroms.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The difference between the thickness of the sacrificial layer in the second region and the thickness of the sacrificial layer in the first region is 100 angstroms to 150 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial dielectric layer includes carbon-containing materials.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer includes carbon-containing organic matter.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the sacrificial layer includes chemical vapor deposition.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Methods for removing the sacrificial layer and part of the initial dielectric layer include electron beam etching.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The electron beam etching process includes: a multi-point rapid temperature-controlled electron beam etching process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before performing several cycles of thinning on the initial dielectric layer, the process further includes performing an initial thinning process on the initial dielectric layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The initial thinning process includes: electron beam etching process assisted by multi-point rapid temperature control.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the dummy gate and before forming the initial dielectric layer, the method further includes forming an initial etch stop layer on the substrate surface and the dummy gate sidewall surface.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The initial etch stop layer includes: an initial gate sidewall located on the surface of the dummy gate sidewall, and an initial contact etch stop layer located on the surface of the initial gate sidewall.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the initial contact etch stop layer includes silicon nitride.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the initial gate sidewall includes nitrides.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the dielectric layer is higher than the top surface of the pseudo-gate.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming the dielectric layer, the method further includes: removing a portion of the initial etch stop layer to form an etch stop layer, the etch stop layer being flush with the dielectric layer.

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