Integrated circuit structure, memory and integrated circuit layout

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides an integrated circuit structure, a memory and an integrated circuit layout, the integrated circuit structure comprises: a data pad; an electrostatic discharge circuit located on one side of the data pad and electrically connected with the data pad; a first transmission circuit located on one side of the electrostatic discharge circuit facing the data pad, the first transmission circuit being electrically connected with the electrostatic discharge circuit through a first bus; and a second transmission circuit located on one side of the electrostatic discharge circuit away from the first transmission circuit, the second transmission circuit being electrically connected with the electrostatic discharge circuit through a second bus; wherein one of the first transmission circuit and the second transmission circuit is used for transmitting data from the data pad to a storage array, and the other is used for receiving data from the storage array and transmitting the data to the data pad. The embodiment of the present disclosure is at least beneficial to shorten the lengths of the first bus and the second bus, so as to reduce the parasitic capacitance and layout area of the integrated circuit structure as a whole.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an integrated circuit structure, a memory, and an integrated circuit layout. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] However, due to the limited area of ​​memory, excessive and densely packed circuits can easily lead to coupling and mutual interference. Furthermore, the overall footprint is large, increasing costs. Therefore, it is necessary to optimize the layout and routing of the various circuit structures within the memory. Summary of the Invention

[0004] This disclosure provides an integrated circuit structure, a memory, and an integrated circuit layout. By separating the circuit structure for writing data from the circuit structure for reading data, the overall parasitic capacitance and layout area of ​​the integrated circuit structure are reduced.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides an integrated circuit structure, including: a data pad; an electrostatic discharge circuit located on one side of the data pad and electrically connected to the data pad; a first transmission circuit located on the side of the electrostatic discharge circuit facing the data pad, the first transmission circuit being electrically connected to the electrostatic discharge circuit via a first bus; and a second transmission circuit located on the side of the electrostatic discharge circuit away from the first transmission circuit, the second transmission circuit being electrically connected to the electrostatic discharge circuit via a second bus; wherein, one of the first transmission circuit and the second transmission circuit is used to transmit data from the data pad to a storage array, and the other is used to receive data from the storage array and transmit it to the data pad.

[0006] In some embodiments, the first transmission circuit is used to transmit data from the data pads to the storage array, and the second transmission circuit is used to receive data from the storage array and transmit it to the data pads.

[0007] In some embodiments, the first transmission circuit comprises: an input buffer circuit for receiving data transmitted from the data pads corresponding to the input buffer circuit; and a latch circuit for receiving and latching data output from the input buffer unit, and outputting the latched data in response to a write clock signal.

[0008] In some embodiments, the input buffer circuit is located between the latch circuit and the electrostatic discharge circuit.

[0009] In some embodiments, the second transmission circuit includes: a first-in-first-out (FIFO) circuit for receiving and transmitting data from the storage array; and a driving circuit for receiving data output from the FIFO circuit and outputting the data to the data pads, wherein the driving circuit is located between the electrostatic discharge circuit and the FIFO circuit.

[0010] In some embodiments, the second transmission circuit further includes a parallel-to-serial conversion circuit, which is located between the driving circuit and the first-in-first-out circuit, and is used to perform parallel-to-serial conversion on the data output from the first-in-first-out circuit, and transmit the converted data to the driving circuit.

[0011] In some embodiments, the second transmission circuit further includes a pre-drive circuit, which is located between the drive circuit and the first-in-first-out circuit.

[0012] In some embodiments, the integrated circuit structure further includes: a first clock processing circuit, which provides a first clock signal, and a first transmission circuit outputs data from the data pads in response to the first clock signal; and a second clock processing circuit, which provides a second clock signal, and a second transmission circuit outputs data from the memory array in response to the second clock signal; wherein the positional arrangement of the first clock processing circuit and the second clock processing circuit corresponds to the positional arrangement of the first transmission circuit and the second transmission circuit.

[0013] In some embodiments, the integrated circuit structure further includes: a first data selection module, which is connected to multiple first transmission circuits via multiple third buses, each third bus corresponding to at least one first transmission circuit; and a second data selection module, which is connected to multiple second transmission circuits via multiple fourth buses, each fourth bus corresponding to at least one second transmission circuit; wherein the first data selection module and the second data selection module are connected to the memory array and located on the same side of the first transmission circuit and the second transmission circuit, and the positional arrangement of the first data selection module and the second data selection module corresponds to the positional arrangement of the first transmission circuit and the second transmission circuit.

[0014] In some embodiments, the integrated circuit structure includes: a plurality of data pads in the same row, a plurality of electrostatic discharge circuits in the same row, a plurality of first transmission circuits in the same row, and a plurality of second transmission circuits in the same row, wherein the data pads, the electrostatic discharge circuits, the first transmission circuits and the second transmission circuits correspond to each other.

[0015] In some embodiments, the integrated circuit structure further includes: a data mask pad, located in the same row as the data pad, for transmitting data mask signals; a third transmission circuit, located in the same row as the first transmission circuit, for transmitting the data mask signals from the data mask pad; and a fourth transmission circuit, located in the same row as the fourth transmission circuit, for receiving the data mask signals from the memory array and transmitting them to the data mask pad.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, including: a storage cell; and the integrated circuit structure described in any of the preceding claims.

[0017] According to some embodiments of this disclosure, another aspect of this disclosure provides an integrated circuit layout, including: a data pad area for defining the positions of multiple data pads in the same row; an electrostatic discharge area located on one side of the data pad area for defining the positions of multiple electrostatic discharge circuits in the same row; a first transmission area located between the data pad area and the electrostatic discharge area for defining the positions of multiple first transmission circuits in the same row, wherein the first transmission circuits and the electrostatic discharge circuits are electrically connected via a first bus; and a second transmission area located on the side of the electrostatic discharge area away from the first transmission area for defining the positions of multiple second transmission circuits in the same row, wherein the second transmission circuits and the data pads are electrically connected via a second bus; wherein one of the first transmission circuits and the second transmission circuits is used to transmit data from the data pads to a memory array, and the other is used to receive data from the memory array and transmit it to the data pads.

[0018] In some embodiments, the first transmission circuit is used to transmit data from the data pads to the storage array, and the second transmission circuit is used to receive data from the storage array and transmit it to the data pads.

[0019] In some embodiments, the first transmission area includes: an input buffer for defining a plurality of input buffer circuits in the same row; and a latch area located on the side of the input buffer away from the electrostatic discharge area for defining a plurality of latch circuits in the same row.

[0020] In some embodiments, the second transmission area includes: a first-in-first-out (FIFO) area for defining a plurality of FIFO circuits in the same row; and a drive circuit area located between the FIFO area and the electrostatic discharge area for defining a plurality of drive circuits in the same row.

[0021] In some embodiments, the integrated circuit layout further includes: a first clock region for defining a first clock processing circuit; and a second clock region for defining a second clock processing circuit, wherein the positional arrangement of the first clock region and the second clock region corresponds to the positional arrangement of the first transmission region and the second transmission region.

[0022] In some embodiments, the integrated circuit layout further includes: a first module area for defining a first data selection module; a plurality of third bus areas for defining a plurality of third buses, the third buses connecting the first data selection module and the corresponding first transmission circuit; a second module area for defining a second data selection module, the first module area and the second module area being located on the same side of the first transmission area and the second transmission area, and the positional arrangement of the first module area and the second module area corresponding to the positional arrangement of the first transmission area and the second transmission area; and a plurality of fourth bus areas for defining a plurality of fourth buses, the fourth buses connecting the second data selection module and the corresponding second transmission circuit.

[0023] In some embodiments, in the direction from the first transmission area to the second transmission area, the two initial third bus areas are the longest and the shortest, respectively; the lengths of adjacent third bus areas at odd-numbered positions among the plurality of third bus areas change according to a first trend, and the lengths of adjacent third bus areas at even-numbered positions among the plurality of third bus areas change according to a second trend, wherein the first trend is either increasing or decreasing, and the second trend is either increasing or decreasing.

[0024] In some embodiments, in the direction from the first transmission area to the second transmission area, the two initial fourth bus areas are the longest and the shortest, respectively; the lengths of adjacent fourth bus areas at odd-numbered positions among the plurality of fourth bus areas change according to a first trend, and the lengths of adjacent fourth bus areas at even-numbered positions among the plurality of fourth bus areas change according to a second trend, wherein the first trend is either increasing or decreasing, and the second trend is either increasing or decreasing.

[0025] The technical solution provided in this disclosure has the following advantages:

[0026] The first and second transmission circuits are used to write data to and read data from the memory array, respectively. The first and second transmission circuits are located on opposite sides of the electrostatic discharge circuit, resulting in short distances between them and the discharge circuit. This shortens the length of the first and second buses, thereby reducing the overall parasitic capacitance of the integrated circuit structure and lowering its power consumption. Furthermore, since the data pads and the discharge circuit require a certain distance for data transmission, placing the first transmission circuit within this gap improves the integration density of the integrated circuit structure and reduces its overall layout area. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0028] Figure 1 This is a partial structural diagram of an integrated circuit structure corresponding to a certain data pad;

[0029] Figure 2 This is a partial structural diagram of an integrated circuit structure;

[0030] Figures 3 to 8 Six partial structural diagrams of an integrated circuit structure corresponding to a certain data pad are provided in an embodiment of this disclosure;

[0031] Figure 9 This is a partial structural diagram of an integrated circuit structure provided in an embodiment of the present disclosure;

[0032] Figure 10 for Figure 9 A schematic diagram of the local transmission path layout of the integrated circuit provided in the document;

[0033] Figure 11 for Figure 2 A schematic diagram of the local transmission path layout of the integrated circuit provided in the document;

[0034] Figure 12 for Figure 10 A schematic diagram of the structure between the third or fourth bus and the seventh or eighth bus;

[0035] Figure 13 for Figure 3 The diagram shows the layout structure of the integrated circuit provided in the document.

[0036] Figure 14 for Figure 9 The diagram shows the layout structure of the integrated circuit provided in the document.

[0037] Figure 15 for Figure 10 The diagram shows the layout structure of the integrated circuit provided in the document. Detailed Implementation

[0038] As can be seen from the background technology, the layout and wiring of various circuit structures in memory need to be optimized.

[0039] Figure 1 This is a partial structural diagram of an integrated circuit structure corresponding to a certain data pad. Figure 2 This is a partial structural diagram of an integrated circuit structure.

[0040] refer to Figure 1 The integrated circuit structure includes: a data pad 10, and an electrostatic discharge circuit 11, a driving circuit 12, a pre-driving circuit 13, a parallel-to-serial conversion circuit 14, an input buffer circuit 15, a first-in-first-out (FIFO) circuit 16, and a latch circuit 17 arranged sequentially along a direction X away from the data pad 10. When writing data to the memory array, the data transmission path is: data pad 10 - electrostatic discharge circuit 11 - input buffer circuit 15 - FIFO circuit 16; when reading data from the memory array, the data transmission path is: FIFO circuit 16 - parallel-to-serial conversion circuit 14 - pre-driving circuit 13 - driving circuit 12 - electrostatic discharge circuit 11 - data pad 10.

[0041] It is easy to see that during the process of writing data into the memory array, the data transmission path needs to bypass the drive circuit 12, pre-drive circuit 13, and parallel-to-serial conversion circuit 14 between the electrostatic discharge circuit 11 and the input buffer circuit 15, and also needs to bypass the first-in-first-out circuit 16 between the input buffer circuit 15 and the latch circuit 17. Both of these factors increase the length of the data transmission path. Similarly, during the process of reading data from the memory array, the data transmission path needs to bypass the input buffer circuit 15 between the first-in-first-out circuit 16 and the parallel-to-serial conversion circuit 14, which also increases the length of the data transmission path. Therefore, whether in the data writing or reading stage, there is an additional winding length in the data transmission path, which is not conducive to reducing the parasitic capacitance of the integrated circuit structure, nor is it conducive to simplifying the overall layout of the integrated circuit structure.

[0042] In addition, refer to Figure 2 The integrated circuit structure includes: multiple data pads 10 arranged in the same row, multiple electrostatic discharge circuits 11 arranged in the same row, a driving circuit 12, multiple pre-driving circuits 13 arranged in the same row, multiple parallel-to-serial conversion circuits 14 arranged in the same row, multiple input buffer circuits 15 arranged in the same row, multiple first-in-first-out circuits 16 arranged in the same row, and multiple latch circuits 17 arranged in the same row, with the data pads 10, electrostatic discharge circuits 11, driving circuits 12, pre-driving circuits 13, parallel-to-serial conversion circuits 14, input buffer circuits 15, first-in-first-out circuits 16, and latch circuits 17 facing each other; and a redistribution layer 18 located between the data pads 10 and the electrostatic discharge circuits 11, used to electrically connect the data pads 10 and the electrostatic discharge circuits 11, with the redistribution layer 18 corresponding to each data pad 10.

[0043] Since the redistribution layer 18 has certain requirements on the width of the gap between the data pad 10 and the electrostatic discharge circuit 11, it is not difficult to find that the space utilization rate of the gap area between the data pad 10 and the electrostatic discharge circuit 11, that is, the area where the redistribution layer 18 is located, is low, which is not conducive to improving the overall integration density of the integrated circuit structure.

[0044] In addition, the integrated circuit structure also includes a data sampling pad 19, a first power supply pad 1, a second power supply pad 2, and a ground pad 3. The data sampling pad 19 receives a data sampling signal, such as an RDQS signal; the voltage level of the first power supply received by the first power supply pad 1 can be higher than the voltage level of the second power supply received by the second power supply pad 2.

[0045] It should be noted that, Figure 2 Data pads 10 are labeled DQ0, DQ1, DQ2, and DQ3. Figure 1 and Figure 2 The circuit is labeled DqESD for electrostatic discharge circuit 11, DqFDrv for drive circuit 12, DqPDrv for pre-drive circuit 13, DqP2S for parallel-to-serial conversion circuit 14, DqIB for input buffer circuit 15, DqFiFo for first-in-first-out circuit 16, and DqLat for latch circuit 17. Additionally, Figure 1 The absence of a numeric suffix after the DQ designation indicates that it does not specifically refer to data pad 10. Furthermore, Figure 2 The sampling pad 19 is labeled RDQS, the first power pad 1 is labeled VDDQ, the second power pad 2 is labeled VCC, and the ground pad 3 is labeled VSS.

[0046] This disclosure provides an integrated circuit structure, a memory, and an integrated circuit layout. In the integrated circuit structure, a first transmission circuit and a second transmission circuit are located on opposite sides of an electrostatic discharge circuit, resulting in a short distance between the first and second transmission circuits and the electrostatic discharge circuit. This shortens the length of the first and second buses, thereby reducing the overall parasitic capacitance of the integrated circuit structure and lowering its power consumption. Furthermore, since a certain distance is required between the data pads and the electrostatic discharge circuit for data transmission, placing the first transmission circuit within this distance improves the integration density of the integrated circuit structure and reduces its overall layout area.

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0048] This disclosure provides an embodiment of an integrated circuit structure, which will be described in detail below with reference to the accompanying drawings. Figures 3 to 8 Six partial structural diagrams of an integrated circuit structure corresponding to a certain data pad are provided in an embodiment of this disclosure; Figure 9 This is a partial structural diagram of an integrated circuit structure provided in an embodiment of the present disclosure; Figure 10 for Figure 9 A schematic diagram of the local transmission path layout of the integrated circuit provided in the document; Figure 11 for Figure 2 A schematic diagram of the local transmission path layout of the integrated circuit provided in the document; Figure 12 for Figure 10 A schematic diagram of the structure between the third or fourth bus 178 and the seventh or eighth bus.

[0049] It should be noted that, Figures 3 to 12 In the diagram, the electrostatic discharge circuit 101 is labeled DqESD, the drive circuit 125 is labeled DqFDrv, the pre-drive circuit 145 is labeled DqPDrv, the parallel-to-serial conversion circuit 135 is labeled DqP2S, the input buffer circuit 113 is labeled DqIB, the first-in-first-out circuit 115 is labeled DqFiFo, and the latch circuit 123 is labeled DqLat.

[0050] refer to Figure 3 The integrated circuit structure includes: a data pad 100; an electrostatic discharge circuit 101 located on one side of the data pad 100 and electrically connected to it; a first transmission circuit 103 located on the side of the electrostatic discharge circuit 101 facing the data pad 100, and electrically connected to the electrostatic discharge circuit 101 via a first bus 104; and a second transmission circuit 105 located on the side of the electrostatic discharge circuit 101 away from the first transmission circuit 103, and electrically connected to the electrostatic discharge circuit 101 via a second bus 106. One of the first transmission circuit 103 and the second transmission circuit 105 is used to transmit data from the data pad 100 to a memory array (not shown in the figure), and the other is used to receive data from the memory array and transmit it to the data pad 100. Data pads 100 can be electrically connected to each other via a redistribution layer 102.

[0051] Thus, by separating the circuit structure for storing data in the memory array from the circuit structure for reading data from the memory array, the first transmission circuit 103 and the second transmission circuit 105 are located on opposite sides of the electrostatic discharge circuit 101. On the one hand, reducing the distance between the first transmission circuit 103 and the second transmission circuit 105 and the electrostatic discharge circuit 101 helps to shorten the length of the first bus 104 and the second bus 106, thereby reducing the overall parasitic capacitance of the integrated circuit structure and reducing the power consumption of the integrated circuit structure. On the other hand, whether in the data writing or reading stage, the first bus 104 does not need to bypass the second transmission circuit 105, and the second bus 106 does not need to bypass the first transmission circuit 103, which helps to avoid unnecessary winding lengths in the first bus 104 and the second bus 106, thereby further reducing the overall parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0052] In some embodiments, continue to refer to Figure 3 The first transmission circuit 103 can be located between the electrostatic discharge circuit 101 and the data pad 100. Since the redistribution layer 102 has certain requirements on the spacing width between the data pad 100 and the electrostatic discharge circuit 101 when it electrically connects the data pad 100 and the electrostatic discharge circuit 101, placing the first transmission circuit 103 between the data pad 100 and the electrostatic discharge circuit 101 is beneficial to improving the space utilization of the area where the redistribution layer 102 is located, thereby increasing the overall integration density of the integrated circuit structure and reducing the overall layout area of ​​the integrated circuit structure.

[0053] In some embodiments, continue to refer to Figure 3 The first transmission circuit 103 is used to transmit data from the data pad 100 to the storage array, corresponding to the data write stage. The second transmission circuit 105 is used to receive data from the storage array and transmit it to the data pad 100, corresponding to the data read stage. In other embodiments, the first transmission circuit can also be used to receive data from the storage array and transmit it to the data pad, and the second transmission circuit can also be used to transmit data from the data pad to the storage array.

[0054] In some embodiments, reference Figure 4 The first transmission circuit 103 may include: an input buffer circuit 113 for receiving data transmitted from the data pad 100 corresponding to the input buffer circuit 113; and a latch circuit 123 for receiving and latching data output from the input buffer circuit 113, and outputting the latched data in response to a write clock signal. It is understood that the first transmission circuit 103 is used to transmit data from the data pad 100 to the storage array at this time. In other embodiments, refer to... Figure 5Alternatively, the second transmission circuit 105 may include an input buffer circuit DqIB and a latch circuit DqLat for transmitting data from the data pad 100 to the storage array. The latch circuit 123, in addition to receiving and latching data output from the input buffer circuit 113, can also perform serial-to-parallel conversion processing on the received data; that is, the latch circuit 123 has the function of a serial-to-parallel conversion circuit, and then outputs the latched data in response to the write clock signal.

[0055] It should be noted that the spacing between the input buffer circuit 113 and the electrostatic discharge circuit 101 is different from the spacing between the latch circuit 123 and the electrostatic discharge circuit 101. For the electrostatic discharge circuit 101, the positional relationship between the input buffer circuit 113 and the latch circuit 123 includes the following two cases:

[0056] During the stage of transferring data from data pad 100 to the storage array, the data transfer path is: data pad 100 - electrostatic discharge circuit 101 - input buffer circuit 113 - latch circuit 123. In some embodiments, refer to... Figure 4 Since the input buffer circuit 113 is located between the latch circuit 123 and the electrostatic discharge circuit 101, the first bus 104 does not need to be wound. It can pass through the electrostatic discharge circuit 101, the input buffer circuit 113 and the latch circuit 123 in sequence, which helps to shorten the length of the first bus 104, thereby reducing the parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0057] In other embodiments, reference is made to Figure 6 The latch circuit 123 can also be located between the input buffer circuit 113 and the electrostatic discharge circuit 101.

[0058] In some embodiments, continue to refer to Figure 4 The second transmission circuit 105 may include: a first-in-first-out (FIFO) circuit 115, which receives and transmits data from the storage array; and a driving circuit 125, which receives data output from the FIFO circuit 115 and outputs data to the data pad 100, and the driving circuit 125 is located between the electrostatic discharge circuit 101 and the FIFO circuit 115. It is understood that, in this case, the second transmission circuit 105 is used to receive data from the storage array and transmit it to the data pad 100. In other embodiments, refer to... Figure 5 Alternatively, the first transmission circuit 103 may include an input buffer circuit and a latch circuit for transmitting data from the data pads to the storage array.

[0059] It should be noted that the spacing between the FIFO circuit 115 and the electrostatic discharge circuit 101 is different from the spacing between the drive circuit 125 and the electrostatic discharge circuit 101. For the electrostatic discharge circuit 101, the positional relationship between the FIFO circuit 115 and the drive circuit 125 includes the following two cases:

[0060] During the stage of receiving data from the storage array and transmitting it to the data pad 100, the data transmission path is: FIFO circuit 115 - drive circuit 125 - electrostatic discharge circuit 101 - data pad 100. In some embodiments, refer to Figure 4 Since the driving circuit 125 is located between the first-in-first-out circuit 115 and the electrostatic discharge circuit 101, the second bus 106 does not need to be wound. It can pass through the first-in-first-out circuit 115, the driving circuit 125 and the electrostatic discharge circuit 101 in sequence, which helps to shorten the length of the second bus 106, thereby reducing the parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0061] In other embodiments, reference is made to Figure 6 The first-in-first-out circuit 115 can also be located between the drive circuit 125 and the electrostatic discharge circuit 101.

[0062] In some embodiments, reference Figure 7 The second transmission circuit 105 may further include a parallel-to-serial conversion circuit 135, which is located between the driving circuit 125 and the first-in-first-out circuit 115. The parallel-to-serial conversion circuit 135 is used to convert the data output from the first-in-first-out circuit 115 into parallel and then transmit the converted data to the driving circuit 125.

[0063] It is understandable that the drive circuit 125 and the corresponding parallel-to-serial conversion circuit 135 constitute an output buffer circuit.

[0064] In some embodiments, reference Figure 8 The second transmission circuit 105 may further include a pre-drive circuit 145, which is located between the drive circuit 125 and the first-in-first-out circuit 115. This enhances the driving capability of data transmission by leveraging the driving capabilities of both the pre-drive circuit 145 and the drive circuit 125, thereby improving the accuracy of data transmission.

[0065] It should be noted that in some embodiments, the second transmission circuit 105 may include either the parallel-to-serial conversion circuit 135 or the pre-drive circuit 145; in other embodiments, the second transmission circuit 105 may include both the parallel-to-serial conversion circuit 135 and the pre-drive circuit 145, with the pre-drive circuit 145 located between the drive circuit 125 and the parallel-to-serial conversion circuit 135. During the stage of receiving data from the storage array and transmitting it to the data pad 100, the data reading transmission path may be: first-in-first-out circuit 115 - parallel-to-serial conversion circuit 135 - pre-drive circuit 145 - drive circuit 125. If the parallel-to-serial conversion circuit 135 is located between the drive circuit 125 and the first-in-first-out circuit 115, and the pre-drive circuit 145 is located between the drive circuit 125 and the parallel-to-serial conversion circuit 135, then the second bus 106 does not need to be wound. It can pass through the first-in-first-out circuit 115, the parallel-to-serial conversion circuit 135, the pre-drive circuit 145, the drive circuit 125, and the static discharge circuit 101 in sequence. This helps to shorten the length of the second bus 106, thereby reducing the parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0066] It should be noted that regardless of whether the second transmission circuit 105 contains only two sub-circuits, such as the first-in-first-out circuit 115 and the drive circuit 125; or contains three sub-circuits, such as the first-in-first-out circuit 115, the drive circuit 125 and the parallel-to-serial conversion circuit 135; or the first-in-first-out circuit 115, the drive circuit 125 and the pre-drive circuit 145; or contains four sub-circuits, such as the first-in-first-out circuit 115, the drive circuit 125, the parallel-to-serial conversion circuit 135 and the pre-drive circuit 145; the arrangement of the sub-circuits in the second transmission circuit 105 along the X direction is not limited. Figures 4 to 8 The descriptions provided are merely illustrative and for ease of explanation.

[0067] In some embodiments, reference Figure 9 The integrated circuit structure may include: multiple data pads 100 arranged in the same row, multiple electrostatic discharge circuits 101 arranged in the same row, multiple first transmission circuits 103 arranged in the same row, and multiple second transmission circuits 105 arranged in the same row, wherein the data pads 100, electrostatic discharge circuits 101, first transmission circuits 103, and second transmission circuits 105 correspond to each other. A data pad 100 is electrically connected to a corresponding electrostatic discharge circuit 101 through a redistribution layer 102, and due to the width requirements of the redistribution layer 102, there is a certain gap between the data pads 100 and the electrostatic discharge circuits 101.

[0068] Thus, in conjunction with references Figure 2 and Figure 9By placing the first transmission circuit 103 between the data pad 100 and the electrostatic discharge circuit 101, it is not only beneficial to avoid unnecessary winding lengths in the first bus 104 and the second bus 106, thereby reducing the overall parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure, but also beneficial to improve the space utilization of the area where the redistribution layer 102 is located, thereby increasing the overall integration density of the integrated circuit structure and reducing the overall layout area of ​​the integrated circuit structure.

[0069] In some embodiments, continue to refer to Figure 9 The integrated circuit structure may further include: a data sampling pad 107, a first power supply pad 117, a second power supply pad 127, and a ground pad 137. The data sampling pad 107 receives a data sampling signal, such as an RDQS signal; the level of the first power supply received by the first power supply pad 117 may be higher than the level of the second power supply received by the second power supply pad 127.

[0070] It should be noted that, Figure 9 Data pads 100 are designated as DQ0, DQ1, DQ2, and DQ3. Figures 3 to 8 The absence of a suffix after the DQ designation indicates that it does not specifically refer to a data pad 100. Figure 9 The data sampling pad 107 is labeled RDQS, the first power supply pad 117 is labeled VDDQ, the second power supply pad 127 is labeled VCC, and the ground pad 137 is labeled VSS. Figure 9 The diagram only shows four data pads 100 in the same row. In practical applications, there is no limit to the number of data pads 100 contained in the integrated circuit structure.

[0071] In some embodiments, in conjunction with reference Figure 9 and Figure 10 , Figure 10 for Figure 9 The diagram provided illustrates the partial transmission path layout of the integrated circuit. It should be noted that... Figure 10 Data pads 100 are labeled DQ0, DQ1, DQ2...DQ7, data sampling pads 107 are labeled RDQS, clock pads 147 are labeled WCK, data mask pads 157 are labeled DM, first clock processing circuit 108 is labeled WCK1, second clock processing circuit 118 is labeled WCK2, first data selection module 148 is labeled DPMUX1, and second data selection module 168 is labeled DPMUX2. Figure 10 The diagram only shows eight data pads 100 in the same row. In practical applications, there is no limit to the number of data pads 100 contained in the integrated circuit structure.

[0072] The integrated circuit structure may further include: a first clock processing circuit 108, which provides a first clock signal, and a first transmission circuit 103 outputs data from the data pad 100 in response to the first clock signal; a second clock processing circuit 118, which provides a second clock signal, and a second transmission circuit 105 outputs data from the memory array in response to the second clock signal; wherein the positional arrangement of the first clock processing circuit 108 and the second clock processing circuit 118 corresponds to the positional arrangement of the first transmission circuit 103 and the second transmission circuit 105, that is, along the direction X, the first clock processing circuit 108 and the second clock processing circuit 118 are arranged vertically.

[0073] The first clock processing circuit 108 is connected to the first transmission circuit 103 via a fifth bus 128. In one example, the first clock processing circuit 108 is connected to the latch circuit 123 in the first transmission circuit 103 via the fifth bus 128. The second clock processing circuit 118 is connected to the second transmission circuit 105 via a sixth bus 138. In one example, the second clock processing circuit 118 is connected to the first-in-first-out circuit 115 in the second transmission circuit 105 via the sixth bus 138.

[0074] Figure 11 for Figure 2 The diagram shows the local transmission path layout of the integrated circuit provided. Figure 11 It contains data pads, latch circuits, FIFO circuits, a first clock processing circuit, and a second clock processing circuit. It should be noted that, for ease of comparison, Figure 11 The data pads are represented by DQ0, DQ1...DQ7, the latch circuit is represented by DqLat, the first-in-first-out circuit is represented by DqFiFo, the first clock processing circuit is represented by WCK1, and the second clock processing circuit is represented by WCK2.

[0075] Reference Figure 10 and Figure 11 Since the first clock processing circuit 108 and the second clock processing circuit 118 are arranged vertically along the X direction, the fifth bus 128 does not need to bypass the second clock processing circuit 118 to achieve electrical connection with the first transmission circuit 103, and the sixth bus 138 does not need to bypass the first clock processing circuit 108 to achieve electrical connection with the second transmission circuit 105. This helps to avoid unnecessary winding lengths in the fifth bus 128 and the sixth bus 138, thereby further reducing the parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0076] In some embodiments, the reference continues Figure 9 and Figure 10The integrated circuit structure can be divided into a first region I and a second region II. Both regions I and II include multiple data pads 100 arranged in a row, multiple electrostatic discharge circuits 101 arranged in a row, multiple first transmission circuits 103 arranged in a row, and multiple second transmission circuits 105 arranged in a row. A first clock processing circuit 108 and a second clock processing circuit 118 are located between regions I and II. Regions I and II can include the same number of data pads 100, thereby reducing the data path differences between the first clock processing circuit 108 and the second clock processing circuit 118 and the first transmission circuits 103 and second transmission circuits 105 corresponding to each data pad 100.

[0077] In some embodiments, reference Figure 9 and Figure 10 The integrated circuit structure may further include: a first data selection module 148, which is connected to multiple first transmission circuits 103 via multiple third buses 158, each third bus 158 corresponding to at least one first transmission circuit 103; and a second data selection module 168, which is connected to multiple second transmission circuits 105 via multiple fourth buses 178, each fourth bus 178 corresponding to at least one second transmission circuit 105; wherein the first data selection module 148 and the second data selection module 168 are connected to the memory array and are located on the same side of the first transmission circuit 103 and the second transmission circuit 105, and the positional arrangement of the first data selection module 148 and the second data selection module 168 corresponds to the positional arrangement of the first transmission circuit 103 and the second transmission circuit 105, that is, along the direction X, the first data selection module 148 and the second data selection module 168 are arranged vertically.

[0078] Figure 11 It has a first data selection module and a second data selection module. It should be noted that, for ease of comparison and explanation, Figure 11 The first data selection module is illustrated by DPMUX1, and the second data selection module is illustrated by DPMUX2.

[0079] Reference Figure 10 and Figure 11In the integrated circuit structure provided in this embodiment, the interval between the latch circuit 123 and the first-in-first-out circuit 115 is relatively large. On the one hand, this is beneficial for increasing the interval between the multiple third buses 158, thereby reducing the parasitic capacitance between the multiple third buses 158 and improving the accuracy of writing data. On the other hand, it is beneficial for increasing the interval between the multiple fourth buses 178, thereby reducing the parasitic capacitance between the multiple fourth buses 178 and improving the accuracy of reading data. In addition, since the first data selection module 148 and the second data selection module 168 are arranged vertically along the X direction, the third bus 158 does not need to bypass the second data selection module 168 to achieve electrical connection with the first transmission circuit 103, or the fourth bus 178 does not need to bypass the first data selection module 148 to achieve electrical connection with the second transmission circuit 105. This helps to avoid unnecessary winding lengths in the third bus 158 or the fourth bus 178, thereby further reducing the overall parasitic capacitance of the integrated circuit structure and simplifying the overall layout of the integrated circuit structure.

[0080] In some embodiments, the first data selection module 148 can be a write data module, with one end electrically connected to the storage array and the other end electrically connected to the data pad 100 via the first transmission circuit 103, to process signals transmitted from the data pad 100 to the storage array; the second data selection module 168 can be a read data module, with one end electrically connected to the storage array and the other end electrically connected to the data pad 100 via the second transmission circuit 105, to process signals transmitted from the storage array to the data pad 100. In one example, the first data selection module 148 is connected to the latch circuit 123 in the first transmission circuit 103 via a third bus 158, and the second data selection module 168 is connected to the first-in-first-out circuit 115 in the second transmission circuit 105 via a fourth bus 178.

[0081] In some embodiments, reference Figure 9 and Figure 10 The integrated circuit structure may further include: a data mask pad 157, located in the same row as the data pad 100, for transmitting data mask signals; a third transmission circuit 167, located in the same row as the first transmission circuit 103, for transmitting data mask signals from the data mask pad 157; and a fourth transmission circuit 177, located in the same row as the fourth transmission circuit 177, for receiving data mask signals from the memory array and transmitting them to the data mask pad 157.

[0082] In some embodiments, the third transmission circuit 167 and the first data selection module 148 can be electrically connected via the seventh bus 188, and the fourth transmission circuit 177 and the second data selection module 168 can be electrically connected via the eighth bus 198.

[0083] In some embodiments, reference Figure 9 , Figure 10 and Figure 12 , Figure 12 for Figure 10 A schematic diagram showing the structure between the third bus 158 or the fourth bus 178 corresponding to the eight data pads 100, and the seventh bus 188 or the eighth bus 198 corresponding to the data mask pad 157.

[0084] Along the direction X from the first transmission circuit 103 to the second transmission circuit 105, the initial two third buses 158 are the longest and shortest, respectively. The lengths of adjacent third buses 158 at odd-numbered positions vary according to a first trend, while the lengths of adjacent third buses 158 at even-numbered positions vary according to a second trend. The first trend is either increasing or decreasing, and the second trend is either increasing or decreasing. By setting adjacent third buses 158 to be of different lengths, the facing area between adjacent third buses 158 is reduced, thereby further reducing the parasitic capacitance between adjacent third buses 158 and thus reducing the overall parasitic capacitance of the integrated circuit structure.

[0085] Furthermore, the length of the seventh bus 188 or the eighth bus 198 varies not only with the length of the adjacent third bus 158 at odd positions according to a first trend, but also with the length of the adjacent third bus 158 at even positions according to a second trend.

[0086] In some embodiments, reference Figure 9 , Figure 10 and Figure 12 Along the direction X from the first transmission circuit 103 to the second transmission circuit 105, the initial two fourth buses 178 are the longest and shortest, respectively. The lengths of adjacent fourth buses 178 at odd-numbered positions vary according to a first trend, while the lengths of adjacent fourth buses 178 at even-numbered positions vary according to a second trend. The first trend is either increasing or decreasing, and the second trend is either increasing or decreasing. By setting adjacent fourth buses 178 to be of different lengths, the facing area between adjacent fourth buses 178 is reduced, thereby further reducing the parasitic capacitance between adjacent fourth buses 178 and thus reducing the overall parasitic capacitance of the integrated circuit structure.

[0087] It should be noted that the reference Figure 12The first two third buses 158 or fourth buses 178 are the two third buses 158 or fourth buses 178 corresponding to data pads DQ7 and DQ0; the third buses 158 or fourth buses 178 in odd-numbered positions are the third buses 158 or fourth buses 178 corresponding to data pads DQ7, DQ6, DQ5 and DQ4; the third buses 158 or fourth buses 178 in even-numbered positions are the third buses 158 or fourth buses 178 corresponding to data pads DQ0, DQ1, DQ2 and DQ3.

[0088] Furthermore, if the lengths of adjacent third bus 158 or fourth bus 178 at odd-numbered positions change in an increasing trend, then along direction X, the first starting third bus 158 or fourth bus 178 has the shortest length, and the second starting third bus 158 or fourth bus 178 has the longest length; if the lengths of adjacent third bus 158 or fourth bus 178 at odd-numbered positions change in a decreasing trend, then along direction X, the first starting third bus 158 or fourth bus 178 has the longest length, and the second starting third bus 158 or fourth bus 178 has the shortest length.

[0089] In summary, the first transmission circuit 103 and the second transmission circuit 105 are located on opposite sides of the electrostatic discharge circuit 101, resulting in shorter distances between them and the electrostatic discharge circuit 101. This shortens the lengths of the first bus 104 and the second bus 106, thereby reducing the overall parasitic capacitance of the integrated circuit structure and lowering its power consumption. Furthermore, since the data pads 100 and the electrostatic discharge circuit 101 require a certain distance for data transmission, placing the first transmission circuit 103 within this gap improves the integration density of the integrated circuit structure and reduces its overall layout area.

[0090] Another embodiment of this disclosure provides a memory including the integrated circuit structure provided in the foregoing embodiments. The parts corresponding to the foregoing embodiments will not be described again here.

[0091] The memory includes: a storage cell; and the integrated circuit structure provided in the foregoing embodiments. Specifically, the memory can be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, or other types of memory.

[0092] As can be seen from the foregoing analysis, the first transmission circuit 103 and the second transmission circuit 105 in the integrated circuit structure are located on both sides of the electrostatic discharge circuit 101, which is beneficial to reducing the overall parasitic capacitance of the integrated circuit structure and thus reducing the power consumption of the integrated circuit structure. It is also beneficial to increase the integration density of the integrated circuit structure and reduce the overall layout area of ​​the integrated circuit structure. Therefore, it is beneficial to reduce the overall parasitic capacitance of the memory containing the integrated circuit structure and thus reduce the power consumption of the memory. It is also beneficial to increase the integration density of the memory and reduce the overall layout area of ​​the memory.

[0093] Another embodiment of this disclosure provides an integrated circuit layout for forming the integrated circuit structure provided in the foregoing embodiments. The following will be combined with… Figures 3 to 15 The integrated circuit layout provided in another embodiment of this disclosure will be described in detail, and the parts corresponding to the foregoing embodiments will not be repeated here.

[0094] in, Figure 13 for Figure 3 The diagram shows the layout structure of the integrated circuit provided in the document. Figure 14 for Figure 9 The diagram shows the layout structure of the integrated circuit provided in the document. Figure 15 for Figure 10 The diagram shows the layout structure of the integrated circuit provided in the document.

[0095] Reference Figure 3 and Figure 13 The integrated circuit layout includes: a data pad area 200, used to define the positions of multiple data pads 100 in the same row; an electrostatic discharge area 201, located on one side of the data pad area 200, used to define the positions of multiple electrostatic discharge circuits 101 in the same row; a first transmission area 203, located between the data pad area 200 and the electrostatic discharge area 201, used to define the positions of the first transmission circuits 103 in the same row, the first transmission circuits 103 and the electrostatic discharge circuits 101 being electrically connected via a first bus 104; and a second transmission area 205, located on the side of the electrostatic discharge area 201 away from the first transmission area 203, used to define the positions of multiple second transmission circuits 105 in the same row, the second transmission circuits 105 and the data pads 100 being electrically connected via a second bus 106; wherein, one of the first transmission circuits 103 and the second transmission circuits 105 is used to transmit data from the data pads 100 to a memory array (not shown in the figure), and the other is used to receive data from the memory array and transmit it to the data pads 100.

[0096] This helps to reduce the distance between the first transmission area 203 and the second transmission area 205 and the electrostatic discharge area 201, and helps to shorten the length of the first bus 104 and the second bus 106, thereby reducing the parasitic capacitance of the integrated circuit structure formed according to the integrated circuit layout and reducing the power consumption of the integrated circuit structure. On the other hand, placing the first transmission area 203 between the data pad 100 and the electrostatic discharge circuit 101 helps to improve the utilization rate of the integrated circuit layout, thereby increasing the integration density of the integrated circuit structure formed according to the integrated circuit layout and reducing the overall layout area of ​​the integrated circuit structure.

[0097] In some embodiments, the first transmission circuit 103 is used to transmit data from the data pad 100 to the storage array, and the second transmission circuit 105 is used to receive data from the storage array and transmit it to the data pad 100. In other embodiments, the first transmission circuit may also be used to receive data from the storage array and transmit it to the data pad, and the second transmission circuit may also be used to transmit data from the data pad to the storage array.

[0098] In some embodiments, in conjunction with reference Figure 9 and Figure 14 The first transmission area 203 includes: an input buffer 213 for defining multiple input buffer circuits 113 in the same row; and a latch area 223 located on the side of the input buffer 213 away from the electrostatic discharge area 201, for defining multiple latch circuits 123 in the same row. It is understood that the first transmission area 203 is subsequently used to transmit data from the data pads 100 to the storage array. In other embodiments, the second transmission area may include an input buffer and a latch area for subsequent transmission of data from the data pads to the storage array.

[0099] It should be noted that, in some embodiments, references Figure 14 The input buffer 213 is located between the latch area 223 and the electrostatic discharge area 201; in other embodiments, the latch area may be located between the input buffer and the electrostatic discharge area.

[0100] In some embodiments, continue to refer to Figure 9 and Figure 14The second transmission area 205 includes: a first-in-first-out (FIFO) area 215, used to define a plurality of FIFO circuits 115 in the same row; and a drive circuit area 225, located between the FIFO area 215 and the electrostatic discharge area 201, used to define a plurality of drive circuits 125 in the same row. It is understood that the second transmission area 205 is subsequently used to receive data from the storage array and transmit it to the data pads 100. In other embodiments, the first transmission area may include both the FIFO area and the drive circuit area, which are then used to transmit data from the data pads to the storage array.

[0101] It should be noted that, in some embodiments, references Figure 14 The drive circuit area 225 is located between the first-in-first-out area 215 and the electrostatic discharge area 201; in other embodiments, the first-in-first-out area may be located between the drive circuit area and the electrostatic discharge area.

[0102] In some embodiments, continue to refer to Figure 14 The second transmission area 205 may further include a parallel-to-serial conversion area 235, which is located between the drive circuit area 225 and the first-in-first-out area 215.

[0103] In some embodiments, continue to refer to Figure 14 The second transmission area 205 may further include a pre-drive circuit area 245, which is located between the drive circuit area 225 and the first-in-first-out area 215.

[0104] It should be noted that in some embodiments, the second transmission area 205 may include either the parallel-to-serial conversion area 235 or the pre-drive circuit area 245; in other embodiments, the second transmission area 205 may include both the parallel-to-serial conversion area 235 and the pre-drive circuit area 245, and the pre-drive circuit area 245 is located between the drive circuit area 225 and the parallel-to-serial conversion area 235.

[0105] It should be noted that regardless of whether the second transmission area 205 contains only two sub-regions, such as the first-in-first-out (FIFO) area 215 and the drive circuit area 225; or contains three sub-regions, such as the FIFO area 215, the drive circuit area 225 and the parallel-to-serial conversion area 235; or the FIFO area 215, the drive circuit area 225 and the pre-drive circuit area 245; or contains four sub-regions, such as the FIFO area 215, the drive circuit area 225, the parallel-to-serial conversion area 235 and the pre-drive circuit area 245; the arrangement of the sub-regions in the second transmission area 205 along the X direction is not restricted. Figure 14 The descriptions provided are merely illustrative and for ease of explanation.

[0106] In some embodiments, continue to refer to Figure 14The integrated circuit layout may also include: a data sampling pad area 207, a first power pad area 217, a second power pad area 227, and a ground pad area 237.

[0107] It should be noted that, Figure 14 The data pad area 200 is identified by DQ0, DQ1, DQ2, and DQ3. Figure 13 The absence of a suffix after the DQ designation indicates that it does not specifically refer to a data pad area 200. Figure 14 The data sampling pad area 207 is identified by RDQS, the first power pad area 217 by VDDQ, the second power pad area 227 by VCC, and the ground pad area 237 by VSS. Figure 14 The diagram only shows four data pad areas 200 in the same row. In practical applications, there is no limit to the number of data pad areas 200 included in the integrated circuit layout.

[0108] In some embodiments, in conjunction with reference Figure 10 , Figure 14 and Figure 15 The integrated circuit layout may also include: a first clock region 208 for defining a first clock processing circuit 108; and a second clock region 218 for defining a second clock processing circuit 118. The positional arrangement of the first clock region 208 and the second clock region 218 corresponds to the positional arrangement of the first transmission region 203 and the second transmission region 205, that is, along the direction X, the first clock region 208 and the second clock region 218 are arranged vertically.

[0109] It should be noted that, Figure 15 Data pad area 200 is labeled DQ0, DQ1, DQ2...DQ7, data sampling pad area 207 is labeled RDQS, clock pad area 247 is labeled WCK, data mask pad area 257 is labeled DM, first clock area 208 is labeled WCK1, second clock area 218 is labeled WCK2, first module area 248 is labeled DPMUX1, and second module area 268 is labeled DPMUX2. Figure 15 The diagram only shows eight data pad areas 200 in the same row. In practical applications, there is no limit to the number of data pad areas 200 included in the integrated circuit layout.

[0110] The integrated circuit layout may further include: a fifth bus area (not shown in the figure) for defining the fifth bus 128, and a sixth bus area (not shown in the figure) for defining the sixth bus 138. The first clock area 208 and the first transmission area 203 are connected via the fifth bus area. In one example, the first clock area 208 and the latch area 223 in the first transmission area 203 are connected via the fifth bus area. The second clock area 218 and the second transmission area 205 are connected via the sixth bus area. In one example, the second clock area 218 and the first-in-first-out area 215 in the second transmission area 205 are connected via the sixth bus area.

[0111] In some embodiments, reference Figure 14 and Figure 15 The integrated circuit layout can be divided into a first region I and a second region II. Both the first region I and the second region II include multiple data pad areas 200 in a row, multiple electrostatic discharge areas 201 in a row, multiple first transmission areas 203 in a row, and multiple second transmission areas 205 in a row; the first clock area 208 and the second clock area 218 are located between the first region I and the second region II.

[0112] In some embodiments, the integrated circuit layout further includes: a first module area 248 for defining a first data selection module 148; a plurality of third bus areas 258 for defining a plurality of third buses 158, the third buses 158 connecting the first data selection module 148 and the corresponding first transmission circuit 103; a second module area 268 for defining a second data selection module 168, the first module area 248 and the second module area 268 being located on the same side of the first transmission area 203 and the second transmission area 205, and the positional arrangement of the first module area 248 and the second module area 268 corresponding to the positional arrangement of the first transmission area 203 and the second transmission area 205; and a plurality of fourth bus areas 278 for defining a plurality of fourth buses 178, the fourth buses 178 connecting the second data selection module 168 and the corresponding second transmission circuit 105.

[0113] In the integrated circuit layout provided in this embodiment, the spacing between the latch area 223 and the first-in-first-out area 215 is relatively large. On the one hand, this helps to increase the spacing between multiple third bus areas 258, thereby reducing the parasitic capacitance between the third buses 158 formed by the multiple third bus areas 258 and improving the accuracy of data writing. On the other hand, it helps to increase the spacing between multiple fourth bus areas 278, thereby reducing the parasitic capacitance between the fourth buses 178 formed by the multiple fourth bus areas 278 and improving the accuracy of data reading. In addition, since the first module area 248 and the second module area 268 are arranged vertically along the X direction, the third bus area 258 does not need to bypass the second module area 268 to connect with the first transmission area 203, or the fourth bus area 278 does not need to bypass the first module area 248 to connect with the second transmission area 205. This helps to avoid unnecessary winding lengths in the third bus area 258 or the fourth bus area 278, thereby further simplifying the overall layout of the integrated circuit.

[0114] In some embodiments, in conjunction with reference Figure 10 and Figure 15 The integrated circuit layout may also include: a data mask pad area 257, located in the same row as the data pad area 200, used to define the data mask pad 157; a third transmission area 267, located in the same row as the first transmission area 203, used to define the third transmission area 267; and a fourth transmission area 277, located in the same row as the second transmission area 205, used to define the fourth transmission circuit 177.

[0115] In some embodiments, in conjunction with reference Figure 10 and Figure 15 The integrated circuit layout may also include: a seventh bus area 288 for defining a seventh bus 188, an eighth bus area 298 for defining an eighth bus 198, a third transmission area 267 and a first module area 248 that can be connected through the seventh bus area 288, and a fourth transmission area 277 and a second module area 268 that can be connected through the eighth bus area 298.

[0116] In some embodiments, reference Figure 15Along the direction X from the first transmission region 203 to the second transmission region 205, the initial two third bus regions 258 are the longest and shortest, respectively. The lengths of adjacent third bus regions 258 at odd-numbered positions vary according to a first trend, while the lengths of adjacent third bus regions 258 at even-numbered positions vary according to a second trend. The first trend is either increasing or decreasing, and the second trend is either increasing or decreasing. Thus, by setting adjacent third bus regions 258 to be of different lengths, the facing area between adjacent third bus regions 258 is reduced, thereby helping to reduce the overall parasitic capacitance of the integrated circuit structure formed based on the integrated circuit layout.

[0117] Furthermore, the length of the seventh bus area 288 or the eighth bus area 298 varies not only with the length of the adjacent third bus area 258 at odd positions according to a first trend, but also with the length of the adjacent third bus area 258 at even positions according to a second trend.

[0118] In some embodiments, reference Figure 15 Along the direction X from the first transmission region 203 to the second transmission region 205, the initial two fourth bus regions 278 are the longest and shortest, respectively. The lengths of adjacent fourth bus regions 278 at odd-numbered positions vary according to a first trend, while the lengths of adjacent fourth bus regions 278 at even-numbered positions vary according to a second trend. The first trend is either increasing or decreasing, and the second trend is either increasing or decreasing. Thus, by setting adjacent fourth bus regions 278 to be of different lengths, the facing area between adjacent fourth bus regions 278 is reduced, thereby helping to reduce the overall parasitic capacitance of the integrated circuit structure formed based on the integrated circuit layout.

[0119] It should be noted that the reference Figure 15 The first two third bus areas 258 or fourth bus areas 278 are the two third bus areas 258 or fourth bus areas 278 corresponding to data pad areas DQ7 and DQ0; the third bus areas 258 or fourth bus areas 278 in odd-numbered positions are the third bus areas 258 or fourth bus areas 278 corresponding to data pad areas DQ7, DQ6, DQ5 and DQ4; the third bus areas 258 or fourth bus areas 278 in even-numbered positions are the third bus areas 258 or fourth bus areas 278 corresponding to data pad areas DQ0, DQ1, DQ2 and DQ3.

[0120] Furthermore, if the lengths of adjacent third bus regions 258 or fourth bus regions 278 at odd-numbered positions change in an increasing trend, then along direction X, the first starting third bus region 258 or fourth bus region 278 is the shortest, and the second starting third bus region 258 or fourth bus region 278 is the longest; if the lengths of adjacent third bus regions 258 or fourth bus regions 278 at odd-numbered positions change in a decreasing trend, then along direction X, the first starting third bus region 258 or fourth bus region 278 is the longest, and the second starting third bus region 258 or fourth bus region 278 is the shortest.

[0121] In summary, the first transmission region 203 and the second transmission region 205 are located on both sides of the electrostatic discharge region 201, which helps to reduce the distance between the first transmission region 203 and the second transmission region 205 and the electrostatic discharge region 201, and helps to shorten the length of the first bus 104 and the second bus 106. This helps to reduce the parasitic capacitance of the integrated circuit structure formed according to the integrated circuit layout, thereby reducing the power consumption of the integrated circuit structure. On the other hand, placing the first transmission region 203 between the data pad 100 and the electrostatic discharge circuit 101 helps to improve the utilization rate of the integrated circuit layout, thereby increasing the integration density of the integrated circuit structure formed according to the integrated circuit layout and reducing the overall layout area of ​​the integrated circuit structure.

[0122] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. An integrated circuit structure, characterized in that, include: Data pads; An electrostatic discharge circuit is located on one side of the data pad and is electrically connected to the data pad; The first transmission circuit is located on the side of the electrostatic discharge circuit facing the data pad, and the first transmission circuit and the electrostatic discharge circuit are electrically connected through a first bus. The second transmission circuit is located on the side of the electrostatic discharge circuit away from the first transmission circuit, and the second transmission circuit is electrically connected to the electrostatic discharge circuit through a second bus. In this circuit, one of the first transmission circuit and the second transmission circuit is used to transmit data from the data pad to the storage array, and the other is used to receive data from the storage array and transmit it to the data pad.

2. The integrated circuit structure as described in claim 1, characterized in that, The first transmission circuit is used to transmit data from the data pad to the storage array, and the second transmission circuit is used to receive data from the storage array and transmit it to the data pad.

3. The integrated circuit structure as described in claim 1, characterized in that, The first transmission circuit includes: An input buffer circuit receives data transmitted from the data pads corresponding to the input buffer circuit. The latching circuit receives and latches data output from the input buffer circuit, and outputs the latched data in response to the write clock signal.

4. The integrated circuit structure as described in claim 3, characterized in that, The input buffer circuit is located between the latch circuit and the electrostatic discharge circuit.

5. The integrated circuit structure as described in claim 1, characterized in that, The second transmission circuit includes: A first-in-first-out (FIFO) circuit is used to receive and transmit data from the storage array; A driving circuit is provided, which is used to receive data output from the first-in-first-out circuit and output the data to the data pad, and the driving circuit is located between the electrostatic discharge circuit and the first-in-first-out circuit.

6. The integrated circuit structure as described in claim 5, characterized in that, The second transmission circuit further includes: A parallel-to-serial conversion circuit is located between the driving circuit and the first-in-first-out (FIFO) circuit. It is used to convert the data output from the FIFO circuit into parallel-to-serial data and transmit the converted data to the driving circuit.

7. The integrated circuit structure as described in claim 5, characterized in that, The second transmission circuit further includes: A pre-drive circuit is located between the drive circuit and the first-in-first-out circuit.

8. The integrated circuit structure as described in claim 1, characterized in that, The integrated circuit structure also includes: A first clock processing circuit is used to provide a first clock signal, and a first transmission circuit outputs data from the data pads in response to the first clock signal. A second clock processing circuit is used to provide a second clock signal, and a second transmission circuit outputs data from the memory array in response to the second clock signal. The positional arrangement of the first clock processing circuit and the second clock processing circuit corresponds to the positional arrangement of the first transmission circuit and the second transmission circuit.

9. The integrated circuit structure as described in claim 1, characterized in that, The integrated circuit structure also includes: A first data selection module is connected to multiple first transmission circuits via multiple third buses, and each third bus corresponds to at least one first transmission circuit. The second data selection module is connected to multiple second transmission circuits via multiple fourth buses, and each of the fourth buses corresponds to at least one second transmission circuit. The first data selection module and the second data selection module are connected to the storage array and are located on the same side of the first transmission circuit and the second transmission circuit, and the positional arrangement of the first data selection module and the second data selection module corresponds to the positional arrangement of the first transmission circuit and the second transmission circuit.

10. The integrated circuit structure as described in claim 1, characterized in that, The integrated circuit structure includes: The data pads, electrostatic discharge circuits, first transmission circuits, and second transmission circuits are arranged in the same row, and the data pads, electrostatic discharge circuits, first transmission circuits, and second transmission circuits correspond to each other.

11. The integrated circuit structure as described in claim 1, characterized in that, The integrated circuit structure also includes: Data mask pads, located in the same row as the data pads, are used to transmit data mask signals; The third transmission circuit, located in the same row as the first transmission circuit, is used to transmit the data mask signal from the data mask pad; A fourth transmission circuit, located in the same row as the fourth transmission circuit, is used to receive the data mask signal from the storage array and transmit it to the data mask pad.

12. A memory, characterized in that, include: Storage unit; The integrated circuit structure as described in any one of claims 1-11.

13. An integrated circuit layout, characterized in that, include: The data pad area is used to define the positions of multiple data pads in the same row; An electrostatic discharge area, located on one side of the data pad area, is used to define the positions of multiple electrostatic discharge circuits in the same row; The first transmission area, located between the data pad area and the electrostatic discharge area, is used to define the positions of multiple first transmission circuits in the same row. The first transmission circuits and the electrostatic discharge circuits are electrically connected through a first bus. The second transmission area is located on the side of the electrostatic discharge area away from the first transmission area. It is used to define the positions of multiple second transmission circuits in the same row. The second transmission circuits are electrically connected to the data pads through a second bus. In this circuit, one of the first transmission circuit and the second transmission circuit is used to transmit data from the data pad to the storage array, and the other is used to receive data from the storage array and transmit it to the data pad.

14. The integrated circuit layout as described in claim 13, characterized in that, The first transmission circuit is used to transmit data from the data pads to the storage array, and the second transmission circuit is used to receive data from the storage array and transmit it to the data pads.

15. The integrated circuit layout as described in claim 13, characterized in that, The first transmission area includes: Input buffers are used to define multiple input buffer circuits in the same row; A latch area, located on the side of the input buffer away from the electrostatic discharge area, is used to define multiple latch circuits in the same row.

16. The integrated circuit layout as described in claim 13, characterized in that, The second transmission area includes: First-in-first-out (FIFO) area is used to define multiple FIFO circuits in the same row; The drive circuit area, located between the first-in-first-out area and the electrostatic discharge area, is used to define multiple drive circuits in the same row.

17. The integrated circuit layout as described in claim 13, characterized in that, The integrated circuit layout also includes: The first clock zone is used to define the first clock processing circuit. The second clock region is used to define the second clock processing circuit, and the positional arrangement of the first clock region and the second clock region corresponds to the positional arrangement of the first transmission region and the second transmission region.

18. The integrated circuit layout as described in claim 13, characterized in that, The integrated circuit layout also includes: The first module area is used to define the first data selection module; Multiple third bus areas are used to define multiple third buses, wherein the third buses connect the first data selection module and the corresponding first transmission circuit; The second module area is used to define the second data selection module. The first module area and the second module area are located on the same side of the first transmission area and the second transmission area, and the positional arrangement of the first module area and the second module area corresponds to the positional arrangement of the first transmission area and the second transmission area. Multiple fourth bus areas are used to define multiple fourth buses, which connect the second data selection module and the corresponding second transmission circuit.

19. The integrated circuit layout as described in claim 18, characterized in that, In the direction from the first transmission area to the second transmission area, the two initial third bus areas are the longest and the shortest, respectively; the lengths of adjacent third bus areas at odd-numbered positions among the multiple third bus areas change according to a first trend, and the lengths of adjacent third bus areas at even-numbered positions among the multiple third bus areas change according to a second trend, wherein the first trend is either increasing or decreasing, and the second trend is either increasing or decreasing.

20. The integrated circuit layout as described in claim 18, characterized in that, In the direction from the first transmission area to the second transmission area, the two initial fourth bus areas are the longest and the shortest, respectively; the lengths of adjacent fourth bus areas at odd-numbered positions among the multiple fourth bus areas change according to a first trend, and the lengths of adjacent fourth bus areas at even-numbered positions among the multiple fourth bus areas change according to a second trend, wherein the first trend is either increasing or decreasing, and the second trend is either increasing or decreasing.

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