A lateral and longitudinal power mosfet device and method of manufacture
Patent Information
- Application Number
- CN202310459362.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-25
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2043-04-25
AI Technical Summary
但重掺杂垂直沉片，尤其是垂直沉片的上半部分会直接影响到器件内部承担电压和参与导电的漂移区，从而影响器件的耐压和阈值等电特性
[0036]本发明的有益效果为：本发明在传统的具有重掺杂垂直沉片的横纵向功率器件基础上，提出一种具有绝缘介质埋层的横纵向功率MOSFET器件及其制造方法。通过在器件内部漂移区下方，垂直沉片的两侧引入绝缘介质埋层结构，有效地抑制重掺杂垂直沉片对器件内部漂移区的不良影响，使得器件的耐压和导通特性更加稳定。
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Figure CN116417501B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to power semiconductor technology, specifically to a horizontal and vertical power MOSFET device and its manufacturing method. Background Technology
[0002] Power semiconductor devices are devices capable of handling large currents and high voltages; also known as power electronic devices, they are indispensable components in modern electronic systems. Power MOSFET devices have advantages such as high input impedance, low conduction loss, low switching loss, and high reliability, and are often used as electronic switches in power management applications.
[0003] Power MOSFET devices are classified into lateral power MOSFETs and vertical power MOSFETs based on the direction of the current path during conduction. Each type has its own advantages and disadvantages. Lateral power MOSFETs have smaller gate-drain capacitance but larger on-resistance, resulting in larger cell width, lower current density, and poorer overcurrent capability. Vertical power MOSFETs have lower on-resistance and better overcurrent capability, but significant gate parasitic effects (especially large gate-drain capacitance), leading to lower switching speed and higher drive power consumption. To address these issues, TI proposed the NexFET, a lateral-vertical power MOSFET device. It uses a heavily doped vertical substrate to change the carrier movement path of the lateral power MOSFET to a vertical one, which helps to reduce the cell size, improve the device's overcurrent capability, and simultaneously achieve a smaller gate-drain capacitance.
[0004] The heavily doped vertical MOSFET structure effectively addresses the limitations of lateral power MOSFETs in current density and current capability, as well as the gate parasitic effect problem of vertical power MOSFETs. However, the heavily doped vertical MOSFET, especially the upper half, directly affects the drift region inside the device that bears voltage and participates in conduction, thus affecting the device's breakdown voltage and threshold voltage characteristics. Summary of the Invention
[0005] To address the above problems, this invention proposes a horizontal and vertical power MOSFET device and its manufacturing method.
[0006] The technical solution of the present invention is as follows:
[0007] A horizontal and vertical power MOSFET device includes a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, an insulating dielectric buried layer 4, a heavily doped first conductivity type semiconductor vertical wafer 5, a gate dielectric layer 6, a gate polysilicon electrode 7, a second conductivity type semiconductor body region 8, a first conductivity type semiconductor drift region 9, a heavily doped first conductivity type semiconductor source region 10, a heavily doped second conductivity type semiconductor ohmic contact region 12, a dielectric layer 11, and a source metal 13.
[0008] The heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, and the lightly doped second conductivity type semiconductor epitaxial layer 3 is located above the heavily doped first conductivity type semiconductor substrate 2. The heavily doped first conductivity type semiconductor vertical wafer 5 extends from the upper surface of the lightly doped second conductivity type semiconductor epitaxial layer 3 into the lightly doped second conductivity type semiconductor epitaxial layer 3 and into the heavily doped first conductivity type semiconductor substrate 2, connecting the first conductivity type semiconductor drift region 9 and the heavily doped first conductivity type semiconductor substrate 2. The second conductivity type semiconductor body region 8 is located above the lightly doped second conductivity type semiconductor epitaxial layer 3, and has a heavily doped first conductivity type semiconductor source region 10 and a heavily doped second conductivity type semiconductor ohmic contact region 12 inside. The side of the heavily doped first conductivity type semiconductor source region 10 is in contact with the source metal 13. The heavily doped second conductivity type semiconductor ohmic contact region 12 is in contact with the source metal 13 above it; the first conductivity type semiconductor drift region 9 is located in the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductivity type semiconductor vertical wafer 5 and the lightly doped second conductivity type semiconductor body region 8, respectively; the upper surface of the second conductivity type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, which surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the semiconductor body region 8 through the gate dielectric layer 6; the source metal 13 is located on the upper surface of the first insulating dielectric layer 11 and completely covers the area where the first conductivity type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through a contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region 10.
[0009] The feature is that the lightly doped second conductivity type semiconductor epitaxial layer 3 has an insulating dielectric buried layer 4, which is located below the first conductivity type semiconductor drift region 9 and is in direct contact with the heavily doped first conductivity type semiconductor vertical wafer 5, and its width is smaller than that of the first conductivity type semiconductor drift region 9.
[0010] As a preferred approach, the doping concentration in the heavily doped region is greater than 1e19 cm⁻¹. -3 The doping concentration in the lightly doped region is less than 1e17cm. -3The doping concentration range of the first conductivity type semiconductor drift region 9 is 1e17 cm⁻¹. -3 -3e17 cm -3 .
[0011] As a preferred embodiment, the shape of the insulating dielectric buried layer 4 is rectangular or stepped.
[0012] As a preferred embodiment, the semiconductor material is silicon or silicon carbide.
[0013] As a preferred embodiment, the insulating dielectric material is silicon dioxide or silicon nitride.
[0014] As a preferred embodiment, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
[0015] To achieve the above-mentioned objective, the present invention also provides a method for manufacturing the aforementioned horizontal and vertical power MOSFET device, comprising the following steps:
[0016] Step 1, Single crystal silicon preparation and epitaxial growth; A lightly doped second conductivity type semiconductor epitaxial layer 3 is grown on a heavily doped first conductivity type semiconductor substrate 2 using vapor phase epitaxy.
[0017] Step 2, Ion implantation; oxygen or nitrogen ion implantation is performed, followed by annealing to form an insulating dielectric buried layer 4;
[0018] Step 3, trench etching; deposit a hard mask on the lightly doped second conductivity type semiconductor epitaxial layer 3, and selectively etch the hard mask using photolithography. The etching process uses reactive ion etching or plasma etching. The trench is located between the insulating dielectric buried layers 4 and does not directly contact the insulating dielectric buried layers 4.
[0019] Step 4, trench filling; epitaxial growth to form a single crystal vertical wafer 5 of a heavily doped first conductivity type semiconductor;
[0020] Step 5: Oxide layer growth, polysilicon deposition and etching; thermal oxidation growth of gate dielectric layer 6, deposition of gate polysilicon electrode 7 and etching;
[0021] Step 6, ion implantation; forming a second conductivity type semiconductor bulk region 8 by second conductivity type ion implantation;
[0022] Step 7, Ion implantation; Forming a first conductivity type semiconductor drift region 9 by first conductivity type ion implantation;
[0023] Step 8, ion implantation; a heavily doped first conductivity type semiconductor source region 10 is formed by first conductivity type ion implantation;
[0024] Step 9, dielectric layer deposition and contact hole etching; deposit dielectric layer 11, etch contact holes, the etching process adopts reactive ion etching or plasma etching;
[0025] Step 10, ion implantation; ion implantation of heavily doped second conductivity type semiconductor ohmic contact region 12;
[0026] Step 11, metallization; deposit source metal 13, thin the substrate, and form drain metal 1 with back gold.
[0027] As a preferred method, step 2 is further as follows:
[0028] Step 2, ion implantation; perform one or more implantation energies and different masks for oxygen or nitrogen ion implantation, and anneal to form two rectangular or stepped insulating dielectric buried layers 4.
[0029] As a preferred embodiment, steps 2 and 3 are further defined as follows:
[0030] Step 2, ion implantation; perform one or two implantation energies and different masks for oxygen or nitrogen ions, and anneal to form a rectangular or stepped insulating dielectric buried layer 4;
[0031] Step 3, trench etching; deposit a hard mask on the lightly doped second conductivity type semiconductor epitaxial layer 3, and selectively etch the hard mask using photolithography, performing etching in the order of semiconductor, insulating medium and semiconductor, using reactive ion etching or plasma etching.
[0032] As a preferred method, step 2 is further as follows:
[0033] Step 2.1, trench etching; shallow trench etching is performed in the lightly doped second conductivity type semiconductor epitaxial layer 3 with the same depth as the drift region 9 of the first conductivity type semiconductor;
[0034] Step 2.2, Ion implantation; Perform one or two implantation energies and different masks for oxygen or nitrogen ions in the trench, and anneal to form a rectangular or stepped insulating dielectric buried layer 4.
[0035] Step 2.3, trench filling; fill the trench with the same semiconductor as the lightly doped second conductivity type semiconductor epitaxial layer 3.
[0036] The beneficial effects of this invention are as follows: Based on traditional horizontal and vertical power devices with heavily doped vertical substrates, this invention proposes a horizontal and vertical power MOSFET device with an insulating dielectric buried layer and its manufacturing method. By introducing an insulating dielectric buried layer structure on both sides of the vertical substrate below the drift region inside the device, the adverse effects of the heavily doped vertical substrate on the drift region inside the device are effectively suppressed, making the breakdown voltage and conduction characteristics of the device more stable. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of the structure of a horizontal and vertical power MOSFET device according to Embodiment 1 of the present invention;
[0038] Figures 2(a)-2(k) This is a schematic diagram of the manufacturing process of a horizontal and vertical power MOSFET device according to Embodiment 1 of the present invention;
[0039] Figures 3(a)-3(b) This is a schematic diagram of an improved process for a horizontal and vertical power MOSFET device according to Embodiment 1 of the present invention;
[0040] Figures 4(a)-4(c) This is a schematic diagram of an improved process for a horizontal and vertical power MOSFET device according to Embodiment 1 of the present invention;
[0041] Figure 5 This is a schematic diagram of the structure of a horizontal and vertical power MOSFET device according to Embodiment 2 of the present invention.
[0042] The attached diagram lists the components represented by each number as follows:
[0043] 1 is the drain metal, 2 is the heavily doped first conductivity type semiconductor substrate, 3 is the lightly doped second conductivity type semiconductor epitaxial layer, 4 is the insulating dielectric buried layer, 5 is the heavily doped first conductivity type semiconductor vertical wafer, 6 is the gate dielectric layer, 7 is the gate polysilicon electrode, 8 is the second conductivity type semiconductor body region, 9 is the first conductivity type semiconductor drift region, 10 is the heavily doped first conductivity type semiconductor source region, 11 is the dielectric layer, 12 is the heavily doped second conductivity type semiconductor ohmic contact region, and 13 is the source metal. Detailed Implementation
[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0045] Example 1
[0046] A type of horizontal and vertical power MOSFET device, such as Figure 1As shown, it includes drain metal 1, heavily doped first conductivity type semiconductor substrate 2, lightly doped second conductivity type semiconductor epitaxial layer 3, insulating dielectric buried layer 4, heavily doped first conductivity type semiconductor vertical wafer 5, gate dielectric layer 6, gate polysilicon electrode 7, second conductivity type semiconductor body region 8, first conductivity type semiconductor drift region 9, heavily doped first conductivity type semiconductor source region 10, heavily doped second conductivity type semiconductor ohmic contact region 12, dielectric layer 11, and source metal 13;
[0047] The heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, and the lightly doped second conductivity type semiconductor epitaxial layer 3 is located above the heavily doped first conductivity type semiconductor substrate 2. The heavily doped first conductivity type semiconductor vertical wafer 5 extends from the upper surface of the lightly doped second conductivity type semiconductor epitaxial layer 3 into the lightly doped second conductivity type semiconductor epitaxial layer 3 and into the heavily doped first conductivity type semiconductor substrate 2, connecting the first conductivity type semiconductor drift region 9 and the heavily doped first conductivity type semiconductor substrate 2. The second conductivity type semiconductor body region 8 is located above the lightly doped second conductivity type semiconductor epitaxial layer 3, and has a heavily doped first conductivity type semiconductor source region 10 and a heavily doped second conductivity type semiconductor ohmic contact region 12 inside. The side of the heavily doped first conductivity type semiconductor source region 10 is in contact with the source metal 13. The heavily doped second conductivity type semiconductor ohmic contact region 12 is in contact with the source metal 13 above it; the first conductivity type semiconductor drift region 9 is located in the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductivity type semiconductor vertical wafer 5 and the lightly doped second conductivity type semiconductor body region 8, respectively; the upper surface of the second conductivity type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, which surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the semiconductor body region 8 through the gate dielectric layer 6; the source metal 13 is located on the upper surface of the first insulating dielectric layer 11 and completely covers the area where the first conductivity type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through a contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region 10.
[0048] The feature is that the lightly doped second conductivity type semiconductor epitaxial layer 3 has an insulating dielectric buried layer 4, which is located below the first conductivity type semiconductor drift region 9 and is in direct contact with the heavily doped first conductivity type semiconductor vertical wafer 5, and its width is smaller than that of the first conductivity type semiconductor drift region 9.
[0049] The doping concentration in heavily doped regions is greater than 1e19 cm⁻¹ -3 The doping concentration in the lightly doped region is less than 1e17 cm⁻¹ -3 The doping concentration range of the first conductivity type semiconductor drift region 9 is 1e17 cm⁻¹.-3 -3e17 cm -3 .
[0050] As a preferred embodiment, the semiconductor material is silicon or silicon carbide.
[0051] As a preferred embodiment, the insulating dielectric material is silicon dioxide or silicon nitride.
[0052] As a preferred embodiment, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
[0053] To achieve the above-mentioned objectives, the present invention also provides a method for manufacturing the horizontal and vertical power MOSFET device with an insulating dielectric buried layer, comprising the following steps:
[0054] Step 1, preparation and epitaxial growth of single crystal silicon; a lightly doped second conductivity type semiconductor epitaxial layer 3 is grown on a heavily doped first conductivity type semiconductor substrate 2 by vapor phase epitaxy; as shown in Figure 2(a);
[0055] Step 2, ion implantation; oxygen or nitrogen ion implantation is performed, followed by annealing to form an insulating dielectric buried layer 4; as shown in Figure 2(b);
[0056] Step 3, trench etching; deposit a hard mask on the lightly doped second conductivity type semiconductor epitaxial layer 3, selectively etch the hard mask using photolithography, and use reactive ion etching or plasma etching. The trench is located between the insulating dielectric buried layers 4 and does not directly contact the insulating dielectric buried layers 4; as shown in Figure 2(c).
[0057] Step 4, trench filling; epitaxial growth to form a single crystal vertical wafer 5 of a heavily doped first conductivity type semiconductor; due to the certain lateral expansion of epitaxy, the lateral width of the first conductivity type semiconductor vertical wafer 5 below the insulating dielectric buried layer 4 will increase; as shown in Figure 2(d).
[0058] Step 5: Oxide layer growth, polysilicon deposition and etching; thermal oxidation growth of gate dielectric layer 6, deposition and etching of gate polysilicon electrode 7; as shown in Figure 2(e);
[0059] Step 6, ion implantation; a second conductivity type semiconductor bulk region 8 is formed by second conductivity type ion implantation; as shown in Figure 2(f);
[0060] Step 7, ion implantation; a first conductivity type semiconductor drift region 9 is formed by first conductivity type ion implantation; as shown in Figure 2(g);
[0061] Step 8, ion implantation; a heavily doped first conductivity type semiconductor source region 10 is formed by first conductivity type ion implantation; as shown in Figure 2(h);
[0062] Step 9, dielectric layer deposition and contact hole etching; deposit dielectric layer 11, etch contact holes, the etching process adopts reactive ion etching or plasma etching; as shown in Figure 2(i);
[0063] Step 10, ion implantation; ion implantation of heavily doped second conductivity type semiconductor ohmic contact region 12; as shown in Figure 2(j);
[0064] Step 11, metallization; deposit source metal 13, thin the substrate, and form drain metal 1 with back gold. As shown in Figure 2(k);
[0065] The working principle of the present invention will be explained below using the first embodiment as an example:
[0066] Longitudinal and lateral power MOSFET devices employ a special heavily doped vertical substrate structure for conduction. Because the doping concentration difference between the vertical substrate and the drift region is two orders of magnitude, and the upper part of the vertical substrate is in direct contact with the drift region, the vertical substrate affects the movement of charge carriers within the drift region and the surface electric field distribution, thus impacting the device's breakdown voltage and conduction characteristics. This invention addresses this by introducing buried insulating dielectric layers on both sides of the vertical substrate below the drift region within the device. This effectively mitigates the adverse effects of the vertical substrate on the drift region, resulting in more stable breakdown voltage and conduction characteristics and improved device reliability.
[0067] Example 2
[0068] The difference between this embodiment and the first embodiment is that:
[0069] Change steps 2 and 3 of the process flow to:
[0070] Step 2, ion implantation; as shown in Figure 3(a), perform one oxygen ion or nitrogen ion implantation, and anneal to form a rectangular insulating dielectric buried layer 4;
[0071] Step 3, trench etching; as shown in Figure 3(b), a hard mask is deposited on the lightly doped second conductivity type semiconductor epitaxial layer 3, and the hard mask is selectively etched by photolithography, and the etching sequence is semiconductor, insulating medium and semiconductor. The etching process uses reactive ion etching or plasma etching.
[0072] The beneficial effects are as follows: In Example 1, trench etching between the two buried insulating dielectric layers 4 presents an overlay error problem. Furthermore, direct ion implantation of the epitaxial layer makes it impossible to precisely control the depth and position of the buried insulating dielectric layer 4, potentially causing it to shift upwards, reducing the contact area between the drift region and the vertical wafer, thus narrowing the current path and severely affecting the device's conduction characteristics. This embodiment implants the buried insulating dielectric layers on both sides of the heavily doped vertical wafer together, and then performs trench etching, solving the overlay error problem that requires precise trench etching between the buried insulating dielectric layers.
[0073] Example 3
[0074] The difference between this embodiment and the first embodiment is that:
[0075] Change steps 2 and 3 of the process flow to:
[0076] Step 2.1, trench etching; as shown in Figure 4(a), shallow trench etching with the same depth as the drift region 9 of the first conductivity type semiconductor is performed in the lightly doped second conductivity type semiconductor epitaxial layer 3.
[0077] Step 2.2, Ion implantation; As shown in Figure 4(b), oxygen or nitrogen ions are implanted once in the trench, and annealing is performed to form a rectangular insulating dielectric buried layer 4;
[0078] Step 2.3, trench filling; as shown in Figure 4(c), the trench is filled with the same semiconductor as the lightly doped second conductivity type semiconductor epitaxial layer 3.
[0079] Step 3, trench etching; deposit a hard mask on the lightly doped second conductivity type semiconductor epitaxial layer 3, and selectively etch the hard mask using photolithography, performing etching in the order of semiconductor, insulating medium and semiconductor, using reactive ion etching or plasma etching.
[0080] Its beneficial effects are: it improves the direct ion implantation to ion implantation after trenching and then trench filling, which solves the problem of not being able to accurately control the depth and position of the insulating dielectric buried layer 4.
[0081] Example 4
[0082] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that, during the ion implantation step of the insulating dielectric buried layer 4, oxygen ions or nitrogen ions are implanted twice at different depths using different implantation energies and different masks to form an insulating dielectric buried layer 4 with a stepped shape. Since the area closer to the drift region on the upper part of the vertical wafer has a greater impact, the stepped buried layer is designed with a longer upper layer and a shorter lower layer to further suppress the adverse effects of the vertical wafer 5 on the device drift region.
[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A horizontal and vertical power MOSFET device, comprising a drain metal (1), a heavily doped first conductivity type semiconductor substrate (2), a lightly doped second conductivity type semiconductor epitaxial layer (3), an insulating dielectric buried layer (4), a heavily doped first conductivity type semiconductor vertical wafer (5), a gate dielectric layer (6), a gate polysilicon electrode (7), a second conductivity type semiconductor body region (8), a first conductivity type semiconductor drift region (9), a heavily doped first conductivity type semiconductor source region (10), a dielectric layer (11), a heavily doped second conductivity type semiconductor ohmic contact region (12), and a source metal (13); The heavily doped first conductivity type semiconductor substrate (2) is located above the drain metal (1), and the lightly doped second conductivity type semiconductor epitaxial layer (3) is located above the heavily doped first conductivity type semiconductor substrate (2). The heavily doped first conductivity type semiconductor vertical wafer (5) extends from the upper surface of the lightly doped second conductivity type semiconductor epitaxial layer (3) into the lightly doped second conductivity type semiconductor epitaxial layer (3) and into the heavily doped first conductivity type semiconductor substrate (2), connecting the first conductivity type semiconductor drift region (9) and the heavily doped first conductivity type semiconductor substrate (2). The second conductivity type semiconductor body region (8) is located above the lightly doped second conductivity type semiconductor epitaxial layer (3), and has a heavily doped first conductivity type semiconductor source region (10) and a heavily doped second conductivity type semiconductor ohmic contact region (12) inside. The side of the heavily doped first conductivity type semiconductor source region (10) is in contact with the source metal (13). The heavily doped second conductivity type semiconductor ohmic contact region (12) is in contact with the source metal (13) above it; the first conductivity type semiconductor drift region (9) is located in the upper part of the lightly doped second conductivity type semiconductor epitaxial layer (3), and its two sides are in direct contact with the heavily doped first conductivity type semiconductor vertical wafer (5) and the lightly doped second conductivity type semiconductor body region (8) respectively; the upper surface of the second conductivity type semiconductor epitaxial layer (3) is covered with an insulating dielectric layer (11), and the insulating dielectric layer (11) surrounds the gate polysilicon electrode (7); the gate polysilicon electrode (7) is isolated from the semiconductor body region (8) through the gate dielectric layer (6); the source metal (13) is located on the upper surface of the first insulating dielectric layer (11) and completely covers the area where the first conductivity type semiconductor drift region (9) is located; the source metal (13) extends into the semiconductor material through the contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region (10); Its features are, The lightly doped second conductivity type semiconductor epitaxial layer (3) has an insulating dielectric buried layer (4), which is located below the first conductivity type semiconductor drift region (9) and in direct contact with the heavily doped first conductivity type semiconductor vertical wafer (5), and its width is smaller than that of the first conductivity type semiconductor drift region (9).
2. The horizontal and vertical power MOSFET device according to claim 1, characterized in that: The doping concentration in heavily doped regions is greater than 1e19 cm⁻¹ -3 The doping concentration in the lightly doped region is less than 1e17 cm⁻¹ -3 The doping concentration range of the first conductivity type semiconductor drift region (9) is 1e17 cm⁻¹. -3 -3e17 cm -3 .
3. A horizontal and vertical power MOSFET device according to claim 1, characterized in that: The shape of the insulating dielectric buried layer (4) is rectangular or stepped.
4. A horizontal and vertical power MOSFET device according to claim 1, characterized in that: The semiconductor material is silicon or silicon carbide.
5. A horizontal and vertical power MOSFET device according to claim 1, characterized in that: The insulating dielectric material is silicon dioxide or silicon nitride.
6. A horizontal and vertical power device according to claim 1, characterized in that: The first type of semiconductor is an N-type semiconductor, and the second type of semiconductor is a P-type semiconductor; or the first type of semiconductor is a P-type semiconductor, and the second type of semiconductor is an N-type semiconductor.
7. A method for manufacturing a horizontal and vertical power MOSFET device according to any one of claims 1 to 6, characterized in that... Includes the following steps: Step 1, single crystal silicon preparation and epitaxial growth; a lightly doped second conductivity type semiconductor epitaxial layer (3) is grown on a heavily doped first conductivity type semiconductor substrate (2) by vapor phase epitaxy. Step 2, Ion implantation; oxygen or nitrogen ion implantation is performed, followed by annealing to form an insulating dielectric buried layer (4); Step 3, trench etching; A hard mask is deposited on a lightly doped second conductivity type semiconductor epitaxial layer (3), and the hard mask is selectively etched using photolithography. The etching process uses reactive ion etching or plasma etching. The trenches are located between the insulating dielectric buried layers (4) and do not directly contact the insulating dielectric buried layers (4). Step 4, trench filling; epitaxial growth to form a single crystal vertical wafer of a heavily doped first conductivity type semiconductor (5); Step 5: Oxide layer growth, polysilicon deposition and etching; A gate dielectric layer (6) is grown by thermal oxidation, and a gate polysilicon electrode (7) is deposited and etched. Step 6, ion implantation; a second conductivity type semiconductor body region (8) is formed by second conductivity type ion implantation; Step 7, ion implantation; A first conductivity type semiconductor drift region (9) is formed by ion implantation of the first conductivity type; Step 8, ion implantation; A heavily doped first conductivity type semiconductor source region (10) is formed by first conductivity type ion implantation; Step 9, dielectric layer deposition and contact hole etching; deposit dielectric layer (11), etch contact holes, the etching process adopts reactive ion etching or plasma etching; Step 10, ion implantation; Ion implantation heavily doped second conductivity type semiconductor ohmic contact region (12); Step 11, metallization; deposit source metal (13), thin the substrate, and form drain metal (1) with back gold.
8. A method for manufacturing a transverse and longitudinal power MOSFET device with an insulating dielectric buried layer according to claim 7, characterized in that... Step 2 further includes: Step 2, ion implantation; perform one or more implantation energies and different masks for oxygen or nitrogen ion implantation, and anneal to form two rectangular or stepped insulating dielectric buried layers (4).
9. A method for manufacturing a transverse and longitudinal power MOSFET device with an insulating dielectric buried layer according to claim 7, characterized in that... Steps 2 and 3 are further as follows: Step 2, ion implantation; perform one or two implantation energies and different masks for oxygen or nitrogen ions, and anneal to form a rectangular or stepped insulating dielectric buried layer (4); Step 3, trench etching; A hard mask is deposited on a lightly doped second conductivity type semiconductor epitaxial layer (3), and the hard mask is selectively etched by photolithography. The etching sequence is semiconductor, insulating medium and semiconductor. The etching process uses reactive ion etching or plasma etching.
10. A method for manufacturing a horizontal and vertical power MOSFET device according to claim 9, characterized in that... Step 2 further includes: Step 2.1, trench etching; shallow trench etching with the same depth as the drift region (9) of the first conductivity type semiconductor is performed in the lightly doped second conductivity type semiconductor epitaxial layer (3); Step 2.2, Ion implantation; oxygen or nitrogen ions are implanted once or twice in the trench with different implantation energies and different masks, and annealed to form a rectangular or stepped insulating dielectric buried layer (4); Step 2.3, trench filling; fill the trench with the same semiconductor as the lightly doped second conductivity type semiconductor epitaxial layer (3).