Trench DMOS device and method of manufacturing the same

Abstract

The present application relates to a trench DMOS device and a method for manufacturing the same, the trench DMOS device comprising an extension gate layer arranged on the inner surface of a gate insulating layer, the extension gate layer comprising a first extension gate region of a second conductive type, a second extension gate region of a first conductive type and a third extension gate region, the trench DMOS device improves the contradictory relationship between the withstand voltage and the specific on-resistance, so that the trench DMOS device not only has high withstand voltage, but also has low specific on-resistance. Moreover, the trench DMOS device is a longitudinal withstand voltage structure, which reduces the device area, thereby reducing the on-resistance of the device, at the same time, the source region and the drain region can be led out from the front surface, which is compatible with CMOS.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device technology, and in particular to a trench-type DMOS device and its fabrication method. Background Technology

[0002] In BCD process development, multiple devices, including Bipolar, CMOS, and DMOS, are developed collaboratively, with NLDMOS being the most critical. In general process technology, RESURF technology is commonly used to reduce the surface electric field in the LDMOS drift region and improve its breakdown voltage performance. However, to achieve the required breakdown voltage, the drift region length needs to be further increased. More importantly, the relationship between the device's on-resistance Rdson and the breakdown voltage BV can be expressed as: Rdson ∝ BV 2.5 In other words, increasing the drift region size increases the on-resistance, leading to a sharp increase in power consumption and a decrease in device switching speed. VMODS uses a vertical breakdown voltage, thus changing the breakdown voltage from that of LDMOS to a vertical one. This allows for a reduction in the overall device size and on-resistance, which alleviates the trade-off between breakdown voltage and on-resistance, but it still cannot further improve this trade-off. Furthermore, VDMOS devices are all back-side led-out, making them incompatible with CMOS processes, and therefore rarely used in BCD development. Summary of the Invention

[0003] Based on this, a trench-type DMOS device compatible with CMOS technology and its fabrication method are provided.

[0004] In a first aspect, a trench-type DMOS device is provided, comprising: a drift region of a first conductivity type and a main trench disposed within the drift region; a drain region of the first conductivity type and a source region of the first conductivity type, disposed on the upper surface of the drift region and on different sides of the main trench; a base region of a second conductivity type, disposed within the drift region and contacting and surrounding the source region; and a trench extension gate, including a gate insulating layer covering the bottom wall and sidewalls of the main trench, an extension gate layer covering the surface of the gate insulating layer, and an insulating dielectric region covering the extension gate layer and filling the main trench; the extension gate layer includes a first extension of the second conductivity type. The system comprises a gate region, a second extended gate region of a first conductivity type, and a third extended gate region of a first conductivity type; the second extended gate region is disposed on the surface of the gate insulating layer near the sidewall of the main trench close to the source region, the third extended gate region is disposed on the surface of the gate insulating layer near the sidewall of the main trench close to the drain region, the first extended gate region is disposed on the surface of the gate insulating layer on the bottom wall of the main trench and extends along the surface of the gate insulating layer adjacent to the second extended gate region and the third extended gate region, and the interface between the first extended gate region and the second extended gate region is located at the same horizontal plane as or below the lower boundary of the base region.

[0005] In one embodiment, the trench-type DMOS device further includes a secondary trench located within the drift region and connected to the main trench. The secondary trench also contains a second extended gate region and a fourth extended gate region of a second conductivity type connected to the second extended gate region.

[0006] In one embodiment, the trench-type DMOS device further includes: a drain electrode electrically connected to both the drain region and the third extended gate region; a source electrode electrically connected to the source region; and a gate electrode electrically connected to both the second extended gate region and the fourth extended gate region.

[0007] In one embodiment, the trench DMOS device further includes: a base region of a second conductivity type, located on the upper surface of the base region of the second conductivity type, the base region being electrically connected to the source electrode, the base region and the source region being connected along a first direction on the upper surface of the drift region, the first direction being different from the second direction, the second direction being the line direction connecting the source region and the drain region.

[0008] In one embodiment, the width of the primary trench along a second direction on the upper surface of the drift region ranges from 4,000 to 10,000 angstroms, and / or the width of the secondary trench along a first direction on the upper surface of the drift region ranges from 3,000 to 5,000 angstroms, and / or the depth of the primary trench along a third direction ranges from 16,000 to 40,000 angstroms, the third direction being a direction perpendicular to the upper surface of the drift region.

[0009] In one embodiment, the length of the second extended gate region along a third direction ranges from 3,000 to 5,000 angstroms, and / or the length of the third extended gate region along the third direction ranges from 2,000 to 6,000 angstroms, the third direction being a direction perpendicular to the upper surface of the drift region.

[0010] In one embodiment, the thickness of the extended gate layer ranges from 1000 to 3000 angstroms.

[0011] In one embodiment, the first extended gate region is polysilicon of the second conductivity type, and the second and third extended gate regions are both polysilicon of the first conductivity type.

[0012] A second aspect provides a method for fabricating a trench-type DMOS device, comprising: providing a drift region having a main trench, the drift region being of a first conductivity type; forming a gate insulating layer on the bottom wall and sidewalls of the main trench; forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer; forming an insulating dielectric region on the surface of the first extended gate region and filling the main trench, wherein the upper surface of the gate insulating layer and the upper surface of the first extended gate region between the insulating dielectric region and the sidewalls of the main trench are both exposed through the trench opening of the main trench, and the first extended gate region is exposed on both sides of the insulating dielectric region; forming a second extended gate region on the upper surface of the first extended gate region. Two extended gate regions and a third extended gate region are located on different sides of the insulating dielectric region and are both in contact with the insulating dielectric region. Both the second and third extended gate regions are of the first conductivity type. A base region of the second conductivity type is formed on the upper surface of the drift region near the second extended gate region. The lower boundary of the base region is at the same horizontal plane as the lower boundary of the second extended gate region, or the lower boundary of the base region is higher than the lower boundary of the second extended gate region. A source region of the first conductivity type is formed on the upper surface of the base region. A drain region of the first conductivity type is formed on the upper surface of the drift region near the third extended gate region.

[0013] In one embodiment, forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer includes: forming polysilicon of a second conductivity type as the first extended gate region on the surface of the gate insulating layer.

[0014] In one embodiment, a second extended gate region and a third extended gate region are formed on the upper surface of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating medium region and are both in contact with the insulating medium region. The second extended gate region and the third extended gate region are both of the first conductivity type. The method includes: injecting ions of the first conductivity type into the upper surface of the first extended gate region exposed at the opening of the main trench, forming the second extended gate region on one side of the insulating medium region, and forming the third extended gate region on the other side of the insulating medium region.

[0015] In one embodiment, the second and third extended gate regions extend into the main trench at depths ranging from 3,000 to 5,000 angstroms.

[0016] In one embodiment, the drift region having a main trench, the drift region being of a first conductivity type, includes: the drift region further having a secondary trench communicating with the main trench.

[0017] The method of forming a gate insulating layer on the bottom wall and side wall of the main trench; forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer includes: the gate insulating layer is also formed on the bottom wall and side wall of the secondary trench; while forming the first extended gate region on the surface of the gate insulating layer of the main trench, the first extended gate region also covers the gate insulating layer in the secondary trench and fills the secondary trench.

[0018] In one embodiment, a second extended gate region and a third extended gate region are formed on the upper surface of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating medium region and are both in contact with the insulating medium region. The second extended gate region and the third extended gate region are both of the first conductivity type. The embodiment also includes: simultaneously implanting ions of the first conductivity type into a portion of the upper surface of the first extended gate region in the secondary trench to form a fourth extended gate region, and the fourth extended gate region is connected to the second extended gate region.

[0019] The aforementioned trench-type DMOS device includes an extended gate layer disposed on the inner surface of the gate insulating layer. The extended gate layer includes a first extended gate region of a second conductivity type, a second extended gate region of a first conductivity type, and a third extended gate region. This can significantly improve the contradictory relationship between the breakdown voltage and specific on-resistance of the trench-type DMOS device, so that the trench-type DMOS device not only has high breakdown voltage but also low specific on-resistance.

[0020] The trench-type DMOS device described above has a vertical withstand voltage structure, which reduces the device area and thus reduces the on-resistance. At the same time, both the source and drain regions can be brought out from the front, making it compatible with CMOS. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1A This is a schematic cross-sectional view of a trench-type VDMOS device provided in one embodiment;

[0023] Figure 1B This is a top view of a trench-type VDMOS device provided in one embodiment;

[0024] Figure 2A This is a schematic cross-sectional view of a trench-type VDMOS device provided in another embodiment;

[0025] Figure 2B This is a top view of a trench-type VDMOS device provided in another embodiment;

[0026] Figure 3 This is a schematic flowchart of a method for fabricating a trench-type VDMOS device provided in one embodiment;

[0027] Figure 4A This is a schematic cross-sectional view of the structure obtained by forming a gate insulating layer on the bottom wall and side wall of the main trench in the fabrication method of the trench-type VDMOS device provided in one embodiment.

[0028] Figure 4B This is a top view of the structure obtained by forming a gate insulating layer on the bottom wall and side wall of the main trench in the fabrication method of the trench-type VDMOS device provided in one embodiment.

[0029] Figure 5A This is a schematic cross-sectional view of the structure obtained by forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer in the fabrication method of a trench-type VDMOS device provided in one embodiment.

[0030] Figure 5B This is a top view of the structure obtained by forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer in the fabrication method of a trench-type VDMOS device provided in one embodiment.

[0031] Figure 6This is a schematic cross-sectional view of the structure obtained by forming an insulating dielectric region on the surface of the first extended gate region and filling the main trench in the fabrication method of the trench-type VDMOS device provided in one embodiment.

[0032] Figure 7A This is a cross-sectional schematic diagram of the structure obtained by forming a second extended gate region and a third extended gate region on the upper surface layer of the first extended gate region in the fabrication method of the trench VDMOS device provided in one embodiment.

[0033] Figure 7B This is a top view of the structure obtained by forming a second extended gate region and a third extended gate region on the upper surface of a first extended gate region in the fabrication method of a trench-type VDMOS device provided in one embodiment.

[0034] Figure 8 This is a schematic cross-sectional view of the structure obtained by forming a base region of a second conductivity type on the upper surface of the drift region near the second extended gate region in the fabrication method of the trench VDMOS device provided in one embodiment.

[0035] Figure 9 This is a schematic flowchart of a method for fabricating a trench-type VDMOS device provided in another embodiment. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0042] Generally, the drain region of VDMOS (Vertical Double Diffusion Metal Oxide Semiconductor) is led out from the back side, which is incompatible with CMOS processes and therefore rarely used in BCD development. In view of this, this application provides a trench-type DMOS device. This trench-type DMOS device can achieve extremely low Rdson (on-resistance) by utilizing the vertical drift region, and because its drain region is led out from the front side, it is compatible with CMOS processes, further reducing the circuit area.

[0043] Please see Figures 1A to 1B , Figure 1A This illustration shows a cross-sectional structural diagram of a trench-type DMOS device according to an embodiment of this application. Figure 1B This diagram shows a top view of a trench-type DMOS device according to an embodiment of this application. Figures 1A to 1B As shown, the trench-type DMOS device includes a drift region 110 of a first conductivity type, a drain region 120 of a first conductivity type, a source region 130 of a first conductivity type, a base region 140 of a second conductivity type, and a trench extended gate 150. The trench extended gate 150 includes a gate insulating layer 152, an extended gate layer 154, and an insulating dielectric region 156. The extended gate layer 154 includes a first extended gate region 154a of a second conductivity type, a second extended gate region 154b of a first conductivity type, and a third extended gate region 154c of a first conductivity type.

[0044] For further reference Figure 1BA main trench 158 is formed in the drift region. A drain region 120 and a source region 130 are disposed on the upper surface of the drift region 110, and the drain region 120 and the source region 130 are disposed on different sides of the main trench 158. A base region 140 is disposed within the drift region 110, contacting and surrounding the source region 130. A gate insulating layer 152 covers the bottom wall and sidewalls of the main trench 158, an extended gate layer 154 covers the surface of the gate insulating layer, and an insulating dielectric region 156 covers the extended gate layer 154 and fills the main trench 158. Specifically, the second extended gate region 154b is disposed on the surface of the gate insulating layer of the main trench 158 near the sidewall of the source region 130, and the third extended gate region 154c is disposed on the surface of the gate insulating layer of the main trench 158 near the sidewall of the drain region 120. The first extended gate region 154a is disposed on the surface of the gate insulating layer of the bottom wall of the main trench 158 and extends along the surface of the gate insulating layer 152 to the second extended gate region 154b and the third extended gate region 154c. The interface between the first extended gate region 154a and the second extended gate region 154b is located on the same horizontal plane as the lower boundary of the base region 140, or the interface between the first extended gate region 154a and the second extended gate region 154b is lower than the lower boundary of the base region 140, so that the base region 140 and the second extended gate region 154b at least partially overlap in the depth direction (third direction) of the main trench 158. The second extended gate region 154b causes the base region 140 to form a channel inverse. It should be noted that the second extended gate region 154b of the first conductivity type, the first extended gate region 154a of the second conductivity type, and the third extended gate region 154c of the first conductivity type constitute a JFP (Junction Field Plate) structure. The second extended gate region 154b of the first conductivity type also serves as the gate structure of a trench-type DMOS device. It is understood that the first conductivity type and the second conductivity type are different conductivity types. Optionally, the first conductivity type is N-type and the second conductivity type is P-type. Optionally, the first conductivity type is P-type and the second conductivity type is N-type.

[0045] In one embodiment, gate insulating layer 152 is a gate oxide layer. Gate insulating layer 152 may also comprise conventional dielectric materials such as oxides, nitrides, and oxides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or gate insulating layer 152 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment, the thickness of gate insulating layer 152 ranges from 200 to 600 angstroms. Optionally, the thickness of gate insulating layer 152 is 400 angstroms.

[0046] In one embodiment, the insulating dielectric layer 156 may be made of silicon dioxide.

[0047] In one embodiment, the width of the main trench 158 along the second direction x of the upper surface of the drift region 110 ranges from 4000 to 10000 angstroms. Optionally, the width of the main trench 158 along the second direction x of the upper surface of the drift region 110 is 6000 angstroms. Here, the second direction x is the direction of the line connecting the source region 130 and the drain region 120, and the second direction x is parallel to the upper surface of the drift region 110. In one embodiment, the depth of the main trench 158 along the third direction ranges from 16000 to 40000 angstroms. Optionally, the depth of the main trench 158 along the third direction is 20000 angstroms. Here, the third direction is a direction perpendicular to the upper surface of the drift region 110. In one embodiment, the thickness of the extended gate layer 154 ranges from 1000 to 3000 angstroms. Optionally, the thickness of the extended gate layer 154 is 2000 angstroms. In one embodiment, the length of the second extended gate region 154b along the third direction ranges from 3000 to 5000 angstroms. Optionally, the length of the second extended gate region 154b along the third direction is 4000 angstroms. In one embodiment, the length of the third extended gate region 154c along the third direction ranges from 2000 to 6000 angstroms. Optionally, the length of the third extended gate region 154c along the third direction is 4000 angstroms. In one embodiment, the lengths of the second extended gate region 154b and the third extended gate region 154c along the third direction are equal. In one embodiment, the first extended gate region 154a can be polysilicon of a second conductivity type, and the second extended gate region 154b and the third extended gate region 154c can be polysilicon of a first conductivity type.

[0048] In one embodiment, the first direction along the upper surface of the drift region 110 refers to the first direction within the horizontal plane where the upper surface of the drift region 110 is located, and the second direction x along the upper surface of the drift region 110 refers to the second direction x within the horizontal plane where the upper surface of the drift region 110 is located. Within the horizontal plane where the upper surface of the drift region 110 is located, the second direction is the direction of the line connecting the source region and the drain region. The first direction and the second direction are different directions.

[0049] The trench-type DMOS device provided in the above embodiments features a JFP structure. When the trench-type DMOS device is forward-biased, a charge accumulation layer is formed in the drift region, thereby reducing the on-resistance. Since the on-resistance is determined by the charge accumulation in the drift region, and the intensity of the charge accumulation depends on the magnitude of the voltage applied to the gate and the thickness of the extended gate layer, but is independent of the doping concentration in the drift region, this breaks the conventional law that the on-resistance of power MOSFETs depends on the doping concentration in the drift region. Simultaneously, because most of the current flows through the charge accumulation layer, and only a small portion flows through the drift region resistance, the temperature distribution of the device is more uniform, and the device operation is more stable. Furthermore, the JFP structure can help regulate the electric field distribution in the drift region when the trench-type DMOS device is in the off state, thereby contributing to improving the breakdown voltage of the trench-type DMOS device. This significantly improves the contradictory relationship between the breakdown voltage and specific on-resistance of the trench-type DMOS device.

[0050] The trench-type DMOS device provided in the above embodiments has a vertical withstand voltage structure, which reduces the device area and thus reduces the on-resistance of the device. At the same time, the drain and source regions of the trench-type DMOS device are both located on the same surface of the device, and both the source and drain regions of the trench-type DMOS device can be led out from the front, making it compatible with CMOS.

[0051] Please see Figure 1B This diagram illustrates a top view of a trench-type DMOS device according to an embodiment of this application. Figure 1B As shown, the trench-type DMOS device may further include a secondary trench 160. Specifically, the secondary trench 160 is located within the drift region and communicates with the main trench 158. The secondary trench 160 also contains a second extended gate region 154b and a fourth extended gate region 154d of a second conductivity type connected to the second extended gate region 154b. The second extended gate region 154b in the secondary trench 160 is connected to the second extended gate region 154b in the main trench 158. The secondary trench 160 in the drift region can be used to accommodate a portion of the junction field plate. It should be noted that the second extended gate region 154b, the fourth extended gate region 154d, the first extended gate region 154a, and the third extended gate region 154c constitute a JFP structure.

[0052] In one embodiment, the length of the second extended gate region 154b provided in the secondary trench 160 along the third direction is greater than the length of the fourth extended gate region 154d along the third direction. In one embodiment, the secondary trench 160 also has a first extended gate region 154a, and the first extended gate region 154a contacts the second extended gate region 154b and the fourth extended gate region 154d provided in the secondary trench 160 and is connected to the first extended gate region 160 provided in the main trench 158. In one embodiment, the doping concentration of the fourth extended gate region 154d is greater than that of the first extended gate region 154a. In one embodiment, the width of the secondary trench 160 along the first direction y on the upper surface of the drift region ranges from 3000 to 5000 angstroms. Optionally, the width of the secondary trench 160 along the first direction y on the upper surface of the drift region is 4000 angstroms.

[0053] In one embodiment, on the upper surface layer of the drift region 110, the main trench 158 and the secondary trench 160 form a "day" - shaped structure or a comb - shaped structure. The "day" - shaped structure includes a rectangular frame part and a straight part. The main trench 158 serves as the straight part of the "day" - shaped structure, and the secondary trench 160 serves as the rectangular frame part of the "day" - shaped structure. The comb - shaped structure includes comb teeth parts and a comb handle part connecting the comb teeth parts. The main trench 158 serves as the comb teeth part of the comb - shaped structure, and the secondary trench 160 serves as the comb handle part of the comb - shaped structure.

[0054] Please refer to Figures 2A to 2B , the trench - type DMOS device may further include a drain electrode D, a source electrode S, and a gate electrode G. Among them, the drain electrode D is electrically connected to both the drain region 120 and the third extended gate region 154c, the source electrode S is electrically connected to the source region 130, and the gate electrode G is electrically connected to both the second extended gate region 154b and the fourth extended gate region 154d. It should be noted that Figure 2A the gate electrode G shown in Figure 2BThe method shown is as follows. In one embodiment, the gate electrode G is in contact with both the second extended gate region 154b and the fourth extended gate region 154d disposed in the secondary trench 160, so that the gate electrode G is electrically connected to both the second extended gate region 154b and the fourth extended gate region 154d. Generally, in order to improve utilization, the size of the second extended gate region 154b in the second direction x in the main trench 158 is small. When the gate is led out by drilling (opening a gate via on the dielectric layer covering the second extended gate region 154b), since the drilling has size requirements, the contradiction between drilling and utilization can be effectively solved by opening the secondary trench 160 and providing the second extended gate region 154b and the fourth extended gate region 154d on the secondary trench 160. In one embodiment, the second extended gate region 154b is N-type and the fourth extended gate region 154d is P-type. The trench-type DMOS device provided in this embodiment ensures that the NDMOS is an N-type gate region, while the potential of the first extended gate region 154a is the same as the gate potential, thus guaranteeing the effectiveness of the JFP structure. In one embodiment, the gate electrode is connected to 0 potential.

[0055] Please continue reading. Figure 2A and Figure 2B The trench-type DMOS device may also include a base lead-out region 202 of a second conductivity type. It should be noted that... Figure 2A The location of the base area lead-out area 202 is for indication only; the actual location of the base area lead-out area 202 is as follows: Figure 2B The location of the base region lead-out region 202 is shown. The base region lead-out region 202 is located on the upper surface of the base region 140 and is electrically connected to the source electrode S. The base region lead-out region 202 and the source region 130 are connected along a first direction y on the upper surface of the drift region 110. It is understood that the first direction y is different from the second direction x. In one embodiment, the doping concentration of the base region lead-out region 202 is greater than the doping concentration of the base region 140. This embodiment achieves the resurf (reduction of surface electric field) function of the JFP structure by shorting the source region 130 and the base region lead-out region 202 together.

[0056] Please refer to Figure 3 It shows a schematic flowchart of a method for fabricating a trench-type DMOS device according to an embodiment of this application, such as... Figure 3 As shown, the fabrication method of a trench-type DMOS device may include steps S302 to S312.

[0057] S302 provides a drift region with a main trench, the drift region being of the first conductivity type.

[0058] Figure 4A This is a schematic diagram of the cross-sectional structure of the drift zone with the main groove. Figure 4BThis is a top view of a drift region with a main trench. In one embodiment, the drift region 110 is disposed on the upper surface of a substrate of a second conductivity type. The width of the main trench 158 along the second direction can range from 4,000 to 10,000 angstroms, and the depth of the main trench 158 along the third direction can range from 16,000 to 40,000 angstroms. The bottom wall of the main trench 158 is arc-shaped. In one embodiment, the drift region 110 has at least one main trench 158.

[0059] In one embodiment, prior to providing the drift region with the main trench, the method includes etching to form the main trench on the drift region. In another embodiment, prior to etching to form the main trench on the drift region, the method includes providing a substrate of a second conductivity type, and forming the drift region on the upper surface of the substrate. The substrate includes a semiconductor substrate, and the material may be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. The step of etching to form the main trench on the drift region may include: forming a mask layer on the surface of the drift region, patterning the mask layer to obtain a patterned mask layer, the patterned mask layer having openings that expose the drift region and define the shape and position of the main trench, and etching the drift region based on the patterned mask layer to form the main trench within the drift region. In one embodiment, the mask layer is a hard mask layer. In another embodiment, the hard mask layer is an oxide / SiN / oxide film structure.

[0060] S304, a grid insulation layer is formed on the bottom and side walls of the main trench.

[0061] Please continue to refer to this. Figures 4A to 4B A gate insulating layer 152 is formed on the bottom and sidewalls of the main trench 158. In one embodiment, the thickness of the gate insulating layer 152 can range from 200 to 600 angstroms. Optionally, the thickness of the gate insulating layer 152 can be 400 angstroms. In one embodiment, the gate insulating layer 152 can be a gate oxide layer. The gate insulating layer 152 may also comprise conventional dielectric materials such as oxides, nitrides, and oxides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate insulating layer 152 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0062] S306, a first extended gate region of a second conductivity type is formed on the surface of the gate insulating layer.

[0063] Please refer to Figures 5A to 5B A first extended gate region 154a is formed on the surface of the gate insulating layer 152. It should be noted that the second conductivity type is a different conductivity type from the first conductivity type. In one embodiment, the thickness of the first extended gate region 154a can range from 1000 to 3000 angstroms. Optionally, the thickness of the first extended gate region 154a can be 2000 angstroms.

[0064] In one embodiment, the step of forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer may include: forming polysilicon of a second conductivity type as the first extended gate region on the surface of the gate insulating layer. It should be noted that after forming the first extended gate region of the second conductivity type on the surface of the gate insulating layer, a recess is left in the middle of the main trench. In one embodiment, forming the first extended gate region of the second conductivity type on the surface of the gate insulating layer includes: depositing a layer of polysilicon of the second conductivity type using a furnace tube to form the first extended gate region of the second conductivity type.

[0065] S308, an insulating dielectric region is formed on the surface of the first extended gate region and the main trench is filled. The upper surface of the gate insulation layer between the insulating dielectric region and the sidewall of the main trench and the upper surface of the first extended gate region are exposed through the slot of the main trench. The first extended gate region is exposed on both sides of the insulating dielectric region.

[0066] Please refer to Figure 6 An insulating dielectric region 156 is formed on the surface of the first extended gate region 154a and fills the main trench. The upper surface of the gate insulating layer 152 between the insulating dielectric region 156 and the sidewall of the main trench, and the upper surface of the first extended gate region 154a are both exposed through the opening of the main trench. The first extended gate region 154a is exposed on both sides of the insulating dielectric region 156. In one embodiment, the material of the insulating dielectric region 156 may include silicon dioxide.

[0067] In one embodiment, the step of forming an insulating dielectric region on the surface of the first extended gate region includes filling the depression of the main trench using an HDP (high-density plasma) process. It is understood that the HDP process has both deposition and etching capabilities, thus providing excellent trench filling performance.

[0068] In one embodiment, after the step of forming an insulating dielectric region on the surface of the first extended region and filling the main trench, the method further includes: etching the insulating dielectric region to the surface of the drift region. After the step of etching the insulating dielectric region to the surface of the drift region, the method further includes: etching the first extended gate region to the surface of the drift region, such that the upper surface of the gate insulation layer between the insulating dielectric region and the sidewall of the main trench and the upper surface of the first extended gate region are both exposed through the opening of the main trench, and the first extended gate region is exposed on both sides of the insulating dielectric region.

[0069] S310, a second extended gate region and a third extended gate region are formed on the upper surface of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating medium region and are in contact with the insulating medium region. Both the second extended gate region and the third extended gate region are of the first conductivity type.

[0070] Please refer to Figures 7A to 7B The formed second extended gate region 154b and third extended gate region 154c are located on different sides of the insulating dielectric region 156, and both are in contact with the insulating dielectric region 156. It should be noted that both the second extended gate region 154b and the third extended gate region 154c are of the first conductivity type. In one embodiment, the second extended gate region 154b and the third extended gate region 154c penetrate into the main trench to the same depth. In one embodiment, the depth of both the second extended gate region 154b and the third extended gate region 154c penetrating into the main trench ranges from 3000 to 5000 angstroms. Optionally, the depth of both the second extended gate region 154b and the third extended gate region 154c penetrating into the main trench is 4000 angstroms.

[0071] In one embodiment, the step of forming a second extended gate region and a third extended gate region on the upper surface of the first extended gate region may include: injecting ions of a first conductivity type into the upper surface of the first extended gate region exposed at the opening of the main trench, forming a second extended gate region on one side of the insulating dielectric region, and forming a third extended gate region on the other side of the insulating dielectric region.

[0072] S312, a base region of the second conductivity type is formed on the upper surface of the drift region near the second extended gate region, and the lower boundary of the base region is located on the same horizontal plane as the lower boundary of the second extended gate region, or the lower boundary of the base region is higher than the lower boundary of the second extended gate region.

[0073] Please refer to Figure 8 A base region 140 is formed on the upper surface of the drift region 110 near the second extended gate region 154b. It should be noted that the lower boundary of the base region 140 is on the same horizontal plane as the lower boundary of the second extended gate region 154b, or the lower boundary of the base region 140 is higher than the lower boundary of the second extended gate region 154b.

[0074] In one embodiment, the step of forming a base region of a second conductivity type on the upper surface of the drift region near the second extended gate region includes: forming a base region of a second conductivity type on the upper surface of the drift region near the second extended gate region by photolithography and ion implantation of ions of the second conductivity type.

[0075] S314 forms a source region of the first conductivity type on the upper surface of the base region.

[0076] Please refer to Figure 1A and Figure 1BThe active polar region 130 is formed on the upper surface of the base region 140.

[0077] In one embodiment, the step of forming a source region of a first conductivity type on the upper surface layer of the base region may include: forming the source region by photolithography and ion implantation of ions of the first conductivity type.

[0078] S316, a drain region of the first conductivity type is formed on the upper surface layer of the drift region near the third extended gate region.

[0079] Please continue to refer to this. Figure 1A and Figure 1B A drain region 120 is formed on the upper surface of the drift region 110 near the third extended gate region 154c.

[0080] In one embodiment, the step of forming a drain region of a first conductivity type on the upper surface layer of the drift region near the third extended gate region may include: forming the drain region by photolithography and ion implantation of ions of the first conductivity type. In one embodiment, the source region and the drain region are formed simultaneously.

[0081] In one embodiment, the fabrication method of a trench-type DMOS device may further include forming a base region of a second conductivity type on the upper surface layer of the base region, wherein the base region and the source region are connected along a first direction on the upper surface of the drift region. In one embodiment, the step of forming a base region of a second conductivity type on the upper surface layer of the drift region includes: forming the base region by photolithography and ion implantation of ions of the second conductivity type.

[0082] In one embodiment, the method for fabricating a trench-type DMOS device may further include forming a source electrode, wherein the source electrode is electrically connected to both the source region and the base region. In another embodiment, the method for fabricating a trench-type DMOS device may further include forming a drain electrode, wherein the drain electrode is electrically connected to both the drain region and the third extended gate region.

[0083] The trench-type VDMOS device fabrication method provided in this application has a relatively simple layout and fabrication method, which reduces production costs. Furthermore, the trench-type DMOS device fabricated by the trench-type DMOS device fabrication method in this application can achieve device performance with extremely low Rdson (on-resistance) by taking advantage of the vertical drift region. Also, because its drain region is led out from the front, it can be compatible with CMOS process technology, further reducing the circuit area.

[0084] Please refer to Figure 9 It illustrates a method for fabricating a trench-type VDMOS device according to an embodiment of this application, such as... Figure 9 As shown, the fabrication method of the trench VDMOS device may include steps S902 to S912.

[0085] S902 provides a drift zone having a main trench and a secondary trench connected to the main trench.

[0086] Please continue to refer to this. Figure 4B The drift region 110 has a main groove 158 and a secondary groove 160 connected to the main groove 158. In one embodiment, the width of the main groove 158 along the second direction is greater than the width of the secondary groove 160 along the first direction.

[0087] S904, a grid insulation layer is formed on the bottom and side walls of the main trench and the bottom and side walls of the secondary trench.

[0088] Please continue to refer to this. Figure 4B A gate insulating layer 152 is formed on the bottom and sidewalls of the main trench 158 and the bottom and sidewalls of the secondary trench 160. A detailed description of the formed gate insulating layer 152 is provided in the embodiments above and will not be repeated here. In one embodiment, the gate insulating layer is formed simultaneously on the bottom and sidewalls of both the main trench and the secondary trench.

[0089] S906, a first extended gate region of a second conductivity type is formed on the surface of the gate insulating layer. The first extended gate region covers the gate insulating layer in the main trench and also covers the gate insulating layer in the secondary trench and fills the secondary trench.

[0090] Please refer to Figure 5B The surface of the gate insulating layer 152 is formed with a first extended gate region 154a of the second conductivity type. It should be noted that the first extended gate region 154a covers the gate insulating layer 152 in the main trench, and the main trench is not filled by the first extended gate region 154a. A groove is left in the middle of the main trench. At the same time, the first extended gate region 154a covers the gate insulating layer 152 in the secondary trench and fills the secondary trench.

[0091] S908, an insulating medium region is formed on the surface of the first extended gate region and the main trench is filled. The upper surface of the gate insulation layer between the insulating medium region and the sidewall of the main trench and the upper surface of the first extended gate region are exposed through the slot of the main trench. The first extended gate region is exposed on both sides of the insulating medium region.

[0092] Please refer to Figure 6 An insulating dielectric region 156 is formed on the surface of the first extended gate region 154a and fills the main trench. It should be noted that the upper surface of the gate insulating layer 152 between the insulating dielectric region 156 and the sidewall of the main trench, and the upper surface of the first extended gate region 154a, are both exposed through the opening of the main trench, so that the first extended gate region 154a is exposed on both sides of the insulating dielectric region 156. The gate insulating layer 152 fills the depression left in the middle of the main trench.

[0093] S910, a second extended gate region and a third extended gate region are formed on the upper surface of the first extended gate region, and first conductive ions are implanted into the upper surface of a portion of the first extended gate region in the secondary trench to form a fourth extended gate region, and the fourth extended gate region is connected to the second extended gate region.

[0094] Please refer to Figure 7B The upper surface layer of the first extended gate region 154a is formed with a second extended gate region 154b, a third extended gate region 154c and a fourth extended gate region 154d.

[0095] In one embodiment, while forming a second and third extended gate region on the upper surface of a first extended gate region, first conductive ions are implanted into a portion of the upper surface of the first extended gate region in a secondary trench to form a fourth extended gate region. In another embodiment, first conductive ions are implanted into the upper surface of the first extended gate region to form the second, third, and fourth extended gate regions.

[0096] S912, a base region of the second conductivity type is formed on the upper surface layer of the drift region near the second extended gate region.

[0097] S914 forms a source region of the first conductivity type on the upper surface of the base region.

[0098] S916, a drain region of the first conductivity type is formed on the upper surface layer of the drift region near the third extended gate region.

[0099] For a detailed description of steps S912 to S916, please refer to the above embodiments, and they will not be repeated here.

[0100] In one embodiment, the step of implanting ions of a first conductivity type into the upper surface of a portion of the first extended gate region in the secondary trench to form a fourth extended gate region may further include the step of forming a gate electrode, the gate electrode being connected to the second extended gate region and the fourth extended gate region, respectively.

[0101] It should be understood that, although Figure 3 and Figure 9 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 and Figure 9 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0102] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A trench-type DMOS device, characterized in that, include: A drift region of the first conductivity type and a main trench disposed within the drift region; The drain region and the source region of the first conductivity type are disposed on the upper surface of the drift region and on different sides of the main trench. A base region of the second conductivity type is disposed within the drift region and contacts and surrounds the source region; A trench extension gate includes a gate insulating layer covering the bottom and sidewalls of a main trench, an extension gate layer covering the surface of the gate insulating layer, and an insulating dielectric region covering the extension gate layer and filling the main trench. The extension gate layer includes a first extension gate region of a second conductivity type, a second extension gate region of a first conductivity type, and a third extension gate region of a first conductivity type. The second extension gate region is disposed on the surface of the gate insulating layer near the sidewall of the main trench close to the source region. The third extension gate region is disposed on the surface of the gate insulating layer near the sidewall of the main trench close to the drain region. The first extension gate region is disposed on the surface of the gate insulating layer on the bottom wall of the main trench and extends along the surface of the gate insulating layer adjacent to the second and third extension gate regions. The interface between the first and second extension gate regions is at the same horizontal plane as or below the lower boundary of the base region.

2. The trench-type DMOS device according to claim 1, characterized in that, It also includes a secondary trench, which is located within the drift region and communicates with the main trench. The secondary trench also has a second extended gate region and a fourth extended gate region of the second conductivity type connected to the second extended gate region.

3. The trench-type DMOS device according to claim 2, characterized in that, Also includes: A drain electrode, which is electrically connected to both the drain region and the third extended gate region; Source electrode, which is electrically connected to the source region; The gate electrode is electrically connected to both the second extended gate region and the fourth extended gate region.

4. The trench-type DMOS device according to claim 3, characterized in that, Also includes: The base region of the second conductivity type is located on the upper surface of the base region of the second conductivity type. The base region is electrically connected to the source electrode. The base region and the source electrode are connected along a first direction on the upper surface of the drift region. The first direction is a first direction within the horizontal plane where the upper surface of the drift region is located. The second direction is a second direction within the horizontal plane where the upper surface of the drift region is located. The first direction and the second direction are different directions. The second direction is the line direction connecting the source electrode region and the drain electrode region.

5. The trench-type DMOS device according to claim 2, characterized in that, The width of the main trench along the second direction of the upper surface of the drift region ranges from 4000 to 10000 angstroms, and / or, The width of the secondary trench along the upper surface of the drift region in a first direction ranges from 3000 to 5000 angstroms, and / or, The depth of the main trench along a third direction ranges from 16,000 to 40,000 angstroms, and the third direction is the direction perpendicular to the upper surface of the drift region.

6. The trench-type DMOS device according to claim 1, characterized in that, The second extended gate region has a length ranging from 3000 to 5000 angstroms along a third direction, and / or, The length of the third extended gate region along the third direction ranges from 2000 to 6000 angstroms, and the third direction is the direction perpendicular to the upper surface of the drift region.

7. The trench-type DMOS device according to claim 1, characterized in that, The thickness of the extended gate layer ranges from 1000 to 3000 angstroms.

8. The trench-type DMOS device according to claim 1, characterized in that, The first extended gate region is polysilicon of the second conductivity type, and the second and third extended gate regions are both polysilicon of the first conductivity type.

9. A method for fabricating a trench-type DMOS device, characterized in that, include: A drift region with a main groove is provided, wherein the drift region is of a first conductivity type; A grid insulation layer is formed on the bottom wall and side wall of the main trench; A first extended gate region of a second conductivity type is formed on the surface of the gate insulating layer; An insulating medium region is formed on the surface of the first extended gate region and the main trench is filled. The upper surface of the gate insulation layer and the upper surface of the first extended gate region, which are disposed between the insulating medium region and the sidewall of the main trench, are exposed through the slot of the main trench. The first extended gate region is exposed on both sides of the insulating medium region. A second extended gate region and a third extended gate region are formed on the upper surface of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating medium region and are in contact with the insulating medium region. The second extended gate region and the third extended gate region are both of the first conductivity type. A base region of a second conductivity type is formed on the upper surface of the drift region near the second extended gate region. The lower boundary of the base region is located on the same horizontal plane as the lower boundary of the second extended gate region, or the lower boundary of the base region is higher than the lower boundary of the second extended gate region. A source region of the first conductivity type is formed on the upper surface layer of the base region; A drain region of the first conductivity type is formed on the upper surface layer of the drift region near the third extended gate region.

10. The method for fabricating a trench-type DMOS device according to claim 9, characterized in that, The formation of a first extended gate region of a second conductivity type on the surface of the gate insulating layer includes: A second type of polysilicon of a second conductivity type is formed on the surface of the gate insulating layer as the first extended gate region.

11. The method for fabricating a trench-type DMOS device according to claim 9, characterized in that, A second extended gate region and a third extended gate region are formed on the upper surface layer of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating dielectric region and are both in contact with the insulating dielectric region. Both the second extended gate region and the third extended gate region are of the first conductivity type, including: Ions of a first conductivity type are injected into the upper surface layer of the first extended gate region exposed at the opening of the main trench, forming the second extended gate region on one side of the insulating dielectric region, and the third extended gate region on the other side of the insulating dielectric region.

12. The method for fabricating a trench-type DMOS device according to claim 9 or 11, characterized in that, The second and third extended gate regions extend into the main trench at depths ranging from 3,000 to 5,000 angstroms.

13. The method for fabricating a trench-type DMOS device according to claim 9 or 11, characterized in that, The drift region provided has a main trench, the drift region being of a first conductivity type, and includes: the drift region further having a secondary trench communicating with the main trench. The method of forming a gate insulating layer on the bottom wall and side wall of the main trench; forming a first extended gate region of a second conductivity type on the surface of the gate insulating layer includes: the gate insulating layer is also formed on the bottom wall and side wall of the secondary trench; while forming the first extended gate region on the surface of the gate insulating layer of the main trench, the first extended gate region also covers the gate insulating layer in the secondary trench and fills the secondary trench.

14. The method for fabricating a trench-type DMOS device according to claim 13, characterized in that, A second extended gate region and a third extended gate region are formed on the upper surface layer of the first extended gate region. The second extended gate region and the third extended gate region are located on different sides of the insulating dielectric region and are both in contact with the insulating dielectric region. Both the second extended gate region and the third extended gate region are of the first conductivity type, including: Simultaneously, ions of a first conductivity type are implanted into the upper surface layer of a portion of the first extended gate region in the secondary trench to form a fourth extended gate region, and the fourth extended gate region is connected to the second extended gate region.

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