An under-voltage lockout structure whose output result is not affected by the power-on speed of a power supply

Abstract

An under-voltage lockout structure whose output result is not affected by the power-on speed, which is composed of an error amplifier, a voltage dividing resistor circuit, an internal voltage stabilizing power supply structure output voltage node, a current sampling circuit, a current comparison circuit and a buffer circuit, can facilitate synchronization of the comparison process of the under-voltage lockout structure with the establishment process of the bandgap reference voltage and the internal voltage stabilizing power supply, thereby avoiding the problem that the traditional scheme is easily affected by the power-on speed and the accuracy of the output result, and the structure of the internal voltage stabilizing power supply is reused, and only a few necessary devices are added to solve the problem existing in the traditional structure.

Description

Technical Field

[0001] This invention relates to undervoltage lockout technology, and in particular to an undervoltage lockout structure whose output is not affected by the power-on speed. Background Technology

[0002] Undervoltage lockout (UVLO) is a chip circuit protection mechanism that prevents certain functional modules or devices from operating when the power supply voltage is undervoltage (e.g., during chip power-on). They only activate when the power supply voltage equals or exceeds a threshold. Furthermore, integrating UVLO circuits into chip circuits can also improve power supply reliability and safety. Figure 3 This is a schematic diagram of the original undervoltage lockout structure. Figure 4 yes Figure 3 A waveform diagram of the relevant nodes. (Reference) Figures 3 to 4 As shown, the traditional undervoltage lockout structure includes an error amplifier EA. The positive input terminal (+) of EA is connected to the internal bandgap reference voltage node Vbg, and the negative input terminal (-) of EA is connected to the voltage divider node Vdiv. The first path of Vdiv is connected to the power supply voltage terminal VDD through the second voltage divider resistor R2, and the second path is grounded through the first voltage divider resistor R1. Figure 4 Explanation of voltage changes at relevant nodes (VDD, Vdiv, Vbg): When the power-up speed of IN is faster than the self-establishment speed of the internal bandgap reference voltage Vbg, the voltage Vdiv at the voltage divider node of VDD is always greater than Vbg. Since Vdiv is the non-inverting input of the undervoltage lockout comparator, from the time VDD starts powering on until the bandgap reference voltage Vbg is established (Vbg changes from a rising line to a horizontal line), the output voltage of the comparator is always low and never experiences a high-to-low transition. Typically, the internal logic circuits of the chip need to use the high-level output of the undervoltage lockout structure for power-on reset when the power supply voltage is below the undervoltage lockout threshold. If the output state of the undervoltage lockout comparator remains low from the time VDD starts powering on until the bandgap reference voltage is established, it cannot reset the logic circuit, causing the logic circuit to output an incorrect logic state during operation, preventing the chip from functioning properly. Summary of the Invention

[0003] This invention addresses the defects or deficiencies in existing technologies by providing an undervoltage lockout structure whose output is unaffected by the power-on speed.

[0004] The technical solution of the present invention is as follows:

[0005] An undervoltage lockout structure whose output is unaffected by the power-on speed is characterized by comprising an error amplifier, wherein the negative input terminal of the error amplifier is connected to a voltage divider node, the positive input terminal of the error amplifier is connected to an internal bandgap reference voltage node of the chip, the first path of the voltage divider node is grounded through a first voltage divider resistor, and the second path is connected to the output voltage node of the internal voltage regulator structure of the chip through a second voltage divider resistor, the output terminal of the error amplifier is connected to a current sampling circuit and a buffer circuit respectively through a current comparison circuit, and the buffer circuit is connected to the undervoltage lockout output signal terminal.

[0006] The current comparison circuit includes a second PMOS transistor. The gate of the second PMOS transistor is connected to the output terminal of the error amplifier. The source of the second PMOS transistor is connected to the output voltage node of the internal voltage regulator structure of the chip. The drain of the second PMOS transistor is connected to the current comparison node. The current comparison node is grounded through a first current source in the first path and connected to the buffer circuit in the second path.

[0007] The buffer circuit includes a first inverter and a second inverter connected in series. The output terminal of the second inverter is connected to the undervoltage lockout output signal terminal. The first input terminal of the first inverter is connected to the power supply voltage terminal through a fourth current source, and the second input terminal is connected to the drain of a second NMOS transistor. The gate of the second NMOS transistor is connected to the current comparison node, and the source of the second NMOS transistor is grounded.

[0008] The current sampling circuit includes a third PMOS transistor and a second PMOS transistor with a common source and common gate configuration. The source of the third PMOS transistor is connected to the drain of a fourth PMOS transistor. The drain of the third PMOS transistor is first connected to the source of a first NMOS transistor and second connected to ground through a second current source. The source of the fourth PMOS transistor is connected to the power supply voltage terminal. The gate of the fourth PMOS transistor is first connected to the power supply voltage terminal through a third current source and second connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the bias voltage terminal.

[0009] Let the bandgap reference voltage be Vbg, the output voltage of the regulated power supply structure be Vreg, the first resistor be R1, and the second resistor be R2. Then Vreg = Vbg * (1 + R2 / R1).

[0010] The mirror ratio between the second PMOS transistor and the third PMOS transistor is 1:1.

[0011] Let the current from the second current source be I1, the current from the third current source be I2, and the current flowing out of the drain of the third PMOS transistor be Imp3. Then Imp3 = I1 - I2.

[0012] Let the current of the first current source be I0, and I0 = (1 / n)*(I1-I2), where n is an integer greater than 1.

[0013] Let the current flowing out of the drain of the second PMOS transistor be Imp2, then Imp2≥I0=(1 / n)*(I1-I2). As a result, the potential of the current comparison node is pulled up to turn on the second NMOS transistor, and the drain potential of the second NMOS transistor is pulled down, causing the inverter output, i.e. the UVLO signal, to reverse from a high level to a low level.

[0014] The technical effects of this invention are as follows: This invention provides an undervoltage lockout structure whose output result is not affected by the power-on speed. Through the combination of an error amplifier, a voltage divider resistor circuit, the output voltage node of the internal regulated power supply structure, a current sampling circuit, a current comparison circuit, and a buffer circuit, it is beneficial to synchronize the comparison process of the undervoltage lockout structure with the establishment process of the bandgap reference voltage and the internal regulated power supply. This avoids the problem that the accuracy of the output result is easily affected by the power-on speed of traditional solutions. Moreover, the structure reuses the structure of the internal regulated power supply. On this basis, only a few necessary components are added to solve the problems existing in the traditional structure. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit principle of an undervoltage lockout structure that implements the present invention, in which the output result is not affected by the power-on speed. Figure 1 The innovative part of this invention is shown within the dashed box.

[0016] Figure 2 yes Figure 1 A waveform diagram of several important nodes. Figure 2 The horizontal axis represents the power supply voltage VDD, and the vertical axis represents the node voltage V. The starting point of each waveform is 0V. Figure 2 This includes the output voltage Vreg of the regulated power supply structure, the bandgap reference voltage Vbg, the absolute value of the gate-source voltage |Vgsp2| of the second PMOS transistor Mp2, and the undervoltage lockout output voltage or undervoltage lockout output signal UVLO (Under Voltage Lock Out).

[0017] Figure 3 This is a schematic diagram of the original undervoltage lockout structure.

[0018] Figure 4 yes Figure 3 A waveform diagram of the relevant nodes. Figure 4 The horizontal axis represents time t, and the vertical axis represents voltage V. Figure 4 The relevant nodes include the following: power supply voltage node VDD, voltage divider node Vdiv, and internal bandgap reference voltage node Vbg. Figure 4In the middle, VDD powers on faster than Vbg, and the voltage at the voltage divider node, Vdiv, is always greater than Vbg.

[0019] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; EA - Error comparator; R1~R2 - First voltage divider resistor to second voltage divider resistor; Mn0~Mn1 - First NMOS transistor to second NMOS transistor; Mp2~Mp4 - Second PMOS transistor to fourth PMOS transistor; Ng1~Ng2 - First inverter to second inverter; I0~I3 - First current source to fourth current source; UVLO - Undervoltage lockout output voltage or undervoltage lockout output signal terminal; Vbg - Internal bandgap reference voltage node of the chip; Vreg - Output voltage node of the internal regulated power supply structure of the chip; |Vgsp2| - Absolute value of the gate-source voltage of the second PMOS transistor Mp2; Vb - Bias voltage terminal; Vdiv - Voltage divider node voltage or voltage divider node. Detailed Implementation

[0020] The following is in conjunction with the attached diagram ( Figures 1-2 The present invention will be described below.

[0021] Figure 1 This is a schematic diagram of the circuit principle of an undervoltage lockout structure that implements the present invention, in which the output result is not affected by the power-on speed. Figure 1 The innovative part of this invention is shown within the dashed box. Figure 2 yes Figure 1 Waveform diagrams for several key nodes. (Reference) Figures 1 to 2As shown, an undervoltage lockout structure whose output is unaffected by the power-on speed includes an error amplifier EA. The negative input (-) of the error amplifier EA is connected to a voltage divider node, and the positive input (+) of the error amplifier EA is connected to an internal bandgap reference voltage node Vbg. The voltage divider node has a first path grounded through a first voltage divider resistor R1, and a second path connected to the output voltage node Vreg of the internal regulated power supply structure through a second voltage divider resistor R2. The output of the error amplifier EA is connected to a current sampling circuit and a buffer circuit through a current comparator circuit. The buffer circuit is connected to the undervoltage lockout output signal terminal UVLO. The current comparator circuit includes a second PMOS transistor Mp2. The gate of the second PMOS transistor Mp2 is connected to the output of the error amplifier EA, the source of the second PMOS transistor Mp2 is connected to the output voltage node Vreg of the internal regulated power supply structure, and the drain of the second PMOS transistor Mp2 is connected to the current comparator node. The current comparator node has a first path grounded through a first current source I0, and a second path connected to the buffer circuit. The buffer circuit includes a first inverter Ng1 and a second inverter Ng2 connected in series. The output terminal of the second inverter Ng2 is connected to the undervoltage lockout output signal terminal UVLO. The input terminal of the first inverter Ng1 is connected to the power supply voltage terminal VDD through a fourth current source I3 in the first path and to the drain of the second NMOS transistor MN1 in the second path. The gate of the second NMOS transistor MN1 is connected to the current comparison node, and the source of the second NMOS transistor MN1 is grounded.

[0022] The current sampling circuit includes a common-source, common-gate third PMOS transistor Mp3 and a second PMOS transistor Mp2. The source of the third PMOS transistor Mp3 is connected to the drain of a fourth PMOS transistor Mp4. The drain of the third PMOS transistor Mp3 is first connected to the source of a first NMOS transistor MN0, and second connected to ground through a second current source I1. The source of the fourth PMOS transistor Mp4 is connected to the power supply voltage terminal VDD. The gate of the fourth PMOS transistor VDD is first connected to the power supply voltage terminal VDD through a third current source I2, and second connected to the drain of the first NMOS transistor MN0. The gate of the first NMOS transistor MN0 is connected to the bias voltage terminal Vb.

[0023] Let the bandgap reference voltage be Vbg, the output voltage of the regulated power supply structure be Vreg, the first resistor be R1, and the second resistor be R2. Then Vreg = Vbg * (1 + R2 / R1). The image ratio between the second PMOS transistor Mp2 and the third PMOS transistor Mp3 is 1:1. Let the second current source current be I1, the third current source current be I2, and the current flowing out of the drain of the third PMOS transistor Mp3 be Imp3. Then Imp3 = I1 - I2. Let the first current source current be I0, and I0 = (1 / n) * (I1 - I2), where n is an integer greater than 1. Let Imp2 be the current flowing out of the drain of the second PMOS transistor Mp2. Then Imp2 ≥ I0 = (1 / n) * (I1 - I2). As a result, the potential of the current comparison node is pulled up to turn on the second NMOS transistor MN1. The drain potential of the second NMOS transistor MN1 is pulled down, causing the inverter output, i.e., the UVLO signal, to be reversed from high level to low level.

[0024] The circuit of the present invention is as follows Figure 1 As shown, Figure 2 The waveforms at key nodes during the operation of the circuit of this invention are shown. This circuit reuses the internal voltage regulator structure of the chip. As can be seen from the circuit structure, the relationship between the output voltage Vreg of the voltage regulator structure and the bandgap reference voltage Vbg is: Vreg = Vbg * (1 + R2 / R1). When the VDD terminal is powered on, Vbg begins to build up. Before Vreg reaches the preset voltage, i.e., before the entire closed-loop system is closed, Vgs of Mp3 gradually increases, and the current of Mp3 also gradually increases. From the one-to-one mirror relationship between Mp2 and Mp3 in this structure, it can be seen that the current of Mp2 also gradually increases. After the entire system completes the closed loop, the current of Mp3 will not continue to rise, and its current value is: IMp3 = I1 - I2. In the design, I0 can be set to (1 / n) * (I1 - I2). As can be seen from the above analysis, during the rise of Mp2, when IMp2≥I0=(1 / n)*(I1-I2), the drain potential of Mp2 is pulled up, causing Mn1 to conduct. The drain potential of Mn1 is pulled down, causing the inverter output, i.e., the UVLO signal, to reverse from a high level to a low level.

[0025] The advantages of this invention are: the comparison process of the undervoltage lockout structure is synchronized with the establishment process of the bandgap reference voltage and the internal regulated power supply, which avoids the problem that the accuracy of the output results is easily affected by the power-on speed of the traditional scheme. Moreover, the structure of the internal regulated power supply is reused in the structure. On this basis, only a few necessary components are added to solve the problems existing in the traditional structure.

[0026] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. An undervoltage lockout structure whose output is unaffected by the power-on speed, characterized in that, The system includes an error amplifier, the negative input of which is connected to a voltage divider node, and the positive input of which is connected to an internal bandgap reference voltage node. The first path of the voltage divider node is grounded through a first voltage divider resistor, and the second path is connected to the output voltage node of the internal voltage regulator structure through a second voltage divider resistor. The output of the error amplifier is connected to a current sampling circuit and a buffer circuit through a current comparison circuit. The buffer circuit is connected to the undervoltage lockout output signal terminal. The current comparison circuit includes a second PMOS transistor. The gate of the second PMOS transistor is connected to the output terminal of the error amplifier. The source of the second PMOS transistor is connected to the output voltage node of the internal voltage regulator structure of the chip. The drain of the second PMOS transistor is connected to the current comparison node. The current comparison node is grounded through a first current source in the first path and connected to the buffer circuit in the second path. The buffer circuit includes a first inverter and a second inverter connected in series. The output terminal of the second inverter is connected to the undervoltage lockout output signal terminal. The first input terminal of the first inverter is connected to the power supply voltage terminal through a fourth current source, and the second input terminal is connected to the drain of a second NMOS transistor. The gate of the second NMOS transistor is connected to the current comparison node, and the source of the second NMOS transistor is grounded.

2. The undervoltage lockout structure according to claim 1, wherein the output result is not affected by the power-on speed, is characterized in that, The current sampling circuit includes a third PMOS transistor and a second PMOS transistor with a common source and common gate configuration. The source of the third PMOS transistor is connected to the drain of a fourth PMOS transistor. The drain of the third PMOS transistor is first connected to the source of a first NMOS transistor and second connected to ground through a second current source. The source of the fourth PMOS transistor is connected to the power supply voltage terminal. The gate of the fourth PMOS transistor is first connected to the power supply voltage terminal through a third current source and second connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the bias voltage terminal.

3. The undervoltage lockout structure according to claim 2, wherein the output result is not affected by the power-on speed, is characterized in that, Let the bandgap reference voltage be Vbg, the output voltage of the regulated power supply be Vreg, the first resistor be R1, and the second resistor be R2. Then Vreg = Vbg (1+R2 / R1).

4. The undervoltage lockout structure according to claim 3, wherein the output result is not affected by the power-on speed, is characterized in that, The mirror ratio between the second PMOS transistor and the third PMOS transistor is 1:

1.

5. The undervoltage lockout structure according to claim 4, wherein the output result is not affected by the power-on speed, is characterized in that, Let the current from the second current source be I1, the current from the third current source be I2, and the current flowing out of the drain of the third PMOS transistor be Imp3. Then Imp3 = I1 - I2.

6. The undervoltage lockout structure according to claim 5, wherein the output result is not affected by the power-on speed, is characterized in that, a The first current source has a current of I0, and I0 = (1 / n) (I1-I2), where n is an integer greater than 1.

7. The undervoltage lockout structure according to claim 6, wherein the output result is not affected by the power-on speed, is characterized in that, Let Imp2 be the current flowing out of the drain of the second PMOS transistor. Then Imp2 ≥ I0 = (1 / n) (I1-I2), thus, the potential of the current comparison node is pulled up to the second NMOS transistor to turn on, and the drain potential of the second NMOS transistor is pulled down, causing the inverter output, i.e., the UVLO signal, to reverse from a high level to a low level.

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