A minimum on-time test method for boost converter

Abstract

A BOOST converter minimum conduction time test method, by introducing a minimum conduction time test mode, establishing a lower pipe current sampling circuit, setting the rising edge single side delay and the falling edge synchronization mechanism between the lower pipe opening signal and the lower pipe conduction sampling control signal, can be beneficial to restore the delay time on the conduction time path in the open loop case, and then compare with the PWM comparator blanking time, the longer time in the two determines the minimum conduction time of BOOST, and then outputs to the COMP pin, so as to quickly test the minimum conduction time in the open loop case and output to the outside of the chip.

Description

Technical Field

[0001] This invention relates to BOOST converter conduction time testing technology, and in particular to a method for testing the minimum conduction time of a BOOST converter. Background Technology

[0002] Peak current mode boost converters are widely used in boost converter architectures due to their relatively simple loop compensation method. For peak current mode boost converters, the voltage and current at the SW (switching node) experience a certain period of RLC oscillation (RLC being the resistor, inductor, and capacitor) due to the parasitic inductance of the package and PCB board at the moment the lower transistor turns on. This oscillation may cause inaccurate inductor current sampling, leading to false triggering of the PWM (Pulse Width Modulation) comparator. Therefore, a blanking circuit is usually added to the PWM comparator to shield the PWM comparator's comparison output signal during the SW oscillation until the oscillation ends and the current sampling signal becomes stable, after which the PWM comparator resumes comparison and output. Furthermore, since the PWM comparator, current sampling circuit, and drive circuit all have a certain delay time, these delay times and the PWM comparator blanking time all affect the minimum on-time of the boost converter. The minimum on-time determines the minimum duty cycle that the boost converter can achieve, making this parameter of minimum on-time particularly important to customers.

[0003] For peak current-mode boost converters, the blanking time (shielding time) and loop delay time added to shield the parasitic inductance of the lower transistor (LS or LSD) at the moment of turn-on in the RLC (resistor, inductor, capacitor) of the switching node (SW) make it difficult or inaccurate to measure the minimum conduction time of the boost converter. To obtain the minimum conduction time, a common method is to fix the output voltage VOUT under closed-loop operation of the boost converter, gradually increase the input voltage VIN until VIN approaches VOUT, and then measure the low-level pulse width of SW. This test mode based on closed-loop conditions to obtain the minimum conduction time of the boost converter is inefficient and lacks real-time performance. Summary of the Invention

[0004] This invention addresses the defects or deficiencies in existing technologies by providing a method for testing the minimum on-time of a BOOST converter.

[0005] The technical solution of the present invention is as follows:

[0006] A method for testing the minimum on-time of a BOOST converter is characterized by introducing a minimum on-time test mode. This mode restores the delay time on the on-time path, setting the first rising edge of the lower transistor on-time sampling control signal to t1 and the first falling edge to t3. The minimum on-time of the BOOST converter is set to minton, where minton = t3 - t1. The first rising edge of the lower transistor on-time sampling control signal is formed by delaying the rising edge of the lower transistor turn-on signal by a single-sided delay after passing through the sixth shielding circuit in the lower transistor drive circuit, to match the lower transistor being fully turned on. The first falling edge of the lower transistor on-time sampling control signal is synchronized with the first falling edge of the lower transistor turn-on signal. The first falling edge of the lower transistor turn-on signal is formed by the lower transistor current sampling circuit being turned off.

[0007] The lower transistor is an NMOS transistor, with its gate and source interconnected and then grounded. The drain of the NMOS transistor is connected to a switching node, which is connected to the positive terminal of a voltage source. The negative terminal of the voltage source is grounded, and the switching node is connected to the current sampling circuit of the lower transistor.

[0008] The lower current sampling circuit includes a first voltage divider sampling NMOS transistor. The drain of the first voltage divider sampling NMOS transistor is connected to the switching node. The gate of the first voltage divider sampling NMOS transistor is connected to the output terminal of the sixth shielding circuit. The source of the first voltage divider sampling NMOS transistor and the drain of the second voltage divider sampling NMOS transistor are interconnected and then connected to the positive input terminal of the transconductance amplifier. The negative input terminal of the transconductance amplifier and the source of the second voltage divider sampling NMOS transistor are both grounded. The gate of the second voltage divider sampling NMOS transistor is connected to the power supply voltage terminal. The output terminal of the transconductance amplifier is connected to the sampling node. The sampling node is grounded through a third resistor.

[0009] The sampling node is connected to the positive input of the pulse width modulation comparator, the negative input of the pulse width modulation comparator is connected to the output of the error amplifier, the output of the pulse width modulation comparator is connected to the first input of the fourth AND gate logic circuit, the second input of the fourth AND gate logic circuit is connected to the output of the third shielding circuit, the output of the fourth AND gate logic circuit is connected to the second input of the RS latch, the first input of the RS latch is connected to the output of the clock circuit, and the first output of the RS latch is connected to the input of the sixth shielding circuit, and the second output is connected to the input of the third shielding circuit.

[0010] The positive input terminal of the error amplifier is connected to the reference voltage terminal, the negative input terminal is connected to the feedback voltage terminal, the first output terminal is connected to the source of the first NMOS transistor, the second output terminal is connected to the high-level pulse width detection pin through the first transmission gate switch, the gate of the first NMOS transistor is connected to the lower clamp signal terminal, the drain of the first NMOS transistor is connected to the power supply voltage terminal, and the output terminal of the sixth shielding circuit is connected to the high-level pulse width detection pin through the second transmission gate switch. The minimum on-time minton of the BOOST converter is obtained by measuring the high-level pulse width of each internal clock cycle.

[0011] In the minimum conduction time test mode, the first transmission gate switch is in the off state and the second transmission gate switch is in the on state.

[0012] The input terminal of the clock circuit is connected to a frequency reduction shielding circuit.

[0013] The frequency reduction shielding circuit is a seventh AND gate logic circuit. The first input terminal of the seventh AND gate logic circuit is connected to the frequency reduction detection terminal, and the second input terminal is connected to the minimum conduction time test signal.

[0014] The technical effects of this invention are as follows: This invention provides a method for testing the minimum on-time of a BOOST converter. By introducing a minimum on-time test mode and establishing a current sampling circuit for the lower transistor, a mechanism is set between the lower transistor turn-on signal and the lower transistor conduction sampling control signal to achieve a single-sided delay on the rising edge and synchronization on the falling edge. This facilitates the restoration of the delay time on the conduction time path in an open-loop condition. The delay time is then compared with the blanking time of the PWM comparator, and the longer of the two times determines the minimum on-time of the BOOST converter. The result is then output to the COMP pin, thereby quickly testing the minimum on-time in an open-loop condition and outputting it to the outside of the chip.

[0015] The present invention has the following features: 1. A strong voltage source is set at the input of the lower transistor sampling circuit, while the error amplifier is in a lower clamp state, ensuring that the condition for turning off the lower transistor is met immediately as soon as the lower transistor sampling circuit is turned on. 2. The delay times of the PWM comparator, current sampling circuit, and drive circuit are all within the minimum conduction time test loop. 3. The test is performed with FB set high, but the internal clock will not be downclocked.

[0016] Compared with the prior art, the present invention has the following advantages: simple circuit structure, ingenious design, and minimum conduction time that is basically consistent with actual working conditions. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure formed by implementing the minimum conduction time test method of a BOOST converter according to the present invention. A BOOST converter is a boost converter.

[0018] Figure 2 yes Figure 1 A schematic diagram of the signal waveforms of the relevant nodes. Figure 2 The node signals from top to bottom are: feedback voltage signal FB (where the arrow indicates the 3rd rising edge), minimum conduction time test signal Test_minton (entering minimum conduction time test mode on the 3rd rising edge of FB), clock signal Clk (clock), lower MOSFET turn-on signal LS_ON, lower MOSFET shielding module LS_BLANK output signal LS_BLANKB, sampling signal SUM of sampling node SUM, master toggle signal MAIN_TRIP output of pulse width modulation comparator PWM_COMP, and lower MOSFET conduction sampling control signal LS_GATE_SNS (where t3-t1 = minton, t1 is the time when LS_GATE_SNS goes high, i.e., the rising edge of the signal, t3 is the time when LS_GATE_SNS goes low, i.e., the falling edge of the signal, and minton is the minimum conduction time of the BOOST converter).

[0019] The reference numerals in the attached diagram are listed below: EA - Error amplifier (its positive input is connected to the reference voltage VREF, its negative input is connected to the feedback voltage, and the error output signal is eaout); MN1 - First NMOS transistor; VDD - Power supply voltage; Clamp_L - Lower clamp signal; COMP - High-level pulse width detection pin; S1 - First transmission gate switch; S2 - Second transmission gate switch; R3 - Third resistor; sum - Sampling node or sampling signal; Ics - Sampling current; PWM_COMP - Pulse width modulation comparator; MAIN_TRIP - Main flip signal; I3 / LS_BLANK - Third shielding circuit / lower transistor shielding module; I4 - Fourth AND gate logic circuit; I6 / LS_GATE_SNS_BLANK - Sixth shielding circuit (its... Output lower MOSFET conduction sampling control signal LS_GATE_SNS); I7 - seventh AND gate logic circuit; SKIP_det - frequency reduction detection terminal; LS_BLANKB - lower MOSFET shielding module LS_BLANK output signal; Clk / clock - clock circuit / clock signal; Latch - RS latch (including first input S, second input R, output Q); LS_ON - lower MOSFET turn-on signal; M_div1 - first voltage divider sampling NMOS transistor; M_div2 - second voltage divider sampling NMOS transistor; gcs - transconductance amplifier; LSD - lower MOSFET (NMOS transistor); SW - switching node; VSW - switching node voltage; Rds_LS - lower MOSFET drain-source resistance; IminPK - minimum peak current (derived from peak current mode BOOST). Detailed Implementation

[0020] The following is in conjunction with the attached diagram ( Figures 1-2The present invention will be described below.

[0021] Figure 1 This is a schematic diagram of the circuit structure formed by implementing the minimum conduction time test method of a BOOST converter according to the present invention. Figure 2 yes Figure 1 A schematic diagram of the signal waveforms at relevant nodes. (Reference) Figures 1 to 2 As shown, a method for testing the minimum on-time of a BOOST converter includes introducing a minimum on-time test mode. This minimum on-time test mode sets the first rising edge of the lower transistor on-time sampling control signal LS_GATE_SNS to t1 and the first falling edge of the lower transistor on-time sampling control signal LS_GATE_SNS to t3 by restoring the delay time on the on-time path. The minimum on-time of the BOOST converter is set to minton, where minton = t3 - t1. The first rising edge of the lower transistor on-time sampling control signal LS_GATE_SNS is formed by delaying the rising edge of the lower transistor turn-on signal LS_ON by the sixth shielding circuit I6 in the lower transistor drive circuit, to match the lower transistor LSD being fully turned on. The first falling edge of the lower transistor on-time sampling control signal LS_GATE_SNS is synchronized with the first falling edge of the lower transistor turn-on signal LS_ON. The first falling edge of the lower transistor turn-on signal LS_ON is formed by being turned off by the lower transistor current sampling circuit. The lower transistor LSD is an NMOS transistor. The gate and source of the NMOS transistor are interconnected and then grounded. The drain of the NMOS transistor is connected to the switching node SW. The switching node SW is connected to the positive (+) terminal of the voltage source. The negative (-) terminal of the voltage source is grounded. The switching node SW is connected to the current sampling circuit of the lower transistor.

[0022] The lower current sampling circuit includes a first voltage divider sampling NMOS transistor. The drain of the first voltage divider sampling NMOS transistor M_div1 is connected to the switching node SW. The gate of the first voltage divider sampling NMOS transistor M_div1 is connected to the output terminal of the sixth shielding circuit I6. The source of the first voltage divider sampling NMOS transistor M_div1 and the drain of the second voltage divider sampling NMOS transistor M_div2 are interconnected and then connected to the positive input terminal (+) of the transconductance amplifier gcs. The negative input terminal (-) of the transconductance amplifier gcs and the source of the second voltage divider sampling NMOS transistor M_div2 are both grounded. The gate of the second voltage divider sampling NMOS transistor M_div2 is connected to the power supply voltage terminal VDD. The output terminal of the transconductance amplifier gcs is connected to the sampling node sum. The sampling node sum is grounded through the third resistor R3. The sampling node sum is connected to the positive input (+) of the pulse width modulation comparator PWM_COMP, the negative input (-) of the pulse width modulation comparator PWM_COMP is connected to the output eaout of the error amplifier EA, the output of the pulse width modulation comparator PWM_COMP is connected to the first input of the fourth AND gate logic circuit I4, the second input of the fourth AND gate logic circuit I4 is connected to the output of the third shielding circuit I3, the output of the fourth AND gate logic circuit I4 is connected to the second input R of the RS latch, the first input S of the RS latch is connected to the output of the clock circuit Clk, and the first output of the RS latch is connected to the input of the sixth shielding circuit I6, and the second output is connected to the input of the third shielding circuit I3.

[0023] The positive input (+) of the error amplifier EA is connected to the reference voltage terminal VREF, and the negative input (-) is connected to the feedback voltage terminal FB. The first output is connected to the source of the first NMOS transistor MN1, and the second output is connected to the high-level pulse width detection pin COMP via the first transmission gate switch S1. The gate of the first NMOS transistor MN1 is connected to the lower clamp signal terminal Clamp_L, and the drain of the first NMOS transistor MN1 is connected to the power supply voltage terminal VDD. The output of the sixth shielding circuit I6 is connected to the high-level pulse width detection pin COMP via the second transmission gate switch S2. Measuring the high-level pulse width for each internal clock cycle yields the minimum on-time (minton) of the BOOST converter. In the minimum on-time test mode, the first transmission gate switch S1 is in the off state, and the second transmission gate switch S2 is in the on state. The input of the clock circuit Clk is connected to the frequency reduction shielding circuit. The frequency reduction shielding circuit is a seventh AND gate logic circuit I7. The first input terminal of the seventh AND gate logic circuit I7 is connected to the frequency reduction detection terminal SKIP_det, and the second input terminal is connected to the minimum conduction time test signal Test_minton (Test_mintonB).

[0024] This invention proposes a method for testing the minimum conduction time of BOOST. By introducing a minimum conduction time test mode, the delay time on the conduction time path is restored, and then together with the blanking time of the PWM comparator, the minimum conduction time of BOOST is determined, thereby testing the minimum conduction time and outputting it to the outside of the chip.

[0025] This invention introduces a minimum on-time test mode to restore the delay time on the on-time path in an open-loop condition. This delay time is then compared with the blanking time of the PWM comparator. The longer of the two times determines the minimum on-time of the BOOST, which is then output to the COMP pin. This allows for the rapid testing of the minimum on-time in an open-loop condition and its output to the outside of the chip.

[0026] Figure 1 The minimum on-time test circuit of this invention is described, and its working principle is as follows: After power-on initialization is completed, the minimum on-time test mode is entered by detecting the third rising edge of FB. Then, FB remains at a logic high level, so the output of the error amplifier is always in a down-clamped state, causing the lower transistor to be immediately turned off as soon as the current exceeds the minimum peak current. To ensure that the internal clock frequency is normal during testing, an AND gate I7 ​​is used to force the clock not to downclock in the minimum on-time test mode.

[0027] M_div1, Mdiv2, and transconductance amplifier gcs together constitute the lower transistor current sampling circuit. When M_div1 is turned on, it samples the voltage at SW and converts it into a sampling current Ics, which falls on resistor R3 and generates a voltage drop at sum. The sum is compared with the eaout voltage. When sum is higher than eaout, the PWM comparator generates a MAIN_TRIP signal to turn off the sampling circuit through the control loop.

[0028] refer to Figure 1 and Figure 2 The specific detection mechanism for minimum conduction time is as follows:

[0029] 1. When the rising edge of the clock arrives, the RS latch generates a high signal LS_ON:

[0030] After passing through the LS_GATE_SNS_blank detection circuit in the lower transistor driver circuit, the LS_GATE_SNS signal is set high and used to turn on the sampling transistor M_div1. At this time, it is considered that the lower transistor is just fully turned on, and this time is recorded as t1.

[0031] The second LS_ON signal enters the PWM comparator blanking circuit (LS-BLANK module). At the same time, LSD BLANK begins to act as a shield, and the output LS_BLANKB signal goes high after the shielding time is completed. This time is recorded as t2.

[0032] 2. Since the external voltage source Vsw at SW is greater than Rds_LS*IminPK, once LS_GATE_SNS goes high, after the delay time of the gcs circuit, the sum point will immediately be higher than eaout.

[0033] 3. After the PWM comparator delay time, the PWM comparator flips, causing the MAIN_TRIP signal to go high;

[0034] 4. After the MAIN_TRIP signal goes high, wait for the LS_BLANKB time to go high. The trailing edge of either signal is valid, which determines whether LS_ON goes low.

[0035] Case 1: If LS_BLANKB goes high after MAIN_TRIP goes high, then immediately pull LS_ON low.

[0036] Scenario 2: If LS_BLANKB remains low after the MAIN_TRIP signal goes high, wait for the LS_Blanking time to end, and then quickly pull LS_ON low once LS_BLANKB goes high.

[0037] 5. After LS_ON goes low, since LS_GATE_SNS blank only has a one-sided delay on the rising edge and no delay on the falling edge, LS_GATE_SNS immediately goes low after LS_ON goes low. The time when LS_GATE_SNS goes low is recorded as t3.

[0038] As can be seen from the analysis in 1-5 above, (t3-t1) is the minimum conduction time of BOOST. Since we disconnect the eaout and COMP pins through switch S1 in the minimum conduction time test mode, and connect the internal signal LS_GATE_SNS to the external COMP pin through switch S2, the high-level pulse width of the COMP pin in each internal clock cycle is the minimum conduction time of BOOST.

[0039] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A method for testing the minimum on-time of a BOOST converter, characterized in that, This includes introducing a minimum conduction time test mode. The minimum conduction time test mode sets the first rising edge of the lower MOSFET conduction sampling control signal to t1 and the first falling edge of the lower MOSFET conduction sampling control signal to t3 by restoring the delay time on the conduction time path. The minimum conduction time of the BOOST converter is set to minton, then minton = t3 - t1. The first rising edge of the lower MOSFET conduction sampling control signal is formed by delaying the rising edge of the lower MOSFET turn-on signal by the sixth shielding circuit in the lower MOSFET drive circuit, so as to match the lower MOSFET being fully turned on. The first falling edge of the lower MOSFET conduction sampling control signal is synchronized with the first falling edge of the lower MOSFET turn-on signal. The first falling edge of the lower MOSFET turn-on signal is formed by the lower MOSFET current sampling circuit being turned off.

2. The method for testing the minimum on-time of a BOOST converter according to claim 1, characterized in that, The lower transistor is an NMOS transistor, with its gate and source interconnected and then grounded. The drain of the NMOS transistor is connected to a switching node, which is connected to the positive terminal of a voltage source. The negative terminal of the voltage source is grounded, and the switching node is connected to the current sampling circuit of the lower transistor.

3. The method for testing the minimum on-time of a BOOST converter according to claim 2, characterized in that, The lower-side current sampling circuit includes a first voltage-dividing sampling NMOS transistor. The drain of the first voltage-dividing sampling NMOS transistor is connected to the switching node. The gate of the first voltage-dividing sampling NMOS transistor is connected to the output terminal of the sixth shielding circuit. The source of the first voltage-dividing sampling NMOS transistor and the drain of the second voltage-dividing sampling NMOS transistor are interconnected and then connected to the positive input terminal of the transconductance amplifier. The negative input terminal of the transconductance amplifier and the source of the second voltage-dividing sampling NMOS transistor are both grounded. The gate of the second voltage-dividing sampling NMOS transistor is connected to the power supply voltage terminal. The output terminal of the transconductance amplifier is connected to the sampling node. The sampling node is grounded through a third resistor.

4. The method for testing the minimum on-time of a BOOST converter according to claim 3, characterized in that, The sampling node is connected to the positive input of the pulse width modulation comparator, the negative input of the pulse width modulation comparator is connected to the output of the error amplifier, the output of the pulse width modulation comparator is connected to the first input of the fourth AND gate logic circuit, the second input of the fourth AND gate logic circuit is connected to the output of the third shielding circuit, the output of the fourth AND gate logic circuit is connected to the second input of the RS latch, the first input of the RS latch is connected to the output of the clock circuit, and the first output of the RS latch is connected to the input of the sixth shielding circuit, and the second output is connected to the input of the third shielding circuit.

5. The method for testing the minimum on-time of a BOOST converter according to claim 4, characterized in that, The positive input terminal of the error amplifier is connected to the reference voltage terminal, the negative input terminal is connected to the feedback voltage terminal, the first output terminal is connected to the source of the first NMOS transistor, the second output terminal is connected to the high-level pulse width detection pin through the first transmission gate switch, the gate of the first NMOS transistor is connected to the lower clamp signal terminal, the drain of the first NMOS transistor is connected to the power supply voltage terminal, and the output terminal of the sixth shielding circuit is connected to the high-level pulse width detection pin through the second transmission gate switch. The minimum on-time minton of the BOOST converter is obtained by measuring the high-level pulse width of each internal clock cycle.

6. The method for testing the minimum on-time of a BOOST converter according to claim 5, characterized in that, In the minimum conduction time test mode, the first transmission gate switch is in the off state and the second transmission gate switch is in the on state.

7. The method for testing the minimum on-time of a BOOST converter according to claim 4, characterized in that, The input terminal of the clock circuit is connected to a frequency reduction shielding circuit.

8. The method for testing the minimum on-time of a BOOST converter according to claim 7, characterized in that, The frequency reduction shielding circuit is a seventh AND gate logic circuit. The first input terminal of the seventh AND gate logic circuit is connected to the frequency reduction detection terminal, and the second input terminal is connected to the minimum conduction time test signal.

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