Adaptive foldback current limiting circuit using resistive transconductance sampling

Abstract

The adaptive turn-back current limiting circuit with resistive trans-impedance sampling is improved on the basis of the traditional current limiting circuit. The output voltage detection circuit is introduced to reflect the overload degree. The heavier the overload degree is, the smaller the current limiting value is. The original fixed value limiting method is changed to turn-back current limiting, so as to reduce the chip heating and the risk of switch tube breakdown under high output voltage.

Description

Technical Field

[0001] This invention relates to overload current limiting technology for BOOST converters, and in particular to an adaptive foldback current limiting circuit employing resistive transconductance sampling. Background Technology

[0002] Figure 2 This is a schematic diagram of a traditional current-limiting circuit. (Example) Figure 2 As shown, a traditional current limiting circuit includes voltage node B, the sampling current Ics of the BOOST lower transistor (BOOST is a boost converter, and the lower transistor is also called the lower switching transistor), a constant current source I_LIM, a first inverter INV1, and a second inverter INV2. The voltage node B has three paths: the first path connects to the power supply voltage terminal through the lower transistor current sampling circuit; the second path connects to ground through the constant current source I_LIM; and the third path connects to the input terminal of INV1. The output terminal of INV1 is connected to the input terminal of INV2, and the output terminal of INV2 is connected to the overcurrent indication signal terminal (outputting the overcurrent indication signal LIM). Ics flows into voltage node B, and I_LIM flows out of voltage node B. The constant current source I_LIM has a fixed current limiting value. When the sampling current Ics of the lower transistor increases to I_LIM, point B becomes high, and the overcurrent indication signal LIM becomes high. In overload applications, the inductor current of the BOOST converter can be very large, and if not handled properly, the chip may be burned out. Therefore, a current limiting circuit is introduced to limit the peak inductor current. Traditional current limiting circuits limit the peak inductor current to a fixed value when overloaded, regardless of the severity of the overload. This causes the BOOST converter to always operate at the maximum peak current state when overloaded, resulting in severe heat generation. Furthermore, the BOOST switching transistor is at risk of breakdown when the output voltage remains high. Summary of the Invention

[0003] This invention addresses the defects or deficiencies in existing technologies by providing an adaptive foldback current limiting circuit that employs resistive transconductance sampling.

[0004] The technical solution of the present invention is as follows:

[0005] An adaptive foldback current limiting circuit employing resistive transconductance sampling includes a second node. The second node has a first path connected to the power supply voltage terminal via a lower transistor current sampling circuit, a second path grounded via a constant current source, and a third path connected to the input terminal of a first inverter. The output terminal of the first inverter is connected to the input terminal of a second inverter, and the output terminal of the second inverter is connected to an overcurrent indication signal terminal. The lower transistor sampling current Ics flows into the second node, and the constant current source current limiting current I_LIM flows out of the second node. The second node is characterized by a fourth path connected to the feedback voltage terminal FB of the boost converter output voltage via an output voltage detection circuit. When the output voltage detection circuit detects an overload in the boost converter, it generates a foldback current Ifold that flows into the second node, ensuring that the peak value of the lower transistor sampling current Ics allowed by the second node is Ics_peak = I_LIM - Ifold.

[0006] The output voltage detection circuit includes a fourth PMOS transistor and a third PMOS transistor with interconnected gates. The drain of the fourth PMOS transistor is connected to the second node. The sources of the fourth PMOS transistor and the third PMOS transistor are both connected to the power supply voltage terminal. The gate and drain of the third PMOS transistor are interconnected and then connected to the drain of a second NMOS transistor. The gates of the second NMOS transistor and the first NMOS transistor are interconnected and then connected to the first node. The drain of the first NMOS transistor is connected to the first node. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.

[0007] The first node has a first path connected to the drain of the second PMOS transistor and a second path connected to the drain of the fourth NMOS transistor. The second PMOS transistor is interconnected with the gate of the first PMOS transistor and then connected to the drain of the first PMOS transistor. The source of the second PMOS transistor and the source of the first PMOS transistor are both connected to the power supply voltage terminal. The gate of the fourth NMOS transistor is connected to the output terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is connected to the feedback voltage terminal FB. The negative input terminal of the second operational amplifier is interconnected with the source of the fourth NMOS transistor and then grounded through the second resistor R2.

[0008] The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the output of the first operational amplifier, the positive input of the first operational amplifier is connected to the reference voltage terminal VREF, and the negative input of the first operational amplifier is interconnected with the source of the third NMOS transistor and then grounded through the first resistor R1.

[0009] The resistance values ​​of the first resistor R1 and the second resistor R2 are equal, R1 = R2 = R.

[0010] The mirror ratio between the first PMOS transistor and the second PMOS transistor is 1:1, the mirror ratio between the third PMOS transistor and the fourth PMOS transistor is 1:N, the mirror ratio between the first NMOS transistor and the second NMOS transistor is 1:N, where N is an integer greater than 1. A first current I0 flows out of the drain of the first PMOS transistor, a second current I1 flows out of the drain of the second PMOS transistor, and a third current I2 flows into the drain of the fourth NMOS transistor.

[0011] Ifold = [(VREF-FB) / R]*N*N. The more severe the overload of the boost converter, the lower the feedback voltage FB of the boost converter output voltage, and the larger Ifold will be. The corresponding peak current limit value of BOOST will be smaller, thereby reducing the risk of heat generation and switching transistor breakdown.

[0012] The technical effects of this invention are as follows: This invention adopts an adaptive foldback current limiting circuit with resistive transconductance sampling, which is an improvement on the traditional current limiting circuit. An output voltage detection circuit is introduced to reflect the degree of overload. The more severe the overload, the smaller the current limiting value. The original fixed value current limiting method is changed to foldback current limiting, thereby reducing the risk of chip overheating and switching transistor breakdown under high output voltage.

[0013] The present invention has the following characteristics: simple circuit structure, ingenious design, and stronger overload protection capability. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating the structural principle of the adaptive foldback current limiting circuit that employs resistive transconductance sampling to implement the present invention.

[0015] Figure 2 This is a schematic diagram of a traditional current limiting circuit.

[0016] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; LIM - Overcurrent indication signal terminal; INV1 - First inverter; INV2 - Second inverter; I_LIM - Current source (or constant current source); Ics - BOOST lower transistor sampling current (BOOST is a boost converter, and the lower transistor is also called the lower switching transistor); MP0~MP3 - First PMOS transistor to fourth PMOS transistor; MN0~MN3 - First NMOS transistor to fourth NMOS transistor; I0~I2 - First current to third current (where I1 is the reference current and I2 is the sampling current); Ifold - Foldback current; R1~R2 - First resistor to second resistor; AMP1~AMP2 - First operational amplifier to second operational amplifier; FB - Feedback voltage terminal; VREF - Reference voltage terminal; A~B - First node to second node; 1:1 or 1:N - Mirror ratio (N is an integer greater than 1). Detailed Implementation

[0017] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0018] Figure 1 This is a schematic diagram illustrating the structural principle of the adaptive foldback current limiting circuit employing resistive transconductance sampling, which implements the present invention. (Reference) Figure 1 As shown, an adaptive foldback current limiting circuit using resistive transconductance sampling includes a second node B. The second node B has a first path connected to the power supply voltage terminal VDD via a lower transistor current sampling circuit (Ics), a second path grounded via a constant current source I_LIM, and a third path connected to the input terminal of a first inverter INV1. The output terminal of the first inverter INV1 is connected to the input terminal of a second inverter INV2, and the output terminal of the second inverter INV2 is connected to the overcurrent indication signal terminal LIM. The lower transistor sampling current Ics flows into the second node B, and the constant current source current limiting current I_LIM flows out of the second node B. The second node B has a fourth path connected to the feedback voltage terminal FB of the boost converter output voltage via an output voltage detection circuit. When the output voltage detection circuit detects an overload of the boost converter, it generates a foldback current Ifold that flows into the second node B, making the peak value of the allowed lower transistor sampling current Ics at the second node B Ics_peak = I_LIM - Ifold.

[0019] The output voltage detection circuit includes a fourth PMOS transistor MP3 and a third PMOS transistor MP2 with gate interconnection. The drain of the fourth PMOS transistor MP3 is connected to the second node B. The sources of the fourth PMOS transistor MP3 and the third PMOS transistor MP2 are both connected to the power supply voltage terminal VDD. The gate-drain interconnect of the third PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN1. The second NMOS transistor MN1 is connected to the first NMOS transistor MN0 with its gate interconnected and then connected to the first node A. The drain of the first NMOS transistor MN0 is connected to the first node A. The sources of the first NMOS transistor MN0 and the second NMOS transistor MN1 are both grounded. The first node A is connected to the drain of the second PMOS transistor MP1 in the first path and to the drain of the fourth NMOS transistor MP3 in the second path. The gate of the second PMOS transistor MP1 is interconnected with the gate of the first PMOS transistor MP0 and then connected to the drain of the first PMOS transistor MP0. The source of the second PMOS transistor MP1 and the source of the first PMOS transistor MP0 are both connected to the power supply voltage terminal VDD. The gate of the fourth NMOS transistor MN3 is connected to the output terminal of the second operational amplifier AMP2. The positive input terminal (+) of the second operational amplifier AMP2 is connected to the feedback voltage terminal FB. The negative input terminal (-) of the second operational amplifier AMP2 is interconnected with the source of the fourth NMOS transistor MN3 and then grounded through the second resistor R2.

[0020] The drain of the first PMOS transistor MP0 is connected to the drain of the third NMOS transistor MN2. The gate of the third NMOS transistor MN2 is connected to the output of the first operational amplifier AMP1. The positive input (+) of the first operational amplifier AMP1 is connected to the reference voltage terminal VREF. The negative input (-) of the first operational amplifier AMP1 is interconnected with the source of the third NMOS transistor MN2 and then grounded through the first resistor R1. The first resistor R1 and the second resistor R2 have the same resistance value, R1 = R2 = R. The image ratio between the first PMOS transistor MP0 and the second PMOS transistor MP1 is 1:1. The image ratio between the third PMOS transistor MP2 and the fourth PMOS transistor MP3 is 1:N. The image ratio between the first NMOS transistor MN0 and the second NMOS transistor MN1 is 1:N, where N is an integer greater than 1. A first current I0 flows from the drain of the first PMOS transistor MP0, a second current I1 flows from the drain of the second PMOS transistor MP1, and a third current I2 flows into the drain of the fourth NMOS transistor MN3. Ifold = [(VREF-FB) / R]*N*N. The more severe the overload of the boost converter, the lower the feedback voltage FB of the boost converter output voltage, and the larger Ifold will be. The corresponding peak current limit value of BOOST will be smaller, thereby reducing the risk of heat generation and switching transistor breakdown.

[0021] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. An adaptive foldback current limiting circuit employing resistive transconductance sampling, comprising a second node, wherein the second node has a first path connected to the power supply voltage terminal via a lower transistor current sampling circuit, a second path grounded via a constant current source, and a third path connected to the input terminal of a first inverter. The output terminal of the first inverter is connected to the input terminal of a second inverter, and the output terminal of the second inverter is connected to an overcurrent indication signal terminal. The lower transistor sampling current Ics flows into the second node, and the constant current source current limiting current I_LIM flows out of the second node. The circuit is characterized in that... The fourth path of the second node is connected to the feedback voltage terminal FB of the boost converter output voltage through the output voltage detection circuit. When the output voltage detection circuit detects that the boost converter is overloaded, a foldback current Ifold flows into the second node, so that the peak value of the allowed lower transistor sampling current Ics of the second node is Ics_peak = I_LIM - Ifold. The output voltage detection circuit includes a fourth PMOS transistor and a third PMOS transistor with interconnected gates. The drain of the fourth PMOS transistor is connected to the second node. The sources of the fourth PMOS transistor and the third PMOS transistor are both connected to the power supply voltage terminal. The gate and drain of the third PMOS transistor are interconnected and then connected to the drain of a second NMOS transistor. The second NMOS transistor is interconnected with the gate of the first NMOS transistor and then connected to the first node. The drain of the first NMOS transistor is connected to the first node. The sources of the first NMOS transistor and the second NMOS transistor are both grounded. The first node has a first path connected to the drain of the second PMOS transistor and a second path connected to the drain of the fourth NMOS transistor. The second PMOS transistor is interconnected with the gate of the first PMOS transistor and then connected to the drain of the first PMOS transistor. The source of the second PMOS transistor and the source of the first PMOS transistor are both connected to the power supply voltage terminal. The gate of the fourth NMOS transistor is connected to the output terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is connected to the feedback voltage terminal FB. The negative input terminal of the second operational amplifier is interconnected with the source of the fourth NMOS transistor and then grounded through the second resistor R2. The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the output of the first operational amplifier, the positive input of the first operational amplifier is connected to the reference voltage terminal VREF, and the negative input of the first operational amplifier is interconnected with the source of the third NMOS transistor and then grounded through the first resistor R1.

2. The adaptive foldback current limiting circuit using resistive transconductance sampling according to claim 1, characterized in that, The first resistor R1 and the second resistor R2 have the same resistance value, R1 = R2 = R.

3. The adaptive foldback current limiting circuit using resistive transconductance sampling according to claim 2, characterized in that, The mirror ratio between the first PMOS transistor and the second PMOS transistor is 1:1, the mirror ratio between the third PMOS transistor and the fourth PMOS transistor is 1:N, the mirror ratio between the first NMOS transistor and the second NMOS transistor is 1:N, where N is an integer greater than 1. A first current I0 flows out of the drain of the first PMOS transistor, a second current I1 flows out of the drain of the second PMOS transistor, and a third current I2 flows into the drain of the fourth NMOS transistor.

4. The adaptive foldback current limiting circuit using resistive transconductance sampling according to claim 3, characterized in that, Ifold=[(VREF-FB) / R] N The more severe the overload of the boost converter, the lower the feedback voltage FB of the boost converter output voltage, the larger Ifold, and the smaller the corresponding BOOST peak current limit value, thereby reducing the risk of heat generation and switching transistor breakdown.

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