Dead-band regulating device and inverter using the same

Abstract

The present application provides a dead-time adjusting device and a converter using the same. The converter includes a first switch tube, and the dead-time adjusting device includes a communication bus, an integrated circuit and a controller. The integrated circuit includes a second switch tube, a sampling processing circuit and a bus control circuit. The control signal of the second switch tube is complementary to the control signal of the first switch tube and has a dead-time. The sampling processing circuit samples the voltage on the second switch tube to obtain the length of the dead-time, and correspondingly generates a digital signal. The bus control circuit transmits the digital signal to the communication bus by switching on and off. The controller receives the digital signal of the bus control circuit through the communication bus, aligns the communication timing of the communication bus before transmitting the digital signal to the communication bus, and adjusts the length of the dead-time according to the received digital signal.

Description

Technical Field

[0001] This case relates to a dead-time adjustment device and a converter applicable thereto, and more particularly to a dead-time adjustment device capable of precisely controlling the dead time of a switching transistor and a converter applicable thereto. Background Technology

[0002] In recent years, energy consumption has received widespread attention from society, and the principle of energy conservation and environmental protection has been increasingly emphasized. Therefore, reducing the losses of power converters to improve their efficiency has become particularly important.

[0003] For half-bridge DC-DC power converters, parasitic parameters in the power devices and printed circuit boards cause delays in the turn-on and turn-off of the power switches. Furthermore, peripheral circuits such as the driver chip also introduce delays in the drive signals. These delays can easily cause the primary and secondary switches of the half-bridge DC-DC power converter to turn on simultaneously, leading to shoot-through. In this case, the power supply will directly ground, generating a significant short-circuit current, which can ultimately damage the power switches due to thermal breakdown. Therefore, to avoid shoot-through, a dead time must be introduced into the control signals of the switches.

[0004] Furthermore, in existing half-bridge DC-DC converters, diodes are used for rectification on the secondary side. However, diodes have the disadvantage of excessively high forward voltage drop. When the rectified current is large, the conduction loss of the diodes becomes significant, thus affecting the overall efficiency of the converter. To solve this problem, synchronous rectification technology has emerged. This technology uses MOSFETs as synchronous rectification devices, leveraging their low on-resistance to greatly reduce the power loss of synchronous rectification devices, thereby significantly improving the efficiency of the converter. However, since MOSFETs are active devices, appropriate control signals are required to ensure the normal operation of the converter. Controlling the dead time in the control signal has always been one of the challenges in the application of synchronous rectification technology. If the dead time control is not precise enough, the efficiency of the converter cannot be maximized, and in severe cases, it may even cause the secondary side current to flow back to the primary side, making the converter unable to operate normally.

[0005] Therefore, there is an urgent need to provide a dead-zone adjustment device and a converter suitable for improving the above-mentioned prior art. Summary of the Invention

[0006] The purpose of this invention is to provide a dead-time adjustment device and a converter applicable to it. By sampling the voltage on the switching transistor in the integrated circuit, the duration of the dead time in the control signal of the switching transistor is obtained and a corresponding digital signal is generated. Thus, the duration of the dead time can be precisely controlled and adjusted based on the digital signal to reduce the loss caused by the dead time and improve the efficiency of the converter.

[0007] To achieve the above objectives, this invention provides a dead-time adjustment device suitable for a converter including a first switching transistor, and comprising a communication bus, an integrated circuit, and a controller. The integrated circuit is electrically connected to the communication bus for communication and includes a second switching transistor, a sampling processing circuit, and a bus control circuit. The control signal of the second switching transistor is complementary to the control signal of the first switching transistor and has a dead time. The sampling processing circuit samples the voltage on the second switching transistor to obtain the duration of the dead time and generates a digital signal based on the duration of the dead time. The bus control circuit includes at least one switch and transmits digital signals to the communication bus by turning the switch on and off. The controller is electrically connected to the communication bus for communication, wherein the controller receives digital signals from the bus control circuit through the communication bus, performs communication timing alignment of the communication bus before transmitting digital signals on the communication bus, and adjusts the duration of the dead time according to the received digital signals.

[0008] To achieve the above objectives, this invention also provides a converter, comprising a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal, a first switching transistor, and a dead-time adjustment device. The positive and negative input terminals are used to receive input signals, and the positive and negative output terminals are used to output output signals. The first switching transistor is electrically connected to the positive input terminal. The second switching transistor of the integrated circuit of the dead-time adjustment device is electrically connected to the negative output terminal. The converter is used to convert the input signal into an output signal.

[0009] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the circuit structure of a converter and its dead-time adjustment device according to an embodiment of this case.

[0011] Figure 2 for Figure 1 A schematic diagram of the waveforms of some signals in the converter.

[0012] Figure 3 for Figure 2 A magnified view of a portion of the image.

[0013] Figure 4 exemplify Figure 1 The circuit architecture of the sampling processing circuit in the middle.

[0014] Figure 5A and Figure 5B for Figure 4 The schematic diagram of the comparator circuit in the image.

[0015] Figure 6 for Figure 1A schematic diagram of the process by which a dead-time adjustment device adjusts the duration of the dead time based on a voltage signal.

[0016] Figure 7 for Figure 1 A schematic diagram of the dead zone adjustment device.

[0017] Figure 8A and Figure 8B exemplify Figure 1 The bus control circuit transmits the implementation state of any bit in the digital signal to the communication bus.

[0018] Figure 9 exemplify Figure 1 The communication timing of the bus control circuit transmitting a digital signal to the communication bus.

[0019] Figure 10A and Figure 10B An example is shown where the dead-time adjustment device includes multiple integrated circuits connected in parallel.

[0020] Among them, the attached reference numerals

[0021] 1a: Converter

[0022] Vin+: Input positive terminal

[0023] Vin-: Negative input terminal

[0024] S1: First primary-side switching transistor

[0025] S2: Second primary-side switching transistor

[0026] 11: Transformer

[0027] 2a: Integrated Circuits

[0028] 12: Controller

[0029] CB: Communication Bus

[0030] Vo+: Positive output terminal

[0031] Vo-: Negative output terminal

[0032] 111: Primary winding

[0033] 112: Secondary winding

[0034] C1, C2: Input capacitors

[0035] Co: Output capacitor

[0036] S3: First secondary-side switching transistor

[0037] S4: Second auxiliary switch transistor

[0038] 21: Sampling Processing Circuit

[0039] PWM1: Control signal for the first primary-side switch S1

[0040] PWM2: Control signal for the second primary-side switch S2

[0041] PWM3: Control signal for the first secondary-side switch S3

[0042] PWM4: Control signal for the second secondary-side switch S4

[0043] Vsd3: Source-drain voltage of the first secondary-side switching transistor S3

[0044] Vsd4: Source-drain voltage of the second secondary-side switch S4

[0045] D1: Drive pin of the first secondary-side switch S3

[0046] D2: Drive pin of the second secondary-side switch S4

[0047] CS: Current pin

[0048] TEMP: Temperature pin

[0049] Dt: Digital signal pin

[0050] DT: Digital Signal

[0051] t0, t1, t2, t3, t4, t5, t6, t7, t8: Time points

[0052] Ts: Switching cycle

[0053] Vf: Diode forward voltage drop

[0054] PWM4F, PWM4R: Pulse signals

[0055] PWM3F, PWM3R: Pulse signals

[0056] T3R, T3F, T4R, T4F: Dead Time

[0057] 211: Sampling Circuit

[0058] 212: Signal conversion circuit

[0059] 213: Comparator Circuit

[0060] V3F, V3R, V4F, V4R: Voltage signals

[0061] Vth_up: Upper limit threshold

[0062] Vth_down: Lower threshold

[0063] 214: Comparator

[0064] 215: Register

[0065] Bit0, Bit1, Bit2, Bit3, Bit4, Bit5, Bit6, Bit7: bits

[0066] S61, S62, S63, S64, S65, S66, S67: Steps

[0067] Vstep: Adjustment range

[0068] 22: Bus control circuit

[0069] S22: Switch

[0070] Vcc: Voltage

[0071] Rup: Pull-up resistor

[0072] T1, T2, T3: Time periods

[0073] Tb: Duration

[0074] 2a1, 2a2, 2an: Integrated circuits

[0075] S31, S32, S3n: First secondary-side switching transistors

[0076] S41, S42, S4n: Secondary side switching transistors Detailed Implementation

[0077] Some typical embodiments embodying the features and advantages of this invention will be described in detail in the following description. It should be understood that this invention can have various variations under different implementation methods, all of which do not depart from the scope of this invention, and the descriptions and illustrations therein are for illustrative purposes only and are not intended to limit this invention.

[0078] Figure 1 This is a schematic diagram of the circuit structure of a converter and its dead-time adjustment device according to an embodiment of this case. Figure 1As shown, converter 1a is a half-bridge DC-DC converter, and includes an input positive terminal Vin+, an input negative terminal Vin-, a first primary-side switch S1, a second primary-side switch S2, a transformer 11, a dead-time adjustment device, an output positive terminal Vo+, and an output negative terminal Vo-. The dead-time adjustment device includes an integrated circuit 2a, a communication bus CB, and a controller 12. The input positive terminal Vin+ and the input negative terminal Vin- are used to receive an input signal, and the output positive terminal Vo+ and the output negative terminal Vo- are used to output an output signal. Converter 1a is used to convert the input signal into the output signal. The first primary-side switch S1 and the second primary-side switch S2 are connected in series between the input positive terminal Vin+ and the input negative terminal Vin-, and the first primary-side switch S1 and the second primary-side switch S2 are respectively connected to the input positive terminal Vin+ and the input negative terminal Vin-. Transformer 11 includes a primary winding 111 and a secondary winding 112, wherein the first end of the primary winding 111 is electrically connected to the connection point between the first primary switching transistor S1 and the second primary switching transistor S2. Transformer 11 may be, for example, but not limited to, an isolation transformer. In some embodiments, converter 1a further includes input capacitors C1 and C2 connected in series between the positive input terminal Vin+ and the negative input terminal Vin-, the capacitor bridge arm formed by input capacitors C1 and C2 is connected in parallel with the switch bridge arm formed by the first primary switching transistor S1 and the second primary switching transistor S2, and the second end of the primary winding 111 of transformer 11 is electrically connected to the connection point between input capacitors C1 and C2. In some embodiments, converter 1a further includes an output capacitor Co electrically connected between the positive output terminal Vo+ and the negative output terminal Vo-.

[0079] In the dead-time adjustment device, integrated circuit 2a and controller 12 are electrically connected to a single communication bus CB and communicate with each other. Integrated circuit 2a includes a first secondary-side switch S3, a second secondary-side switch S4, and a sampling processing circuit 21. Integrated circuit 2a is integrated into a single chip, thereby greatly reducing the impact of noise on the sampling accuracy of the sampling processing circuit 21. The first secondary-side switch S3 and the second secondary-side switch S4 are used for secondary-side synchronous rectification. The first secondary-side switch S3 is electrically connected between the first end of the secondary winding 112 and the output negative terminal Vo-, the second end of the secondary winding 112 is electrically connected to the output positive terminal Vo+, and the second secondary-side switch S4 is electrically connected between the third end of the secondary winding 112 and the output negative terminal Vo-. Furthermore, as... Figure 2As shown, the control signal PWM3 of the first secondary-side switch S3 is complementary to the control signal PWM1 of the first primary-side switch S1 and has a dead time. The control signal PWM4 of the second secondary-side switch S4 is complementary to the control signal PWM2 of the second primary-side switch S2 and also has a dead time. The sampling processing circuit 21 samples the voltage on the first secondary-side switch S3 to obtain the duration of the dead time of the control signal PWM3 (i.e., the dead time corresponding to the first secondary-side switch S3), and samples the voltage on the second secondary-side switch S4 to obtain the duration of the dead time of the control signal PWM4 (i.e., the dead time corresponding to the second secondary-side switch S4). Based on the duration of the dead time corresponding to the first secondary-side switch S3 and the dead time corresponding to the second secondary-side switch S4, the sampling processing circuit 21 generates a digital signal DT. Integrated circuit 2a transmits digital signal DT to communication bus CB. Controller 12 receives digital signal DT transmitted by integrated circuit 2a via communication bus CB. Controller 12 controls the control signals of each switch in converter 1a according to digital signal DT, so as to precisely control and adjust the duration of the two dead times corresponding to the first secondary switch S3 and the second secondary switch S4, thereby reducing the loss caused by dead time and improving the efficiency of converter 1a.

[0080] The switching transistors in converter 1a can be, for example, but not limited to, MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated gate bipolar transistors), SiC (silicon carbide) transistors, or GaN (gallium nitride) transistors. In this embodiment, the switching transistors in converter 1a are MOSFETs. The drain and source of the first secondary-side switching transistor S3 are electrically connected to the first terminal of the secondary winding 112 and the output negative terminal Vo-, respectively. The drain and source of the second secondary-side switching transistor S4 are electrically connected to the third terminal of the secondary winding 112 and the output negative terminal Vo-, respectively. Correspondingly, the voltages on the first secondary-side switching transistor S3 and the second secondary-side switching transistor S4 sampled by the sampling processing circuit 21 are the source-drain voltage Vsd3 of the first secondary-side switching transistor S3 and the source-drain voltage Vsd4 of the second secondary-side switching transistor S4, respectively.

[0081] In some embodiments, integrated circuit 2a has two drive pins, D1 and D2, electrically connected to the gates of the first secondary-side switch S3 and the second secondary-side switch S4, respectively, for receiving control signals PWM3 and PWM4 and providing them to the first secondary-side switch S3 and the second secondary-side switch S4. In some embodiments, integrated circuit 2a has two drain pins (not shown), the drains of the first secondary-side switch S3 and the second secondary-side switch S4 being electrically connected to the first and third ends of the secondary winding 112 via the two drain pins, respectively. In some embodiments, integrated circuit 2a has a digital signal pin Dt electrically connected to the sampling processing circuit 21, wherein the digital signal pin Dt is used to output a digital signal DT to the controller 12.

[0082] In some embodiments, the sampling processing circuit 21 includes a current sampling circuit (not shown), and the integrated circuit 2a has a current pin CS electrically connected to the current sampling circuit. The current sampling circuit samples the current flowing through the first secondary-side switch S3 and the current flowing through the second secondary-side switch S4 and generates a current signal. The current pin CS is used to output the current signal. In some embodiments, the sampling processing circuit 21 includes a temperature detection circuit (not shown), and the integrated circuit 2a has a temperature pin TEMP electrically connected to the temperature detection circuit. The temperature detection circuit detects the temperatures of the first secondary-side switch S3 and the second secondary-side switch S4 to generate a temperature signal. The temperature pin TEMP is used to output the temperature signal.

[0083] Figure 2 for Figure 1 A waveform diagram of some signals in the converter. Figure 3 for Figure 2 A magnified view of a portion of the image. (See attached image.) Figure 2 As shown, control signals PWM1 and PWM3 are complementary, and control signals PWM2 and PWM4 are complementary. The period from time t0 to t8 is one switching cycle Ts. Taking the second secondary-side switch S4 as an example, when control signal PWM4 is high (e.g., Figure 2During the period from t0 to t4, the rectified current flows through the conductive channel of the second secondary-side switch S4. Therefore, the source-drain voltage Vsd4 of the second secondary-side switch S4 is the voltage drop across the on-resistance of the second secondary-side switch S4 caused by the rectified current. At time t4, when the control signal PWM4 changes from high to low, the conductive channel in the second secondary-side switch S4 is turned off. At this time, current still flows through the body diode of the second secondary-side switch S4. Therefore, the source-drain voltage Vsd4 of the second secondary-side switch S4 is the forward voltage drop of the body diode (denoted as -Vf). Afterward, the second secondary-side switch S4 is turned off due to reverse voltage. At time t6, the second primary-side switch S2 is turned off, and the second secondary-side switch S4 is subjected to a positive voltage. Since the control signal PWM4 is still at a low level, during the period from t6 to t7, the rectified current flows through the body diode of the second secondary-side switch S4. The source-drain voltage Vsd4 of the second secondary-side switch S4 is the forward voltage drop (-Vf) of the body diode. At time t7, the control signal PWM4 changes from a low level to a high level, and the source-drain voltage Vsd4 of the second secondary-side switch S4 is the voltage drop formed by the rectified current across the on-resistance of the second secondary-side switch S4. Figure 2 and Figure 3 As shown, in this switching cycle Ts, the dead time T4F is located at the falling edge of the control signal PWM4 from time t4 to t5, and the dead time T4R is located at the rising edge of the control signal PWM4 from time t6 to t7. The sampling processing circuit 21 generates two pulse signals PWM4F and PWM4R by sampling the source-drain voltage Vsd4 of the second secondary-side switch S4. The pulse signal PWM4F reflects the duration of the dead time T4F located at the falling edge of the control signal PWM4, and the pulse signal PWM4R reflects the duration of the dead time T4R located at the rising edge of the control signal PWM4.

[0084] The operation of the first secondary-side switch S3 is similar to that of the second secondary-side switch S4, so it will not be described again here. Similarly, the sampling processing circuit 21 generates two pulse signals PWM3F and PWM3R by sampling the source-drain voltage Vsd3 of the first secondary-side switch S3. The pulse signal PWM3F reflects the duration of the dead time T3F at the falling edge of the control signal PWM3, and the pulse signal PWM3R reflects the duration of the dead time T3R at the rising edge of the control signal PWM3.

[0085] Figure 4 exemplify Figure 1 The circuit architecture of the sampling processing circuit in the example. Figure 4As shown, the sampling processing circuit 21 includes a sampling circuit 211, a signal conversion circuit 212, and a comparison circuit 213 that are electrically connected to each other. The sampling circuit 211 samples the voltage on the switching transistor in the integrated circuit 2a to generate a pulse signal reflecting the duration of the dead time in the control signal of the switching transistor. The signal conversion circuit 212 converts the pulse signal into a voltage signal reflecting the duration of the dead time. The comparison circuit 213 compares the voltage signal with a threshold to generate a digital signal DT. The controller 12 receives the digital signal DT generated by the comparison circuit 213 via the communication bus CB and adjusts the control signal of the switching transistor in the converter 1a according to the digital signal DT, thereby adjusting the duration of the dead time.

[0086] In this embodiment, the sampling processing circuit 21 includes two sampling circuits 211 and two signal conversion circuits 212. In the sampling circuit 211 and signal conversion circuit 212 corresponding to the first secondary-side switch S3, the sampling circuit 211 samples the source-drain voltage Vsd3 of the first secondary-side switch S3 to generate two pulse signals PWM3F and PWM3R. The signal conversion circuit 212 converts the two pulse signals PWM3F and PWM3R into voltage signals V3F and V3R, respectively, and provides them to the comparator circuit 213. Similarly, in the sampling circuit 211 and signal conversion circuit 212 corresponding to the second secondary-side switch S4, the sampling circuit 211 samples the source-drain voltage Vsd4 of the second secondary-side switch S4 to generate two pulse signals PWM4F and PWM4R. The signal conversion circuit 212 converts the two pulse signals PWM4F and PWM4R into voltage signals V4F and V4R, respectively, and provides them to the comparator circuit 213. Voltage signals V3F, V3R, V4F, and V4R respectively reflect the durations of the corresponding dead times T3F, T3R, T3F, and T4R. In practice, the number of sampling circuits 211 and signal conversion circuits 212 is unlimited; their number can correspond to the number of switching transistors in integrated circuit 2a, or sampling and signal conversion can be performed solely by the same sampling circuit 211 and the same signal conversion circuit 212.

[0087] Furthermore, in this embodiment, the signal conversion circuit 212 is an integrator circuit that converts the pulse signal into a voltage signal through integration. The magnitude of the voltage signal is proportional to the duration of the dead time; specifically, the larger the voltage signal, the longer the dead time, and vice versa. However, in practice, the implementation of the signal conversion circuit 212 is not limited to this; it can be any circuit capable of converting a pulse signal into a voltage signal reflecting the duration of the dead time.

[0088] Comparator circuit 213 receives all voltage signals V3F, V3R, V4F, and V4R, compares each voltage signal with the upper threshold Vth_up and the lower threshold Vth_down, and generates a digital signal DT based on all comparison results. The controller 12 of converter 1a controls the control signals PWM1, PWM2, PWM3, and PWM4 of all switching transistors according to the digital signal DT to adjust the duration of each dead time.

[0089] Figure 5A and Figure 5B for Figure 4 The schematic diagram of the comparator circuit in the image shows the bits of the digital signal DT. For example... Figure 5A As shown, the comparator circuit 213 includes a comparator 214 and a register 215. The comparator 214 is used to compare the voltage signal and the threshold, and generate a dead-time adjustment instruction based on the comparison result. The dead-time adjustment instruction is stored in the register 215, and the digital signal DT generated by the comparator circuit 213 contains all the dead-time adjustment instructions in the register 215.

[0090] In this embodiment, the comparator circuit 213 includes eight comparators 214 and an eight-bit register 215. Each comparator 214 compares the corresponding voltage signal (V3F, V3R, V4F, or V4R) with the corresponding threshold (Vth_up or Vth_down) to generate a dead-time adjustment instruction, which is stored in the corresponding bit (Bit0, Bit1, Bit2, Bit3, Bit4, Bit5, Bit6, or Bit7) in the register 215. The voltage signal, threshold, and bit for each of the eight comparators 214 are as follows: Figure 5A As shown in the diagram, in register 215, bits 0 and 1 represent dead-time adjustment instructions (Bit0, Bit1) corresponding to the dead time T3R at the rising edge of control signal PWM3; bits 2 and 3 represent dead-time adjustment instructions (Bit2, Bit3) corresponding to the dead time T3F at the falling edge of control signal PWM3; bits 4 and 5 represent dead-time adjustment instructions (Bit4, Bit5) corresponding to the dead time T4R at the rising edge of control signal PWM4; and bits 6 and 7 represent dead-time adjustment instructions (Bit6, Bit7) corresponding to the dead time T4F at the falling edge of control signal PWM4. All bits in register 215 (i.e., all dead-time adjustment instructions) form the digital signal DT.

[0091] Based on the digital signal DT, the controller 12 adjusts the duration of each dead time by controlling the control signals of each switching transistor. Since the adjustment methods for each dead time are similar, this example only focuses on the dead time T3R located at the rising edge of the control signal PWM3. Figure 5B As shown in Tables 1 and 2, when the upper threshold Vth_up is greater than the lower threshold Vth_down, and the corresponding voltage signal V3R is less than the lower threshold Vth_down, bits Bit0 and Bit1 are both 0, and the corresponding dead-time adjustment instruction is (0,0). In this case, controller 12 increases the duration of the dead time T3R. When the voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up, bits Bit0 and Bit1 are 0 and 1 respectively, and the corresponding dead-time adjustment instruction is (0,1). In this case, controller 12 does not adjust the duration of the dead time T3R, i.e., it maintains the current duration of the dead time T3R. When the voltage signal V3R is greater than the upper threshold Vth_up, bits Bit0 and Bit1 are both 1, and the corresponding dead-time adjustment instruction is (1,1). In this case, controller 12 decreases the duration of the dead time T3R.

[0092] Table 1

[0093] V3R <Vth_down 0 0 Vth_down≤V3R≤Vth_up 0 1 V3R>Vth_up 1 1

[0094] Table 2

[0095] (0,0) Increase the duration of dead time. (0,1) Duration of maintaining the current dead zone (1,1) Reduce the duration of dead time

[0096] The corresponding adjustment process is illustrated in the example below. Figure 6 Taking the dead time T3R at the rising edge of the control signal PWM3 as an example, firstly, it is determined whether the corresponding voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up (step S61). If the determination result is yes, that is, the voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up, then the current dead time T3R is maintained (step S62). If the determination result is no, that is, the voltage signal V3R is less than the lower threshold Vth_down or greater than the upper threshold Vth_up, then it is further determined whether the voltage signal V3R is less than the lower threshold Vth_down (step S63).

[0097] If the determination result of step S63 is yes, that is, the voltage signal V3R is less than the lower threshold Vth_down, then the dead time T3R is increased (step S64). Then, it is determined whether the voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up (step S65). If the determination result is yes, then the current dead time T3R is maintained (step S62). If the determination result is no, then the dead time T3R is increased again (step S64). In this way, when the voltage signal V3R is less than the lower threshold Vth_down, the dead time T3R will be gradually increased until the voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up.

[0098] If the result of step S63 is negative, i.e., the voltage signal V3R is greater than the upper threshold Vth_up, then the duration of the dead time T3R is reduced (step S66). Then, it is determined whether the voltage signal V3R is between the lower threshold Vth_down and the upper threshold Vth_up (step S67). If the result is positive, the current duration of the dead time T3R is maintained (step S62). If the result is negative, the duration of the dead time T3R is reduced again (step S67). Thus, when the voltage signal V3R is greater than the upper threshold Vth_up, the duration of the dead time T3R is gradually reduced until the voltage signal V3R falls between the lower threshold Vth_down and the upper threshold Vth_up.

[0099] It should be noted that when increasing or decreasing the dead time T3R (steps S64 and S66), the adjustment increment is Vstep each time. Vstep is less than the difference between the lower threshold Vth_down and the upper threshold Vth_up. The specific value of Vstep can be designed based on the switching frequency of converter 1a and the duration of each dead time. This allows for precise control and adjustment of the dead time duration, reducing losses caused by dead time and improving converter efficiency.

[0100] Figure 7 for Figure 1 A schematic diagram of the dead-zone adjustment device. (See diagram below.) Figure 7As shown, integrated circuit 2a also includes bus control circuit 22, which is electrically connected to sampling processing circuit 21 and communication bus CB, and includes at least one switch S22. Sampling processing circuit 21 obtains the dead time duration by sampling the voltage of each secondary-side switch, generates a corresponding digital signal DT, and stores the digital signal DT in register 215. Bus control circuit 22 transmits the digital signal DT to communication bus CB by turning switch S22 on and off, so that controller 12 can receive the digital signal DT through communication bus CB, and control the control signals of each switch in converter 1a according to the digital signal DT, so as to accurately control and adjust the duration of the two dead times corresponding to the first secondary-side switch S3 and the second secondary-side switch S4 respectively.

[0101] Specifically, the bus control circuit 22 also includes a pull-up resistor Rup, whose two ends are electrically connected to the voltage Vcc and the first terminal of switch S22, respectively, while the second terminal of switch S22 is grounded. When the bit value of the digital signal DT is logic 0, switch S22 is turned on, and the bus control circuit 22 outputs a low level (i.e., logic 0) to the communication bus CB; when the bit value of the digital signal DT is logic 1, switch S22 is turned off, and the bus control circuit 22 outputs a high level (i.e., logic 1) to the communication bus CB. In this way, the bus control circuit 22 transmits each bit value of the digital signal DT to the communication bus CB through the on / off state of switch S22.

[0102] Figure 8A and Figure 8B exemplify Figure 1 The bus control circuit 22 transmits the implementation state sample of any bit in the digital signal DT to the communication bus CB. Figure 8A and Figure 8B In the diagram, the transmitted bits are 1 and 0 respectively. The solid line represents the signal output by the bus control circuit 22, and the dashed line reflects the control of the communication bus CB by the controller 12. For example... Figure 8A and Figure 8B As shown, first at time t0, controller 12 pulls the signal in the communication bus CB low to perform communication timing alignment and inform integrated circuit 2a that communication is about to begin. Next, the bus control circuit 22 of integrated circuit 2a transmits a high-level or low-level signal (reflecting a bit value of 1 or 0) to the communication bus CB. Then, at time t1, controller 12 reads the signal transmitted by bus control circuit 22 in the communication bus CB to determine the value of the corresponding bit. In other embodiments, controller 12 can also perform communication timing alignment by pulling the signal in the communication bus CB high.

[0103] Figure 9 exemplify Figure 1 The bus control circuit 22 transmits a digital signal DT to the communication bus CB according to the communication timing. For example... Figure 9 As shown, during time period T1, controller 12 pulls the signal in communication bus CB low to align communication timing and informs integrated circuit 2a that communication is about to begin. During time period T2, controller 12 raises the signal in communication bus CB to AGV to achieve a delay. During time period T3, bus control circuit 22 first outputs the header check code, then sequentially outputs each bit of the digital signal DT, and finally outputs the tail check code. In this embodiment, the header check code contains two bits of 1 and 0, and the tail check code contains two bits of 0 and 1; however, this is not a limitation in practical applications. After receiving the header check code, digital signal DT, and tail check code through communication bus CB, controller 12 needs to verify the header and tail check codes. If the verification is correct, controller 12 determines that the received digital signal DT is valid and then adjusts the dead time based on the received digital signal DT; otherwise, if the verification fails, controller 12 determines that the received digital signal DT is invalid and maintains the existing dead time duration. Figure 9 In this context, tb represents the time required to transmit any single bit.

[0104] In some embodiments, during time period T1, the controller 12 can also perform communication timing alignment by raising the signal in the communication bus CB. Correspondingly, during time period T2, the controller 12 pulls the signal in the communication bus CB low to achieve a delay. This application is not limited to the foregoing. In some embodiments, the controller 12 communicates with the bus control circuit 22 through the communication bus CB at a fixed frequency to receive the digital signal DT.

[0105] Additionally, in some embodiments, multiple integrated circuits can be connected in parallel to achieve higher output power in order to increase the power rating of the converter. For example... Figure 10A As shown, the dead-time adjustment device includes n integrated circuits 2a1, 2a2, ..., 2an connected in parallel, where n is an integer greater than 1. Each integrated circuit is electrically connected to the communication bus CB and communicates with the controller 12 through the communication bus CB. In some embodiments, each integrated circuit can communicate with the controller 12 simultaneously. Figure 10B This example illustrates the connection relationships between secondary-side switches when the dead-time regulation device contains multiple integrated circuits. For example... Figure 10B As shown, all first-side switches S31, S32, ..., S3n are connected in parallel, and all second-side switches S41, S42, ..., S4n are connected in parallel. Figure 10BFor the sake of simplicity, the complete integrated circuits 2a1, 2a2, ..., 2an are not shown in the diagram. In reality, secondary-side switches S31 and S41 belong to integrated circuit 2a1, secondary-side switches S32 and S42 belong to integrated circuit 2a2, and secondary-side switches S3n and S4n belong to integrated circuit 2an. The control signals of all first secondary-side switches S31, S32, ..., S3n connected in parallel are the same, and the control signals of all second secondary-side switches S41, S42, ..., S4n connected in parallel are the same.

[0106] When controller 12 receives all digital signals DT transmitted by integrated circuits 2a1, 2a2, ..., 2an, controller 12 performs an AND operation on the value of the same bit in all digital signals DT and synchronously controls the dead time in all integrated circuits based on the operation result. Taking the dead time (T3R) at the rising edge of the control signal (PWM3) of the first secondary-side switch as an example, its corresponding dead time adjustment instruction is (Bit0, Bit1). When (Bit0, Bit1) in all digital signals DT received by controller 12 contains three cases such as (1,1), (0,1), and (0,0), controller 12 performs an AND operation on all bits Bit0 to obtain a result of 0, and performs an AND operation on all bits Bit1 to obtain a result of 0. At this time, controller 12 adjusts the dead time at the rising edge of the control signal of the first secondary-side switch in all integrated circuits in the same way based on the case where (Bit0, Bit1) is (0,0) (i.e., increases the dead time, as shown in Table 2). Therefore, it can be seen that the controller 12 makes the same adjustment to the dead time of the parallel secondary-side switches, thereby simplifying control and effectively saving the resources required to adjust the dead time. In this embodiment, the specific method by which each integrated circuit generates and transmits the digital signal DT is the same as described above, and therefore will not be repeated here.

[0107] Taking the dead time (T3R) at the rising edge of the control signal (PWM3) of the first secondary-side switch as an example and referring to Table 2, if all digital signals DT received by controller 12 contain both (1,1) and (0,1) values ​​(Bit0, Bit1), the AND operation result is (0,1), and controller 12 will maintain the dead time duration. If all digital signals DT received by controller 12 contain only (1,1) values ​​(Bit0, Bit1), the AND operation result is (1,1), and controller 12 will reduce the dead time duration. Therefore, for any dead time adjustment command and its corresponding dead time in digital signal DT, the AND operation result of controller 12 on each bit will reflect the duration (state) of the smallest corresponding dead time in all integrated circuits.

[0108] Furthermore, if all non-integrated circuit switches in the converter are considered as first switches, and all integrated circuit switches are considered as second switches, the actual number of first and second switches is not limited to the two in the aforementioned embodiments; their numbers can be any positive integer, for example, one or more first and second switches. The specific circuit of the converter is also not limited to the above embodiments. When the converter includes multiple first switches, the integrated circuit includes multiple second switches corresponding to the multiple first switches. The control signals of the corresponding first and second switches are complementary and have a dead time. The sampling processing circuit samples the voltage on each second switch to obtain the duration of the dead time corresponding to each second switch, and generates a digital signal based on the duration of the dead time corresponding to all second switches. This digital signal is used to adjust the duration of the dead time corresponding to all second switches. The specific adjustment method is the same as described above and will not be repeated here.

[0109] In summary, this invention provides a dead-time adjustment device and a converter applicable to it. By sampling the voltage on the switching transistor in the integrated circuit, the duration of the dead time in the control signal of the switching transistor is obtained and a corresponding digital signal is generated. Thus, the duration of the dead time can be precisely controlled and adjusted based on the digital signal to reduce the loss caused by the dead time and improve the efficiency of the converter.

[0110] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A dead-zone adjustment device, characterized in that, Suitable for a converter including a first switching transistor, the dead-time adjustment device includes: A communication bus; An integrated circuit, electrically connected to the communication bus for communication, and comprising: A second switching transistor, wherein the control signal of the second switching transistor is complementary to the control signal of the first switching transistor and has a dead time; A sampling processing circuit samples the voltage across the second switching transistor to obtain the duration of the dead time, and generates a digital signal based on the duration of the dead time; and A bus control circuit includes at least one switch, and transmits the digital signal to the communication bus by turning the at least one switch on and off. as well as A controller is electrically connected to the communication bus for communication. The controller receives the digital signal from the bus control circuit through the communication bus. Before the communication bus transmits the digital signal, the controller performs communication timing alignment of the communication bus. The controller adjusts the duration of the dead time according to the received digital signal.

2. The dead-zone adjustment device as described in claim 1, characterized in that, When transmitting each bit of the digital signal on the communication bus, the controller first performs communication timing alignment of the communication bus.

3. The dead-zone adjustment device as described in claim 2, characterized in that, When transmitting each bit of the digital signal on the communication bus, the controller first pulls the signal in the communication bus low or high to perform communication timing alignment and enable the integrated circuit to know that communication is about to take place; The bus control circuit then transmits a high-level or low-level signal reflecting the bit to the communication bus; subsequently, the controller reads the high-level or low-level signal transmitted by the bus control circuit in the communication bus to determine the value of the corresponding bit.

4. The dead-zone adjustment device as described in claim 1, characterized in that, The bus control circuit also includes a pull-up resistor, the two ends of which are electrically connected to a power supply and the first terminal of the switch, respectively, and the second terminal of the switch is grounded; the bus control circuit transmits each bit value of the digital signal to the communication bus through the on and off states of the switch.

5. The dead-zone adjustment device as described in claim 4, characterized in that, When the value of this bit of the digital signal is logic 0, the switch is turned on, and the bus control circuit outputs a low level to the communication bus; when the value of this bit of the digital signal is logic 1, the switch is turned off, and the bus control circuit outputs a high level to the communication bus.

6. The dead-zone adjustment device as described in claim 1, characterized in that, The communication timing sequence in which the bus control circuit transmits the digital signal to the communication bus each time includes a first time period, a second time period, and a third time period in sequence. During the first time period, the controller pulls the signal in the communication bus low or high to perform communication timing alignment and inform the integrated circuit that communication is about to take place; During the second time period, the controller raises the corresponding signal in the communication bus to a high level or pulls it to a low level to achieve a delay; During this third time period, the bus control circuit first outputs the head check code, then sequentially outputs each bit in the digital signal, and finally outputs the tail check code. After receiving the header check code, the digital signal, and the tail check code through the communication bus, the controller first checks the header check code and the tail check code. If the check is correct, the controller determines that the received digital signal is valid and then adjusts the dead time duration according to the received digital signal. If the check is incorrect, the controller determines that the received digital signal is invalid and maintains the existing dead time duration.

7. The dead-zone adjustment device as described in claim 1, characterized in that, The dead time includes the dead time at the rising edge of the control signal of the second switch and the dead time at the falling edge of the control signal of the second switch. The digital signal includes multiple bits, each of which reflects the duration of the corresponding dead time.

8. The dead-zone adjustment device as described in claim 7, characterized in that, The dead-time adjustment device includes multiple integrated circuits, and multiple second switching transistors of the multiple integrated circuits are connected in parallel.

9. The dead-zone adjustment device as described in claim 8, characterized in that, When the controller receives multiple digital signals from the multiple integrated circuits simultaneously, the controller performs a bitwise AND operation on the corresponding bits of the multiple digital signals. For any bit in the digital signal and the duration of the dead time it reflects, the controller performs a bitwise AND operation on the bits of the multiple digital signals and adjusts the duration of the dead time in the control signals of the multiple second switches in the same way according to the operation result.

10. The dead-zone adjustment device as described in claim 9, characterized in that, For any bit in the digital signal and the duration of the dead time it reflects, the result of the AND operation performed by the controller reflects the duration of the minimum dead time among the control signals of the plurality of second switches.

11. The dead-zone adjustment device as described in claim 8, characterized in that, The multiple integrated circuits communicate with the controller simultaneously through the communication bus, and the control signals of the multiple second switching transistors connected in parallel in the multiple integrated circuits are the same.

12. The dead-zone adjustment device as claimed in claim 1, characterized in that, The sampling processing circuit includes a sampling circuit, a signal conversion circuit, and a comparison circuit that are electrically connected to each other. The sampling circuit samples the voltage on the second switch to generate a pulse signal that reflects the duration of the dead time. The signal conversion circuit converts the pulse signal into a voltage signal that reflects the duration of the dead time. The comparison circuit compares the voltage signal with a threshold to generate a digital signal. The controller controls the control signals of the first switch and the second switch according to the digital signal to adjust the duration of the dead time.

13. The dead-zone adjustment device as described in claim 12, characterized in that, The threshold includes an upper threshold and a lower threshold, with the upper threshold being greater than the lower threshold. When the voltage signal is less than the lower threshold, the controller increases the duration of the dead time. When the voltage signal is between the lower threshold and the upper threshold, the controller does not adjust the duration of the dead time, i.e., it maintains the current duration of the dead time. When the voltage signal is greater than the upper threshold, the controller decreases the duration of the dead time.

14. The dead-zone adjustment device as claimed in claim 1, characterized in that, The converter includes a plurality of first switching transistors, and the integrated circuit includes a plurality of second switching transistors corresponding to the plurality of first switching transistors. The control signals of the corresponding first switching transistors and the second switching transistors are complementary and have a dead time. The sampling processing circuit samples the voltage on each second switching transistor to obtain the duration of the dead time corresponding to each second switching transistor, and generates the digital signal according to the duration of the dead time corresponding to the plurality of second switching transistors. The controller adjusts the duration of the dead time corresponding to the plurality of second switching transistors according to the digital signal.

15. A converter, characterized in that, Include: The device has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, wherein the positive input terminal and the negative input terminal are used to receive an input signal, and the positive output terminal and the negative output terminal are used to output an output signal. A first switching transistor is electrically connected to the positive input terminal; as well as The dead-time adjustment device according to any one of claims 1 to 14, wherein the second switch of the integrated circuit is electrically connected to the negative output terminal, and the converter is used to convert the input signal into the output signal.

16. The converter as claimed in claim 15, characterized in that, The converter includes: The two first switching transistors are connected in series between the positive input terminal and the negative input terminal, wherein the first and second first switching transistors are respectively connected to the positive input terminal and the negative input terminal; Two input capacitors are connected in series between the positive and negative input terminals; and A transformer includes a primary winding and a secondary winding, wherein the first end of the primary winding is electrically connected to the connection point between the two first switching transistors, and the second end of the primary winding is electrically connected to the connection point between the two input capacitors. The integrated circuit includes two second switching transistors. The first second switching transistor is electrically connected between the first end of the secondary winding and the negative output terminal, and the second end of the secondary winding is electrically connected to the positive output terminal. The second second switching transistor is electrically connected between the third end of the secondary winding and the negative output terminal. The control signal of the first second switching transistor is complementary to the control signal of the first first switching transistor and has a dead time. The control signal of the second second switching transistor is complementary to the control signal of the second first switching transistor and also has a dead time. The sampling processing circuit samples the voltage on each of the second switches to obtain the duration of the dead time corresponding to each of the second switches, and generates the digital signal based on the duration of the dead time corresponding to the two second switches, wherein the digital signal is used to adjust the duration of the dead time corresponding to the two second switches.

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