A peak current mode boost circuit with constant peak current independent of duty cycle

Abstract

The application discloses a peak current mode BOOST circuit with peak current not changing with duty ratio, belonging to slope compensation recovery technology, and the peak current mode BOOST circuit is characterized by setting a slope compensation current circuit and a slope compensation current peak information circuit at a sampling node for controlling a pulse width modulation comparator switch, so that the slope compensation current peak can be offset under any load condition, thereby ensuring that the BOOST peak current is not affected by the slope compensation, and the effect that the BOOST converter peak current does not change with the duty ratio is realized.

Description

Technical Field

[0001] This invention relates to current loop slope compensation technology for BOOST converters, and in particular to a peak current-mode BOOST circuit in which the peak current does not change with the duty cycle. Background Technology

[0002] Figure 2 This is a schematic diagram of a traditional duty cycle modulation circuit with superimposed slope compensation. (Example) Figure 2 As shown, the traditional duty cycle modulation circuit with superimposed slope compensation includes a first PMOS transistor MP0 and a second PMOS transistor MP2 (with a mirror ratio of 1:1) with a common source and common gate. The source of MP2 is connected to the power supply voltage terminal VDD. The gate and drain of MP0 are interconnected and then connected to the drain of the first NMOS transistor MN1. The gate of MN1 is connected to the sawtooth wave voltage terminal VRAMP for generating the internal clock. The source of MN1 is connected to the first node A, which is grounded through the first resistor R1. The drain of MP2 is connected to the sampling node sum. The slope compensation current Islope flows from the drain of MP2 into sum. sum is connected to VDD through the current sampling terminal Ics of the lower transistor. The sampling current Ics of the BOOST lower transistor flows into the sampling node sum. sum is grounded through the third resistor R3. sum is connected to the pulse width modulation comparator. The positive input (+) and negative input (-) of the PWM_COMP amplifier are connected to the clamping node eaout, which is the output of the error amplifier EA. The output of the PWM_COMP amplifier is connected to the main flip signal terminal MAIN_TRIP (or the output main flip signal MAIN_TRIP). The positive input (+) of the error amplifier EA is connected to the reference voltage terminal VREF. The negative input (-) of the error amplifier EA is connected to the feedback voltage terminal FB. The clamping node eaout is connected to the source of the third PMOS transistor MP3 and the negative input (-) of the first operational amplifier AMP1. The positive input (+) of AMP1 is connected to the upper clamping voltage terminal Clamp_H. The output of AMP1 is connected to the gate of MP3. The drain of MP3 is grounded.

[0003] In peak current-mode boost converters, when the duty cycle is greater than 50%, slope compensation is needed in the current loop to eliminate subharmonic oscillations. However, adding slope compensation reduces the peak inductor current, resulting in a lower boost current limit. A common solution is to change the slope compensation gradient, transforming the fixed-slope compensation current into a segmented-slope compensation current; the larger the duty cycle, the larger the slope. This approach mitigates the reduction in maximum peak current caused by slope compensation, but it cannot completely eliminate it. Figure 2This diagram illustrates a traditional duty cycle modulation comparator circuit with superimposed slope compensation. The VRAMP generates a sawtooth wave with an internal clock, producing a current Islope with a fixed slope across resistor R1. This slope-compensated current Islope is superimposed on the sampling current Ics of the lower transistor via the mirror image of MP2, and converted into a sum-point voltage across R3. This sum-point voltage is compared with the output eaout of the error amplifier, thereby controlling the PWM comparator switch. Op-amps AMP1 and MP3 form an upper clamping circuit for eaout through negative feedback. When the load is light or medium, the eaout voltage is low and insufficient to turn on MP3, so the upper clamping circuit does not operate. As the load increases, the eaout voltage gradually rises. When the load increases to the point where the inductor current reaches its maximum peak current, MP3 turns on, and the upper clamping circuit begins to function. At this time, the negative feedback clamps the eaout voltage to the Clamp_H value. Only when the inductor current increases to satisfy (Ics + Islope) * R3 = Clamp_H does the PWM comparator flip and turn off the lower transistor. Analysis shows that the larger the duty cycle, the larger the slope compensation current Islope, which in turn results in a smaller effective maximum peak current Ics and a smaller effective current limit value for BOOST. Summary of the Invention

[0004] This invention addresses the defects or deficiencies in existing technologies by providing a peak current-mode BOOST circuit whose peak current does not change with the duty cycle.

[0005] The technical solution of the present invention is as follows:

[0006] A peak current-mode BOOST circuit whose peak current does not change with duty cycle is characterized by comprising a sampling node and a clamping node for controlling the switching of a pulse width modulation comparator. The sampling node has a first path connected to the positive input terminal of the pulse width modulation comparator, a second path connected to the power supply voltage terminal VDD through the current sampling terminal of the lower transistor, a third path connected to the slope compensation current circuit and the slope compensation current peak information circuit, and a fourth path grounded through a third resistor. The sampling current of the BOOST lower transistor flows into the sampling node, and the difference between the slope compensation current and the slope compensation current peak information flows into the sampling node. The clamping node is connected to the negative input terminal of the pulse width modulation comparator.

[0007] The slope compensation current peak information circuit includes a sample-and-hold circuit and a voltage-to-current conversion circuit. The sample-and-hold circuit is connected to the slope compensation current circuit, and the voltage-to-current conversion circuit is connected to the sampling node.

[0008] The ramp compensation current circuit includes a first PMOS transistor and a second PMOS transistor with common source and common gate. The source of the second PMOS transistor is connected to the power supply voltage terminal VDD, and the drain of the second PMOS transistor is connected to the sampling node. The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the first node, and the first node is grounded through the first resistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock.

[0009] The sample-and-hold circuit includes a first switch, one end of which is connected to the first node and the other end of which is connected to the second node. The second node is grounded through a first capacitor and the second path is connected to a fourth node through a second switch. The fourth node is grounded through a second capacitor and the second path is connected to the voltage-to-current circuit.

[0010] The voltage-to-current conversion circuit includes a second operational amplifier. The positive input terminal of the second operational amplifier is connected to the fourth node, and the negative input terminal of the second operational amplifier is connected to the fifth node. The fifth node has a first path grounded through a second resistor, a second path connected to the source of a second NMOS transistor, a gate of the second NMOS transistor connected to the output terminal of the second operational amplifier, and a drain of the second NMOS transistor connected to the sampling node.

[0011] Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2.

[0012] The clamping node has a first path connected to the output of the error amplifier, a second path connected to the negative input of the first operational amplifier and the source of the third PMOS transistor, the drain of the third PMOS transistor being grounded, the gate of the third PMOS transistor being connected to the output of the first operational amplifier, the positive input of the first operational amplifier being connected to the clamping voltage terminal, the positive input of the error amplifier being connected to the reference voltage terminal, and the negative input of the error amplifier being connected to the feedback voltage terminal.

[0013] Let the voltage of the sampling node be sum, the sampling current of the BOOST transistor be Ics, the slope compensation current be I_slope, the peak value of the slope compensation current be I_slope_DC, and the resistance of the third resistor be R3, then sum = (Ics + I_slope - Islope_DC) * R3.

[0014] The output of the pulse width modulation comparator is connected to the master flip signal terminal to output the master flip signal MAIN_TRIP.

[0015] The technical effects of this invention are as follows: This invention provides a peak current-mode BOOST circuit whose peak current does not change with the duty cycle. It belongs to the slope compensation recovery technology. By setting a slope compensation current circuit and a slope compensation current peak information circuit at the sampling node of the control pulse width modulation comparator switch, it is beneficial to cancel out the peak value of the slope compensation current under any load condition, thereby ensuring that any peak current of the BOOST is not affected by the slope compensation, and realizing the effect that any peak current of the BOOST converter does not change with the duty cycle.

[0016] The present invention has the following features: 1. By using a sample-and-hold circuit, the peak value of the slope compensation voltage is sampled and used as a DC current, which is then subtracted from the slope compensation current, thereby ensuring that the slope compensation will not affect the peak value of the inductor current under any DC load. 2. The upper clamping voltage of the error amplifier is a fixed clamping value, which does not change with the duty cycle.

[0017] The advantages of this invention compared to the prior art are: simple circuit structure, ingenious design, and the fact that the peak current of BOOST does not change with slope compensation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the structural principle of a peak current-mode BOOST circuit that implements the present invention, where the peak current does not change with the duty cycle.

[0019] Figure 2 This is a schematic diagram of a traditional duty cycle modulation circuit with superimposed slope compensation.

[0020] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; PWM_COMP - Pulse width modulation comparator; EA - Error amplifier; AMP1~AMP2 - First operational amplifier to second operational amplifier; MAIN_TRIP - Main flip signal terminal; sum - Sampling node; VREF - Reference voltage terminal; FB - Feedback voltage terminal; eaout - Clamping node; Clamp_H - Upper clamping voltage terminal; Ics - Lower transistor current sampling terminal or BOOST lower transistor sampling current (BOOST is the boost converter, and the lower transistor is also called the lower switching transistor); R1~R3 - First resistor to third resistor; C1~C2 - First capacitor to second capacitor; S1~S2 - First switch to second switch; I_slope - Slope compensation current; I_slope_DC - Slope compensation current peak information; MP0 - First PMOS transistor; MP2~MP3 - Second PMOS transistor to third PMOS transistor; MN0~MN1 - First NMOS transistor to second NMOS transistor; VRAMP - Internal clock generation sawtooth wave voltage terminal; A~B - First node to second node; D~E - Fourth node to fifth node; 1:1 - Mirror ratio. Detailed Implementation

[0021] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0022] Figure 1 This is a schematic diagram illustrating the structural principle of a peak current-mode BOOST circuit that implements the present invention, where the peak current does not change with the duty cycle. (Reference) Figure 1 As shown, a peak current-mode BOOST circuit with peak current independent of duty cycle includes a sampling node `sum` and a clamping node `eaout` that control the switching of a pulse width modulation comparator (PWM_COMP). The sampling node `sum` has a first path connected to the positive input (+) of the PWM_COMP, a second path connected to the power supply voltage terminal VDD via the lower transistor current sampling terminal `Ics`, a third path connected to both a slope compensation current circuit and a slope compensation current peak information circuit, and a fourth path grounded via a third resistor R3. The BOOST lower transistor sampling current `Ics` flows into the sampling node `sum`, and the difference between the slope compensation current `I_slope` and the slope compensation current peak information `I_slope_DC` flows into the sampling node `sum`. The clamping node `eaout` is connected to the negative input (-) of the PWM_COMP. The slope compensation current peak information circuit includes a sample-and-hold circuit and a voltage-to-current conversion circuit. The sample-and-hold circuit is connected to the slope compensation current circuit, and the voltage-to-current conversion circuit is connected to the sampling node `sum`.

[0023] The slope compensation current circuit includes a first PMOS transistor MP0 and a second PMOS transistor MP2 with a common source and common gate. The source of the second PMOS transistor MP2 is connected to the power supply voltage terminal VDD, and the drain of the second PMOS transistor MP2 is connected to the sampling node sum. The gate and drain of the first PMOS transistor MP0 are interconnected and connected to the drain of the first NMOS transistor MN0. The source of the first NMOS transistor MN0 is connected to the first node A. The first node A is grounded through the first resistor R1. The gate of the first NMOS transistor MN0 is connected to the sawtooth wave voltage terminal VRAMP generated by the internal clock. The sample-and-hold circuit includes a first switch S1. One end of the first switch S1 is connected to the first node A, and the other end is connected to the second node B. The second node B is grounded through the first capacitor C1 and the second path is connected to the fourth node D through the second switch S2. The fourth node D is grounded through the second capacitor C2 and the second path is connected to the voltage-to-current circuit. The voltage-to-current conversion circuit includes a second operational amplifier AMP2. The positive input (+) of the second operational amplifier AMP2 is connected to the fourth node D, and the negative input (-) of the second operational amplifier AMP2 is connected to the fifth node E. The fifth node E is grounded through a second resistor R2 in the first path and connected to the source of a second NMOS transistor MN1 in the second path. The gate of the second NMOS transistor MN1 is connected to the output of the second operational amplifier AMP2, and the drain of the second NMOS transistor MN1 is connected to the sampling node sum. Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2.

[0024] The clamping node eaout has its first path connected to the output of the error amplifier EA, and its second path connected to the negative input (-) of the first operational amplifier AMP1 and the source of the third PMOS transistor MP3. The drain of the third PMOS transistor MP3 is grounded, and the gate of the third PMOS transistor MP3 is connected to the output of the first operational amplifier AMP1. The positive input (+) of the first operational amplifier AMP1 is connected to the clamping voltage terminal Clamp_H. The positive input (+) of the error amplifier EA is connected to the reference voltage terminal VREF, and the negative input (-) of the error amplifier EA is connected to the feedback voltage terminal FB.

[0025] Let the voltage of the sampling node be sum, the sampling current of the BOOST transistor be Ics, the slope compensation current be I_slope, the peak value of the slope compensation current be I_slope_DC, and the resistance of the third resistor be R3. Then sum = (Ics + I_slope - I_slope_DC) * R3. The output of the pulse width modulation comparator PWM_COMP is connected to the main switching signal terminal to output the main switching signal MAIN_TRIP.

[0026] Peak current-mode BOOST converters are widely used in BOOST converter architectures due to their relatively simple loop compensation method. When the duty cycle is greater than 50%, slope compensation is required in the current loop to eliminate subharmonic oscillations. However, after adding slope compensation, the peak inductor current decreases, resulting in a lower BOOST load-carrying capacity. Therefore, this invention employs slope compensation recovery circuit technology to cancel out the peak current under any load condition, ensuring that the peak current of the BOOST converter is unaffected by slope compensation under any load, achieving the effect that the peak current of the BOOST converter does not change with the duty cycle. This invention includes using a sample-and-hold circuit to sample the peak value of the slope compensation voltage and use it as a DC current, subtracting it from the slope compensation current, thus ensuring that slope compensation does not affect the peak value of the inductor current under any DC load. The upper clamping voltage of the error amplifier is a fixed clamping value that does not change with the duty cycle.

[0027] The circuit designed in this invention is as follows: Figure 1 As shown, by canceling the peak information of the slope compensation, the peak current under any load does not change with the duty cycle. The resistors R1 and R2, switches S1 and S2, and capacitors C1 and C2 constitute a sample-and-hold circuit. During the conduction period of the BOOST transistor, switch S2 is open and S1 is closed, and capacitor C1 samples the slope compensation voltage. During the conduction period of the BOOST transistor, switch S1 is open and S2 is closed, and the voltage sampled by capacitor C1 is transferred and held on capacitor C2. In this way, the peak information of the slope compensation current is transmitted from point A to point E as a DC current. Furthermore, the voltage is converted to current by the buffer composed of AMP2, MN1, and R2. The peak value of the DC slope compensation is subtracted from the slope compensation current I_slope at the sum point. This results in the pure slope compensation amount, after removing the peak current information, being superimposed on resistor R3. This pure slope compensation amount is then compared with eaout at the PWM comparator. Since the voltage expression at the sum point is now: sum = (Ics + I_slope - Islope_DC) * R3, it is completely unrelated to the peak value of the slope compensation. It can be seen that after adopting the slope recovery technology in this design, the slope compensation current will not affect the peak value of the inductor current under any load and any duty cycle. Therefore, it is ensured that the peak current of BOOST does not change with the duty cycle.

[0028] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A peak current-mode BOOST circuit whose peak current does not change with duty cycle, characterized in that, The device includes a sampling node and a clamping node for controlling the switching of a pulse width modulation comparator. The sampling node has a first path connected to the positive input terminal of the pulse width modulation comparator, a second path connected to the power supply voltage terminal VDD through the current sampling terminal of the lower transistor, a third path connected to the ramp compensation current circuit and the ramp compensation current peak information circuit, and a fourth path grounded through a third resistor. The sampling current of the BOOST lower transistor flows into the sampling node, and the difference between the ramp compensation current and the ramp compensation current peak information flows into the sampling node. The clamping node is connected to the negative input terminal of the pulse width modulation comparator. The slope compensation current peak information circuit includes a sample-and-hold circuit and a voltage-to-current circuit. The sample-and-hold circuit is connected to the slope compensation current circuit, and the voltage-to-current circuit is connected to the sampling node. The ramp compensation current circuit includes a first PMOS transistor and a second PMOS transistor with common source and common gate. The source of the second PMOS transistor is connected to the power supply voltage terminal VDD, and the drain of the second PMOS transistor is connected to the sampling node. The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the first node. The first node is grounded through the first resistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock. The sample-and-hold circuit includes a first switch, one end of which is connected to the first node and the other end of which is connected to the second node. The second node is grounded through a first capacitor and the second path is connected to a fourth node through a second switch. The fourth node is grounded through a second capacitor and the second path is connected to the voltage-to-current circuit. The voltage-to-current conversion circuit includes a second operational amplifier. The positive input terminal of the second operational amplifier is connected to the fourth node, and the negative input terminal of the second operational amplifier is connected to the fifth node. The fifth node has a first path grounded through a second resistor, a second path connected to the source of a second NMOS transistor, a gate of the second NMOS transistor connected to the output terminal of the second operational amplifier, and a drain of the second NMOS transistor connected to the sampling node.

2. The peak current-mode BOOST circuit with peak current independent of duty cycle as described in claim 1, characterized in that, Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2.

3. The peak current-mode BOOST circuit with peak current independent of duty cycle according to claim 2, characterized in that, The clamping node has a first path connected to the output of the error amplifier, a second path connected to the negative input of the first operational amplifier and the source of the third PMOS transistor, the drain of the third PMOS transistor being grounded, the gate of the third PMOS transistor being connected to the output of the first operational amplifier, the positive input of the first operational amplifier being connected to the clamping voltage terminal, the positive input of the error amplifier being connected to the reference voltage terminal, and the negative input of the error amplifier being connected to the feedback voltage terminal.

4. The peak current-mode BOOST circuit according to claim 3, wherein the peak current does not change with the duty cycle, is characterized in that, Let the voltage of the sampling node be sum, the sampling current of the BOOST transistor be Ics, the slope compensation current be I_slope, the peak value of the slope compensation current be I_slope_DC, and the resistance of the third resistor be R3, then sum = (Ics + I_slope - I_slope_DC). R3.

5. The peak current-mode BOOST circuit with peak current independent of duty cycle according to claim 1, characterized in that, The output of the pulse width modulation comparator is connected to the master flip signal terminal to output the master flip signal MAIN_TRIP.

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