Flyback converter and method of controlling the same

Abstract

This invention discloses a flyback converter and its control method. The flyback converter includes a transformer, a synchronous rectifier switch, and a synchronous rectifier controller. The transformer includes a secondary coil. The synchronous rectifier switch is coupled to the secondary coil and the synchronous rectifier controller to output the voltage difference across the switch and receive a control voltage. The control method includes the synchronous rectifier controller detecting a fast falling edge of the voltage difference across the switch to generate a fast falling edge signal, generating an envelope signal based on the voltage difference across the switch, generating a time length control signal based on the voltage difference across the switch and the envelope signal, generating a blank time signal based on the voltage difference across the switch and the time length control signal, and performing logical operations on the blank time signal and the fast falling edge signal to generate a control voltage.

Description

Technical Field

[0001] This invention relates to power supplies, and more particularly to a flyback converter and its control method. Background Technology

[0002] Flyback converters offer advantages such as high conversion efficiency and low losses. Existing flyback converters regulate output voltage or current by controlling a main switch located on the primary side of the transformer. In current technology, replacing the original diodes with a secondary-side rectifier switch for synchronous rectification on the secondary side of the flyback converter significantly reduces rectification losses, thereby improving power conversion efficiency.

[0003] The existing control strategy for the secondary-side rectifier switch works by turning off the main switch with a control signal, causing the drain voltage of the main switch to rise. This releases the energy stored in the transformer to the secondary side, thereby decreasing the voltage difference Vds between the drain and source terminals of the secondary-side rectifier switch. The controller detects this decrease in Vds to trigger the secondary-side rectifier switch to turn on. However, when the flyback converter operates in discontinuous conduction mode, after the energy in the transformer has been completely released to the secondary side, the voltage difference Vds across the secondary-side rectifier switch will resonate and oscillate. The controller may then misdetect the decreasing waveform of the resonant voltage difference Vds and erroneously trigger the secondary-side rectifier switch to turn on.

[0004] As disclosed in patent applications TW110124942 and CN202110688325.3: (1) a shorter blanking time is given to the high rising slope of the voltage difference Vds across the rectifier switch at the instant the main switch is turned on; (2) a longer blanking time is given to the gentler rising slope of the resonant rising waveform of the voltage difference Vds across the rectifier switch when both the main switch and the rectifier switch are turned off. By applying blanking times of different lengths according to the rising slope of different waveforms, the falling waveform during the resonant oscillation of the voltage difference Vds across the switch can be blocked, thus avoiding the accidental triggering of the secondary rectifier switch to turn on. This design can correctly handle most of the resonant oscillation waveform signals of the voltage difference Vds across the rectifier switch. However, when the rising edge of the resonant waveform and the instant the main switch is turned on are close in time, it is difficult to obtain an accurate rising slope, so further improvement is needed. Summary of the Invention

[0005] This invention provides a synchronous rectification control method applicable to flyback converters. The flyback converter includes a transformer, a main switch, a synchronous rectification switch, and a synchronous rectification controller. The transformer includes a primary coil and a secondary coil, with the primary coil coupled to the main switch. The synchronous rectification switch includes a first terminal coupled to the secondary coil and the synchronous rectification controller, a second terminal coupled to a power output port and the synchronous rectification controller, a voltage difference between the first and second terminals, and a control terminal coupled to the synchronous rectification controller to receive a control voltage from the controller to change the impedance between the first and second terminals. The synchronous rectification controller includes a signal edge detection circuit, a blanking time circuit, and an output circuit. The control method includes a signal edge detection circuit that detects the fast falling edge of the voltage difference across the switch to generate a fast falling edge signal; a blanking time circuit that detects the peak of the voltage difference across the switch to generate an envelope signal; a blanking time circuit that generates a time length control signal based on the voltage difference across the switch and the envelope signal; a time length control signal that indicates the difference between the envelope signal and the voltage difference across the switch exceeds a predetermined threshold; a blanking time circuit that generates a blanking time signal based on the voltage difference across the switch and the time length control signal; and an output circuit that performs logical operations based on the blanking time signal and the fast falling edge signal to generate an output signal, thereby generating a control voltage.

[0006] This invention provides another flyback converter, including a transformer, a main switch, a synchronous rectifier switch, and a synchronous rectifier controller. The transformer includes a primary coil with a first terminal for receiving an input signal and a second terminal; and a secondary coil with a first terminal and a second terminal. The main switch is coupled to the second terminal of the primary coil. The synchronous rectifier switch includes a first terminal coupled to the second terminal of the secondary coil and the synchronous rectifier controller for outputting the voltage difference across the switch; a second terminal coupled to a power output port and the synchronous rectifier controller; and a control terminal coupled to the synchronous rectifier controller for receiving a control voltage to generate an output voltage. The synchronous rectifier controller is coupled to the first terminal and the control terminal of the synchronous rectifier switch and includes a signal edge detection circuit, a blanking time circuit, and an output circuit. The signal edge detection circuit is coupled to the first terminal of the synchronous rectifier switch for detecting a fast falling edge of the voltage difference across the switch to generate a fast falling edge signal. The blank time circuit is coupled to the first terminal of the synchronous rectifier switch. It detects the voltage difference across the switch to generate an envelope signal by detecting the peak. Based on the voltage difference and the envelope signal, it generates a time length control signal and a blank time signal. The time length control signal indicates that the difference between the envelope signal and the voltage difference across the switch exceeds a predetermined threshold. The output circuit is coupled to the signal edge detection circuit and the blank time circuit. It performs logical operations on the blank time signal and the fast falling edge signal to generate an output signal, thereby producing a control voltage. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a flyback converter according to an embodiment of the present invention.

[0008] Figure 2 for Figure 1 A schematic diagram of a synchronous rectifier controller.

[0009] Figure 3 show Figure 2 The waveform of the signal along the detection circuit.

[0010] Figure 4 for Figure 2 The waveform diagram of the synchronous rectifier controller in the circuit.

[0011] Figure 5 for Figure 1 A schematic diagram of another blank time circuit.

[0012] Figure 6 for Figure 5 Waveform diagram of the blank time circuit in the image.

[0013] Figure 7 for Figure 5 The circuit diagram of the timer in the image.

[0014] Figure 8 for Figure 5 The circuit diagram of the envelope detector in the image.

[0015] Figure 9 for Figure 1 A flowchart of a control method for a flyback converter in a computer.

[0016] Explanation of reference numerals in the attached figures:

[0017] 1: Flyback converter

[0018] 12: Transformer

[0019] 14: Pulse Width Modulation Controller

[0020] 16: Synchronous Rectifier Controller

[0021] 160: Signal edge detection circuit

[0022] 162: Blank Time Circuit

[0023] 164: Output Circuit

[0024] 181, 182: Power output ports

[0025] 200: Filter

[0026] 62,202,CP: Comparator

[0027] 64: Comparator Circuit

[0028] 204: Trigger

[0029] 61,210: Envelope Detector

[0030] 60,212: Voltage-to-current converter

[0031] 68,214: Timer

[0032] 69,216: Limiting circuit

[0033] 218: Inverter

[0034] 66,203: AND gate

[0035] 206: Voltage Regulator Control Circuit

[0036] cmp, cmp': Comparison results

[0037] cmp1, cmp2: Digital signals

[0038] Cout, C1, Cs: Capacitors

[0039] CV: Variable Capacitor

[0040] D1 to D3: Diodes

[0041] F1 to F3: Rising to the top platform

[0042] ids: Current flowing through

[0043] iev: Envelope signal

[0044] isource: Price surge signal

[0045] ith: critical current

[0046] Isrc: Controlled Current Source

[0047] SW: Switching device

[0048] P11 to P13, P21 to P23: Rising Top Platform

[0049] Q: Output terminal

[0050] Q1: Transistor

[0051] R1 to R5: Resistors

[0052] RV: Variable resistor

[0053] R,S: Input terminals

[0054] Sb: Blank Time Signal

[0055] Sbr: Reverse Blank Time Signal

[0056] Sbl: Time length control signal

[0057] Sm: Main switch

[0058] Spwm: Pulse Width Modulation Signal

[0059] Srst: Reset signal

[0060] SSR: Synchronous Rectifier Switch

[0061] Sf: Fast falling edge signal

[0062] Sgt: Output signal

[0063] SWr: Reset switch

[0064] Sdet: Enable signal

[0065] t1 to t24: Time

[0066] Tbl11 to Tbl13, Tbl21 to Tbl23: Long pulses

[0067] Tbs1 to Tbs3: Short pulses

[0068] Tchg, Tchg1 to Tchg3: Energy storage period

[0069] Tdis, Tdis1, Tdis2: Energy release period

[0070] Tres, Tres1, Tres2: Resonance period

[0071] U1, U2: Operational amplifiers

[0072] Vc: Control voltage

[0073] Vcap, Vres: Adjustment signals

[0074] Vd: Drain voltage

[0075] VDD: Power supply terminal

[0076] Vds: Voltage difference across the switch

[0077] Vev: Envelope signal

[0078] VR: Reference Potential

[0079] VHPF: Voltage difference across the switch after filtering

[0080] Vin: Input signal

[0081] VL, VL1, VL2: Critical Levels

[0082] Vout: Output signal

[0083] Voff: Reset voltage

[0084] Vs: Source voltage

[0085] Vth: Critical Voltage

[0086] VSS1, VSS2: Grounding terminals

[0087] Wp: Primary coil

[0088] Ws: Secondary coil

[0089] 1000: Control Method

[0090] S1002 to S1010: Steps Detailed Implementation

[0091] Figure 1 This is a schematic diagram of a flyback converter 1 according to an embodiment of the present invention. The flyback converter 1 can receive an input signal Vin to generate an output signal Vout. The input signal Vin and the output signal Vout can be DC voltages. The input signal Vin can be provided by a rectifier or other DC power supply. The output signal Vout can be less than the input signal Vin.

[0092] The flyback converter 1 includes a transformer 12, a main switch Sm, a pulse width modulation (PWM) controller 14, a synchronous rectifier switch Ssr, a synchronous rectifier controller 16, and a capacitor Cout. The transformer 12 includes a primary coil Wp and a secondary coil Ws. The primary coil Wp includes a first terminal for receiving the input signal Vin and a second terminal. The secondary coil Ws includes a first terminal and a second terminal. The main switch Sm includes a first terminal coupled to the second terminal of the primary coil Wp; a second terminal coupled to ground VSS1; and a control terminal coupled to the PWM controller 14. The synchronous rectifier switch Ssr includes a first terminal coupled to the second terminal of the secondary coil Ws and the synchronous rectifier controller 16; a second terminal coupled to either the high-voltage terminal or the ground terminal of the power output port 18 of the synchronous rectifier controller 16; and a control terminal coupled to the synchronous rectifier controller 16 to receive a control voltage Vc to generate an output voltage Vout. Capacitor Cout includes a first terminal coupled to the high-voltage terminal of power output port 18; and a second terminal coupled to the ground terminal of power output port 18. The ground terminal of power output port 18 can be coupled to ground terminal VSS2. Ground terminals VSS1 and VSS2 can be separate and can each provide a ground voltage. The main switch Sm and the synchronous rectifier switch Ssr can be implemented by transistors, such as N-type metal oxide semiconductor field-effect transistors (MOSFETs).

[0093] The pulse width modulation controller 14 can provide a pulse width modulation signal Spwm to the main switch Sm to selectively turn the main switch Sm on or off, thereby storing and transferring energy. The synchronous rectification controller 16 can provide a control voltage Vc to the synchronous rectification switch Ssr to selectively turn the synchronous rectification switch Ssr on or off, thereby charging and discharging the capacitor Cout to generate an output signal Vout. The control voltage Vc can be generated based on the voltage difference Vds across the synchronous rectification switch Ssr. For example, the synchronous rectification controller 16 can turn on the synchronous rectification switch by detecting the slope and envelope of the voltage difference Vds across the switch, so that the synchronous rectification switch turns on when the transformer releases energy to the secondary side; when the voltage difference Vds across the switch rises above a threshold, the synchronous rectification switch turns off, so that the synchronous rectification switch turns off after the energy release is complete. The polarity of the primary coil Wp and the secondary coil Ws of the transformer 12 can be opposite. The turns ratio of the primary coil Wp and the secondary coil Ws can be P:1, where P is a positive number. In some embodiments, P may be greater than 1, and transformer 12 may be a step-down transformer. The level of the output signal Vout may be related to the level of the input signal Vin, the duty cycle of the pulse width modulation signal Spwm, and the turns ratio.

[0094] The operating cycle of the flyback converter 1 can include an energy storage period, an energy release period, and a resonance period. During the energy storage period, the pulse width modulation controller 14 can turn on the main switch Sm, the primary coil Wp can store energy, and the synchronous rectification controller 16 can turn off the synchronous rectification switch Ssr. During the energy release period, the pulse width modulation controller 14 can turn off the main switch Sm, energy can be transferred to the secondary coil Ws, and the synchronous rectification controller 16 can turn on the synchronous rectification switch Ssr. When the flyback converter 1 operates in discontinuous-conduction mode (DCM), during the resonance period, the pulse width modulation controller 14 can turn off the main switch Sm, and the synchronous rectification controller 16 can turn off the synchronous rectification switch Ssr.

[0095] The synchronous rectification controller 16 can obtain the drain voltage Vd from the first terminal of the synchronous rectification switch Ssr and the source voltage Vs from the second terminal of the synchronous rectification switch Ssr, thereby generating a voltage difference Vds between the first and second terminals of the synchronous rectification switch Ssr. The synchronous rectification controller 16 can detect the slope and envelope of the voltage difference Vds across the switch to turn on the synchronous rectification switch Ssr at the correct time.

[0096] The synchronous rectification controller 16 may include a signal edge detection circuit 160, a blanking time circuit 162, and an output circuit 164. The signal edge detection circuit 160 and the blanking time circuit 162 may be coupled to the output circuit 164. The signal edge detection circuit 160 can detect the rapid falling edge of the voltage difference Vds across the switch to generate a rapid falling edge signal Sf. During the power release period of the flyback converter 1, once the main switch Sm is turned off, the voltage difference Vds across the switch drops rapidly; while during resonance, the voltage difference Vds across the switch resonates, and the resonance may decrease gradually. The signal edge detection circuit 160 can detect the slope of the voltage difference Vds across the switch to distinguish between the rapid falling edge and the falling edge of the resonant voltage difference Vds. Once the slope of the falling edge of the voltage difference Vds across the switch is detected to exceed a critical level, the signal edge detection circuit 160 can generate a pulse of the rapid falling edge signal Sf.

[0097] The blanking time circuit 162 can set the blanking time of the synchronous rectifier switch Ssr to prevent the synchronous rectifier controller 16 from mistakenly turning on the synchronous rectifier switch Ssr at an incorrect time. During the blanking time, even if a fast falling edge signal Sf appears, the synchronous rectifier switch Ssr cannot be turned on. During the resonance period of the flyback converter 1, the blanking time circuit 162 can set a longer blanking time Tbl to block the falling edge of the resonant waveform for a longer period of time, so as to prevent the synchronous rectifier switch Ssr from being mistakenly turned on. During energy storage, since the conduction period of the main switch Sm must be longer than the blanking time, and it is close to the fast falling edge of the voltage difference Vds across the switch where the synchronous rectifier switch Ssr should be turned on, the blanking time circuit 162 can set a shorter blanking time Tbs, thereby shortening the lower limit of the conduction period of the main switch Sm, and thus allowing the main switch Sm to have a higher switching frequency. The blanking time circuit 162 can detect the peak based on the voltage difference Vds across the switch to generate an envelope signal, generate a time length control signal based on the voltage difference Vds and the envelope signal, and generate a blanking time signal Sb based on the voltage difference Vds and the time length control signal. The blanking time signal Sb can be an active low signal, having a low logic level when enabled and a high logic level when disabled. Different time length control signals will exist depending on the magnitude of the difference between the envelope signal and the voltage difference Vds across the switch. For example, when the difference between the envelope signal and the voltage difference Vds across the switch is less than a predetermined threshold, the flyback converter 1 is in the energy storage period, and the time length control signal corresponds to a shorter blanking time. When the difference between the envelope signal and the voltage difference Vds across the switch exceeds the predetermined threshold, the flyback converter 1 is in the resonance period, and the time length control signal corresponds to a longer blanking time.

[0098] The output circuit 164 can generate a control voltage Vc by performing logical operations and voltage regulation control based on the blank time signal Sb and the fast falling edge signal Sf, and then control the synchronous rectifier switch Ssr through the driver circuit. The logical operation may include AND operation, but is not limited to it. In some embodiments, when the blank time signal Sb is enabled to a low logic level, the output signal Sgt will remain at a low logic level even if a fast falling edge signal Sf occurs, based on the result of the AND operation. When the blank time signal Sb is disabled, the output circuit 164 can generate an output signal based on the fast falling edge signal Sf. For example, when (1) the blank time signal Sb is at a high logic level, and (2) the output circuit 164 receives a pulse of the fast falling edge signal Sf, the output signal Sgt will be set to a high logic level, thereby setting the control voltage Vc to the enabled state.

[0099] Although Figure 1The synchronous rectifier switch Ssr is set on the low side of the secondary coil WS. The synchronous rectifier switch Ssr can also be set on the high side of the secondary coil WS. Those skilled in the art can adjust the opening conditions of the synchronous rectifier switch Ssr according to the technical principles of this invention.

[0100] Figure 2 This is a schematic diagram of a synchronous rectifier controller 16 for a flyback converter 1. The signal edge detection circuit 160 of the synchronous rectifier controller 16 includes a filter 200 and a comparator 202 coupled in sequence. The filter 200 is further coupled to the first terminal of the synchronous rectifier switch Ssr to receive the voltage difference Vds across the switch.

[0101] Filter 200 can be a high-pass filter to filter the voltage difference Vds across the switch to generate a filtered voltage difference VHPF across the switch. Filter 200 may include a variable capacitor CV and variable resistors RV+ and RV-. The variable capacitor CV includes a first terminal for receiving the voltage difference Vds across the switch and a second terminal. The variable resistor RV+ includes a first terminal coupled to the second terminal of the variable capacitor CV and a second terminal coupled to ground V-. The variable resistor RV- includes a first terminal coupled to the second terminal of the variable capacitor CV and a second terminal coupled to the power supply terminal V+. The voltage at the power supply terminal V+ may exceed the voltage at the power supply terminal V-, for example, the voltage at the power supply terminal V+ may be 3.3V, and the voltage at the power supply terminal V- may be 0V. The signal edge detection circuit 160 can adjust the capacitor adjustment signal to control the capacitance value of the variable capacitor CV, adjust the first resistor adjustment signal to control the resistance value of the variable resistor RV+, and adjust the second resistor adjustment signal to control the resistance value of the variable resistor RV-. The cutoff frequency f of filter 200 can be equal to the reciprocal of the product of the constant 2π, the resistance value R1 of variable resistor RV+, and the capacitance value C of variable capacitor CV (f = 1 / (2πR1C)). When flyback converter 1 is powered on, the signal edge detection circuit 160 can adjust the resistance values ​​of variable resistor RV+ and RV- and the capacitance value of variable capacitor CV so that the cutoff frequency f exceeds the resonant frequency of the voltage difference Vds across the switch and is less than the frequency of the fast falling edge of the voltage difference Vds across the switch. Therefore, filter 200 can filter out or significantly reduce the resonance and retain or slightly reduce the fast falling edge to generate the filtered voltage difference VHPF across the switch. In some embodiments, the synchronous rectifier controller 16 can be connected to an adjustable resistor or adjustable capacitor outside the chip via pins; when the flyback converter 1 is shipped from the factory, the cutoff frequency f of the filter 200 is adjusted by changing the resistance or capacitance value of the external resistor or capacitor, so that the high-pass filter 200 satisfies: (1) it can allow the fast falling edge of the voltage difference Vds across the switch to pass effectively and change the output of the subsequent logic circuit, and (2) it filters out most of the waveforms of the voltage difference Vds across the switch that fall slowly without affecting the output of the subsequent logic circuit.

[0102] Comparator 202 compares the voltage difference VHPF across the filtered switch with the critical level VL to generate a fast falling edge signal Sf. Comparator 202 includes an inverting input for receiving the voltage difference VHPF across the filtered switch; a non-inverting input for receiving the critical level VL; and an output for outputting the fast falling edge signal Sf. When the voltage difference VHPF across the filtered switch is less than the critical level VL, comparator 202 outputs a high logic level as the fast falling edge signal Sf to indicate that a fast falling edge has been detected; when the voltage difference VHPF across the filtered switch is not lower than the critical level VL, comparator 202 outputs a low logic level as the fast falling edge signal Sf, indicating that a fast falling edge has not been detected.

[0103] Figure 3 show Figure 2 The waveform diagram of the signal edge detection circuit 160 includes the voltage difference Vds across the switch, the filtered voltage difference VHPF across the switch, the waveform of the fast falling edge signal Sf, and the critical levels VL1 and VL2. The critical level VL1 is greater than the critical level VL2. Figure 3 The display shows the time intervals from t1 to t12, where the period between t1 and t3 is the energy release period Tdis, the period between t3 and t4 is the energy storage period Tchg, the period between t4 and t6 is another energy release period Tdis, and the period between t6 and t12 is the resonance period Tres.

[0104] The signal edge detection circuit 160 can set the critical level LV of comparator 202 to either critical level VL1 or VL2 to detect fast falling edges. The following explanation focuses on detecting fast falling edges using the critical level VL2. At time t1, a fast falling edge occurs in the voltage difference Vds across the switch. After filtering, the voltage difference VHPF across the switch includes a slightly weakened fast falling edge. Between times t1 and t2, since the filtered voltage difference VHPF across the switch is less than the critical level VL2, the fast falling edge signal Sf will have a high logic level pulse. Between times t2 and t4, since the filtered voltage difference VHPF across the switch is greater than the critical level VL2, the fast falling edge signal Sf is set to a low logic level. At time t4, a fast falling edge occurs again in the voltage difference Vds across the switch. After filtering, the voltage difference VHPF across the switch includes a slightly weakened fast falling edge. Between times t4 and t5, because the voltage difference VHPF across the filtered switch is less than the critical level VL2, the fast falling edge signal Sf will exhibit a high logic level pulse. After time t5, because the voltage difference VHPF across the filtered switch is greater than the critical level VL2, the fast falling edge signal Sf is set to a low logic level. At time t6, the resonance period Tres begins, and the voltage difference Vds across the switch resonates. Although negative pulses appear in the voltage difference VHPF across the filtered switch between times t7 and t8, between times t9 and t10, and at time t11, the voltage difference VHPF across the filtered switch is still greater than the critical level VL2. Therefore, the falling edges of these three resonant waves will not change the low logic level of the fast falling edge signal Sf. Therefore, comparator 202, using the critical level VL2, will correctly detect the fast falling edge and ignore the resonant falling edge.

[0105] If the critical level VL1 is used to detect the fast falling edge, the fast falling edge signal Sf' between times t1 and t7 will be the same as the fast falling edge signal Sf. However, between t7 and t8, between t9 and t10, and at time t11, because the voltage difference VHPF across the filtered switch is less than the critical level VL1, the fast falling edge signal Sf' will exhibit a high logic level pulse. Between t8 and t9, between t10 and t11, and after time t11, because the voltage difference VHPF across the filtered switch is greater than the critical level VL1, the fast falling edge signal Sf' is set to a low logic level. If comparator 202 uses the critical level VL1, it may falsely detect the falling edge of resonance and incorrectly turn on the synchronous rectifier switch. Therefore, when manufacturing the flyback converter 1, it is preferable to set the critical level VL of the comparator 202 of the signal edge detection circuit 160 to the critical level VL2, or to set the resistance value R and capacitance value C of the filter 200 so that the amplitude of the voltage difference VHPF across the filtered switch corresponding to all resonant valleys is attenuated to a level higher than the critical level VL1.

[0106] refer to Figure 2 The blanking time circuit 162 includes an envelope detector 210, a voltage-to-current converter 212, a timer 214, a limiting circuit 216, and an inverter 218, sequentially coupled. The envelope detector 210 and the voltage-to-current converter 212 are further coupled to the first terminal of the synchronous rectifier switch Ssr to receive the voltage difference Vds across the switch. The timer 214 is further coupled to the output terminal of the filter 200 to receive the filtered voltage difference VHPF across the switch.

[0107] Envelope detector 210 can be a voltage envelope detector, detecting the peak of the voltage difference Vds across the switch to generate the envelope signal Vev of the voltage difference Vds across the switch. Voltage-to-current converter 212 can be a transconductance operational amplifier, generating a difference current (gm*(Vev-Vds)) as a time length control signal Sbl based on the difference between the envelope signal Vev and the voltage difference Vds across the switch (Vev-Vds), where gm is the transconductance value. Since the difference between the envelope signal Vev and the voltage difference Vds across the switch (Vev-Vds) during resonance... Figure 4 The difference between P11, P12, P13, P21, P22, and P23 will be greater than the difference (Vev-Vds) during the energy storage period. Figure 4 (F1, F2, F3 time periods), therefore, according to the magnitude of the difference (Vev-Vds), the time length control signal Sbl during the resonance period will be greater than the time length control signal Sbl during the energy storage period.

[0108] When the voltage difference VHPF across the filtered switch rises above the positive threshold voltage, it can be considered that the rising edge of the voltage difference Vds across the switch has been detected, triggering timer 214 to start timing. Timer 214 can generate a reverse blank time signal Sbr based on the time length control signal Sbl. When the time length control signal Sbl is small, timer 214 can generate a short pulse in the reverse blank time signal Sbr; when the time length control signal Sbl is large, timer 214 can generate a longer pulse in the reverse blank time signal Sbr. When the voltage difference VHPF across the filtered switch is less than the positive threshold voltage, it can be considered that the rising edge of the voltage difference Vds across the switch has not yet been detected, so timer 214 can be reset without generating a pulse. Because the positive and negative slopes of the resonant waveform are close, the threshold voltage can, for example, be selected to have the same absolute value as the negative threshold level VL, but changed to a positive value.

[0109] Limiting circuit 216 can limit the inverted blank time signal Sbr within a predetermined range, and inverter 218 can invert the inverted blank time signal Sbr to generate a blank time signal Sb. The predetermined range can be between the upper limit pulse length and the lower limit pulse length, for example, 30% to 90% of the expected resonant period.

[0110] The output circuit 164 includes an AND gate 203, a flip-flop 204, and a voltage regulator control circuit 206. The AND gate 203 includes a first terminal coupled to the output of the signal edge detection circuit 160 to receive the fast falling edge signal Sf; a second terminal coupled to the output of the inverter 218 to receive the blank time signal Sb; and an output terminal for outputting the output signal Sgt. The voltage regulator control circuit 206 includes a first terminal coupled to the output Q of the flip-flop 204; and a second terminal coupled to the first terminal of the synchronous rectifier switch Ssr to receive the voltage difference Vds across the switch.

[0111] When the blank time signal Sb is enabled, AND gate 203 can output a low logic level as the output signal Sgt. When the blank time signal Sb is disabled, AND gate 203 can generate the output signal Sgt based on the fast falling edge signal Sf. Specifically, when the blank time signal Sb is disabled, the output signal Sgt can be equal to the fast falling edge signal Sf. As disclosed in applications TW110131031 and CN202110825305.6, the voltage regulation control circuit 206 can adjust the magnitude of the control voltage Vc, thereby outputting the control voltage Vc to the gate of the synchronous rectifier switch Ssr to change the impedance between the first and second terminals of the synchronous rectifier switch Ssr.

[0112] Flip-flop 204 can receive a fast falling edge signal Sf to generate an enable signal Sdet. Flip-flop 204 can be an SR flip-flop, including an input S for the fast falling edge signal Sf; an input R for receiving the reset voltage Voff; and an output Q for outputting the enable signal Sdet. Before the fast falling edge signal Sf of the voltage difference Vds across the switch occurs, the reset voltage Voff is at a low logic level. If the fast falling edge signal Sf is at a high logic level, the enable signal Sdet at the output Q of flip-flop 204 is also at a high logic level; if the fast falling edge signal Sf is at a low logic level, the enable signal Sdet can maintain its previous logic level. The reset voltage Voff corresponds to any secondary-side synchronous rectifier switch Ssr that should be turned off. For example, when the voltage difference Vds across the switch gradually rises from a lower negative voltage to exceed a predetermined voltage, such as from -80mV to -5mV, it indicates that the main switch Sm on the primary side of the flyback converter 1 may be about to be turned on. At this time, the reset voltage Voff can be set to a high logic level to reset the trigger 204, causing the turn-on signal Sdet to drop to a low logic level, so as to quickly turn off the secondary-side synchronous rectifier switch Ssr.

[0113] Figure 4 for Figure 2 The waveform diagram of the synchronous rectifier controller 16 includes the waveforms of the voltage difference Vds across the switch, the envelope signal Vev, the reverse blanking time signal Sbr, the filtered voltage difference VHPF across the switch, the output signal Sgt, and the control voltage Vc. Figure 4 The display shows times from t1 to t24, where the period between t1 and t3 is the energy storage period (Tchg1), the period between t3 and t5 is the energy release period (Tdis1), the period between t5 and t11 is the resonance period (Tres1), the period between t11 and t13 is the energy storage period (Tchg2), the period between t13 and t15 is the energy release period (Tdis2), the period between t15 and t21 is the resonance period (Tres2), and the period between t21 and t23 is the energy storage period (Tchg3). The following combinations... Figure 2 To illustrate, use the synchronous rectifier controller 16 in the middle. Figure 4 .

[0114] At time t1, during the energy storage period Tchg1, when the voltage difference VHPF across the filtered switch rapidly rises above the critical voltage, timer 214 is triggered to start counting, causing the reverse blank time signal Sbr to become a high logic threshold. Between times t1 and t2, the envelope signal Vev rises along with the voltage difference Vds across the switch. The difference between the voltage difference Vds and the envelope signal Vev is small, causing the reverse blank time signal Sbr to form a short pulse Tbs1.

[0115] At time t3, the primary side main switch Sm is turned off, and the energy release period Tdis1 begins. The voltage difference Vds across the switch drops rapidly. After filtering, the voltage difference VHPF across the switch has a negative pulse and is below the threshold voltage VL, causing the rapidly falling edge signal Sf to transition to a high logic level. Meanwhile, the inverted blank time signal Sbr of the short pulse Tbs1 has returned to a low logic level. Therefore, AND gate 203 allows the high logic level of the rapidly falling edge signal Sf to be passed to flip-flop 204, triggering its output enable signal Sdet, which is then passed to the voltage regulation control circuit 206. At time t4, the high logic level enable signal Sdet raises the control voltage Vc and fully turns on the synchronous rectifier switch Ssr at a lower impedance. Between times t4 and t4', the secondary current Id flowing through the synchronous rectifier switch Ssr gradually decreases as the discharge time increases; therefore, under the same lower impedance state, the voltage difference Vds across the switch gradually rises from a negative value towards 0V. At time t4', when the voltage difference Vds across the switch gradually rises to -30mV, the voltage regulation control circuit (not shown; possible embodiments of the voltage regulation control circuit can be found in applications TW110131031 and CN202110825305.6) is triggered to begin reducing the control voltage Vc, so that the synchronous rectifier switch Ssr is no longer in a fully conducting state with low impedance. Between times t4' and t5, by increasing the impedance of the synchronous rectifier switch Ssr, for example, the voltage difference Vds across the switch can be regulated to fluctuate slightly around -30mV.

[0116] At time t5, as the secondary current Id continues to decrease, even if the impedance of the synchronous rectifier switch Ssr is increased, the voltage difference Vds across the switch will eventually rise to more than -5mV, triggering the output reset voltage Voff. Thus, the reset enable signal Sdet is at a low logic level.

[0117] At time t5', the low logic level turn-on signal Sdet causes the control voltage Vc to drop to 0V, thereby turning off the synchronous rectifier switch Ssr. When the flyback converter 1 operates in discontinuous conduction mode (DCM), both the primary side main switch Sm and the secondary side synchronous rectifier switch Ssr are turned off. During the resonance period Tres1, the voltage difference Vds across the switch resonates and begins to rise. After filtering, the voltage difference VHPF across the switch has a positive pulse. However, the voltage difference Vds across the switch has not yet risen to equal the envelope signal Vev, and the envelope signal Vev continues to decrease.

[0118] (1) After time t5', when the voltage difference VHPF across the filtered switch exceeds the positive threshold voltage, timer 214 is triggered to change the reverse blank time signal Sbr to a high logic level; (2) Between time t5' and t6, the voltage difference Vds across the switch has a peak P11. After the envelope signal Vev rises to the peak P11, it begins to decrease more slowly according to its preset drooprate, while the voltage difference Vds across the switch decreases more rapidly according to the slope of its resonant waveform. Therefore, at a time later than the peak P11, there is a large difference between the voltage difference Vds across the switch and the envelope signal Vev, which triggers voltage-current converter 212 to output a longer time length control signal Sbl, thereby causing the reverse blank time signal Sbr to have a longer high level pulse Tbl1. Although the filtered voltage difference HPF11 between the switch terminals, obtained from the falling edge of the resonant waveform of the voltage difference Vds across the switch, may be lower than the threshold voltage VL, and a high-level fast falling edge signal Sf may be output, it is still within the corresponding high-level pulse Tbl1 period. Therefore, AND gate 203 will not trigger to pull up the output signal Sgt, thereby pulling up the control voltage Vc. When the length of the long pulse Tbl1 is less than the upper limit pulse length, the length of the long pulse Tbl1 can be positively correlated with the difference between the voltage difference Vds across the switch and the envelope signal Vev. Between times t6 and t7, although the difference between the voltage difference Vds across the switch and the envelope signal Vev is still large, when the length of the long pulse Tbl1 has reached the upper limit pulse length, the reverse blank time signal Sbr will be clamped and limited by circuit 216 to a low logic level.

[0119] After time t7, when the voltage difference VHPF across the filtered switch exceeds the positive threshold voltage, timer 214 is triggered to change the reverse blank time signal Sbr to a high logic level. Between times t7 and t8, the voltage difference Vds across the switch has a peak P12. After the envelope signal Vev rises to the peak P12, it begins to decrease more slowly according to its preset rate of decline, while the voltage difference Vds across the switch decreases more rapidly according to the slope of its resonant waveform. Therefore, at a point later than the peak P12, there is a large difference between the voltage difference Vds across the switch and the envelope signal Vev, triggering the voltage-to-current converter 212 to output a longer duration control signal Sbl, which in turn causes the reverse blank time signal Sbr to have a longer high-level pulse Tbl2. Although the filtered voltage difference HPF12 between the switch terminals, obtained from the falling edge of the resonant waveform of the voltage difference Vds across the switch, may be lower than the threshold voltage VL, and a high-level fast falling edge signal Sf may be output, it is still within the corresponding high-level pulse Tbl12 period. Therefore, AND gate 203 will not trigger to pull up the output signal Sgt, thereby pulling up the control voltage Vc. When the length of the long pulse Tbl2 is less than the upper limit pulse length, the length of the long pulse Tbl2 can be positively correlated with the difference between the voltage difference Vds across the switch and the envelope signal Vev. Between times t8 and t9, although the difference between the voltage difference Vds across the switch and the envelope signal Vev is still large, when the length of the long pulse Tbl2 has reached the upper limit pulse length, the reverse blank time signal Sbr will be clamped and limited by circuit 216 to a low logic level.

[0120] After time t9, when the voltage difference VHPF across the filtered switch exceeds the positive threshold voltage, timer 214 is triggered to change the reverse blank time signal Sbr to a high logic level. Between times t9 and t10, the voltage difference Vds across the switch has a peak P13. After the envelope signal Vev rises to the peak P13, it begins to decrease more slowly according to its preset rate of decline, while the voltage difference Vds across the switch decreases more rapidly according to the slope of its resonant waveform. Therefore, at a point later than the peak P13, there is a large difference between the voltage difference Vds across the switch and the envelope signal Vev, triggering the voltage-current converter 212 to output a longer duration control signal Sbl, which in turn causes the reverse blank time signal Sbr to have a longer high-level pulse Tbl3. At this time, the voltage difference HPF11 between the two ends of the switch may be higher than the threshold voltage VL after the falling edge of the resonant waveform Vds. Therefore, the high-level fast falling edge signal Sf is not output. Thus, AND gate 202 will not be triggered to pull up the output signal Sgt, thereby pulling up the control voltage Vc.

[0121] The operation mode of the synchronous rectifier controller 16 between time t11 and t20 is the same as that between time t1 and t10, and the details will not be repeated here.

[0122] Between times t20 and t21, the voltage difference Vds across the switch rises again to form another peak, and the envelope signal Vev rises accordingly. However, at this time (1) the resonance decay is slow, and the voltage levels of peaks P21 to P23 are close. (2) When the fourth rise of the resonance is about to reach the fourth peak, the energy storage period Tchg3 begins, and the voltage difference Vds across the switch is rapidly raised from the voltage level close to the resonance peak to the peak value of Vds when the synchronous rectifier switch Ssr is closed. The envelope signal Vev rises accordingly. After filtering, the voltage difference VHPF across the switch is a positive pulse. The difference between the voltage difference Vds across the switch and the envelope signal Vev makes the inverted blank time signal Sbr become a high logic level.

[0123] like Figure 4 As shown, between times t15 and t20, the rising edges of the three peaks P21 to P23 before resonance correspond to the voltage difference pulses HPF21 to 23 across the filtered switch, respectively. At time t21, the voltage difference pulse HPF24 across the filtered switch, corresponding to the start of the energy storage period Tchg3, appears. Because the voltage difference Vds across the switch is rapidly increased by a small voltage from a voltage level close to the resonant peak to reach the peak Vds when the synchronous rectifier switch Ssr is turned off, the voltage level of the positive pulse HPF24 is close to any of the voltage levels of the positive pulses HPF21 to 23. According to the embodiments disclosed in applications TW110124942 and CN202110688325.3, based on the voltage level of the positive pulse HPF24, the length of the reverse blank time signal Sbr will be incorrectly determined to be a long pulse Tbl, which may block the fast falling edge signal Sf appearing at time t24, preventing it from being transmitted to the trigger 204.

[0124] In this invention, between times t21 and t22, since the voltage difference Vds and envelope signal Vev across the switch almost overlap, the difference between the voltage difference Vds and envelope signal Vev is small. Therefore, the blank time circuit 162 will cause the reverse blank time signal Sbr to form a short pulse Tbs3, so that the reverse blank time signal Sbr will be converted to a high logic level before time point t24, allowing the fast falling edge signal Sf that appears at time point t24 to be successfully transmitted to the flip-flop 204.

[0125] The operation mode of the synchronous rectifier controller 16 between time t23 and t24 is the same as that between time t3 and t4, and the details will not be repeated here.

[0126] exist Figure 1 and Figure 2In the embodiment, the flyback converter 1 can automatically adjust the opening conditions of the synchronous rectifier switch Ssr by detecting the envelope of the voltage difference Vds across the switch without setting external pins, thereby reducing the probability of accidentally opening the synchronous rectifier switch Ssr and increasing the working efficiency of the flyback converter 1.

[0127] Figure 5 This is a schematic diagram of another blank time circuit 162 for the flyback converter 1. Figure 5 The blank time circuit 162 can be used to replace Figure 2 The blank time circuit 162 is used to generate the blank time signal Sb. Figure 5 The blanking time circuit 162 includes a voltage-to-current converter 60, an envelope detector 61, a comparator 62, a comparator circuit 64, an AND gate 66, a timer 68, a limit circuit 69, and an inverter 218. The voltage-to-current converter 60 is coupled to the first terminal of the synchronous rectifier switch Ssr, and the envelope detector 61 is coupled to the voltage-to-current converter 60. The comparator 62 is coupled to the envelope detector 61. The comparator circuit 64 is coupled to the envelope detector 61 and the voltage-to-current converter 60. The AND gate 66 is coupled to the comparators 62 and 64. The timer 68 is coupled to the AND gate 66. The limit circuit 69 is coupled to the timer 68, and the inverter 218 is coupled to the limit circuit 69.

[0128] The voltage-to-current converter 60 can be a resistor, converting the voltage difference Vds across the switch into a current ids. The envelope detector 61 can be a current envelope detector, detecting the peak of the current ids to generate a pull-up signal isource and an envelope signal iev. The envelope signal iev represents the envelope of the current ids. The pull-up signal isource is the charging current that generates the envelope signal iev. When the envelope signal iev is less than the current ids, it triggers the pull-up signal isource to go to a high logic level, turning on the power supply inside the envelope detector 61 to pull the envelope signal iev up to the current ids, thus maintaining the envelope signal iev at or above the current ids.

[0129] Comparator 62 includes an inverting input coupled to envelope detector 61 to receive the pull-up signal isource; a non-inverting input to receive the critical current level ith; and an output to output a digital signal cmp1. Comparator 62 compares the pull-up signal isource and the critical current ith to generate the digital signal cmp1. The digital signal cmp1 can be an active high signal. When the pull-up signal isource is less than the critical current ith, comparator 62 enables the digital signal cmp1; when the pull-up signal isource exceeds the critical current ith, comparator 62 disables the digital signal cmp1. The digital signal cmp1 can represent the drooping time of the pull-up signal isource. When the envelope signal iev is greater than or equal to the current ids, envelope detector 61 does not need to continue pulling up the envelope signal iev, so the value of the envelope signal iev will gradually decrease or remain stable; this period can be called the drooping time.

[0130] Comparator circuit 64 compares the envelope signal iev and the current ids to generate a digital signal cmp2. The digital signal cmp2 can be a high-active signal. When the difference between the envelope signal iev and the current ids is less than a preset difference os, comparator circuit 64 enables the digital signal cmp2; when the difference exceeds the preset difference os, comparator circuit 64 disables the digital signal cmp2. Comparator circuit 64 includes a shifter 640 and a comparator 642 coupled to each other. Shifter 640 includes a first terminal coupled to envelope detector 61 for receiving the envelope signal iev; and a second terminal. Shifter 640 can shift the envelope signal iev down by a default difference os to generate a shift signal (iev-os). Comparator 642 includes an inverting input, coupled to the second terminal of shifter 640, for receiving the shift signal (iev-os); a non-inverting input, coupled to voltage-to-current converter 60, for receiving the current ids; and an output for outputting a digital signal cmp2. The digital signal cmp2 represents the peak segment before and after the peak of the envelope signal iev. The resonant peak of the current ids during resonance (…) Figure 6 (P1 to P3) and the rising top platform during energy storage ( Figure 5 Both F1 and F2 will set the digital signal cmp2 to a high logic level.

[0131] AND gate 66 can perform an AND operation on digital signals cmp1 and cmp2 to generate a time length control signal Sbl. Only when both digital signals cmp1 and cmp2 are at high logic levels can AND gate 66 set the time length control signal Sbl to a high logic level to indicate the detection of a rising top platform during energy storage.

[0132] When the voltage difference VHPF across the filtered switch exceeds the critical voltage, it can be considered that the rising edge of the voltage difference Vds across the switch has been detected, triggering timer 68 to start timing. Timer 68 can generate a reverse blank time signal Sbr based on the time length control signal Sbl. When the time length control signal Sbl is at a low logic level, timer 68 can generate a longer pulse in the reverse blank time signal Sbr; when the time length control signal Sbl is at a high logic level, timer 68 can generate a shorter pulse in the reverse blank time signal Sbr. When the voltage difference VHPF across the filtered switch is less than the critical voltage, it can be considered that the rising edge of the voltage difference Vds across the switch has not been detected, therefore timer 68 can be reset and will not generate a pulse in the reverse blank time signal Sbr. Limiting circuit 69 can limit the reverse blank time signal Sbr within a predetermined range, and inverter 218 can invert the reverse blank time signal Sbr to generate a blank time signal Sb.

[0133] Figure 6 for Figure 5 The waveform diagram of the blank time circuit 162 includes the waveforms of the current ids, the envelope signal iev, the pull-up signal isource, the critical current ith, the digital signal cmp1, the digital signal cmp2, ​​and the time length control signal Sbl. Figure 6 The display shows times from t1 to t9, where the period from before time t1 to time t7 is the resonance period (Tres), and the period between time t7 and time t9 is the energy storage period (Tchg). The following combinations... Figure 5 The blank time circuit 162 in the middle is used to illustrate this. Figure 6 .

[0134] Between times t1 and t2, the current ids has a peak P1, and the envelope signal iev is pulled up with the peak P1. The pulled-up signal isource is a positive pulse and exceeds the critical current ith. Therefore, the digital signal cmp1 is at a low logic level. The difference between the envelope signal iev and the current ids is less than the preset difference os. Therefore, the digital signal cmp2 is at a high logic level. Since the digital signal cmp1 is at a low logic level and the digital signal cmp2 is at a high logic level, the time length control signal Sbl is at a low logic level. Between times t2 and t3, the current ids begins to decrease, and the envelope signal iev rises to peak P1 between times t1 and t2 before starting to decrease. The rise signal isource is 0A and is less than the critical current ith, so the digital signal cmp1 is at a high logic level. The difference between the envelope signal iev and the current ids exceeds the preset difference os, so the digital signal cmp2 is at a low logic level. Since the digital signal cmp1 is at a high logic level and the digital signal cmp2 is at a low logic level, the time length control signal Sbl remains at a low logic level, allowing timer 68 to generate a longer pulse in the inverted blank time signal Sbr.

[0135] Between time t3 and t7, there are the corresponding periods of the second and third peaks and troughs during the resonance period. The operation mode of the blank time circuit 162 is the same as that of the first peak and trough period between time t1 and t3, and its details will not be repeated here.

[0136] Between times t7 and t8, the current ids rises again to form another peak, and the envelope signal iev rises accordingly. However, when the fourth rise of the resonance is about to reach the fourth peak, the energy storage period Tchg begins. The voltage difference Vds across the switch is rapidly increased from the voltage level close to the resonance peak P3 to the peak value F1 of Vds when the synchronous rectifier switch Ssr is closed. The envelope signal iev rises accordingly. The rise signal isource is a positive pulse and the rise signal isource exceeds the critical current ith. Therefore, the digital signal cmp1 is at a low logic level. The difference between the envelope signal iev and the current ids is less than the preset difference os. Therefore, the digital signal cmp2 is at a high logic level. Since the digital signal cmp1 is at a low logic level and the digital signal cmp2 is at a high logic level, the time length control signal Sbl is at a low logic level.

[0137] Between times t8 and t9, the current ids remains constant, the envelope signal iev remains constant, the pull-up signal isource is 0A and less than the critical current ith, therefore the digital signal cmp1 is at a high logic level; the difference between the envelope signal iev and the current ids is less than the preset difference os, therefore the digital signal cmp2 maintains a high logic level; since both the digital signals cmp1 and cmp2 are at a high logic level, the time length control signal Sbl is at a high logic level, enabling timer 68 to generate a shorter pulse in the inverted blank time signal Sbr.

[0138] Figure 7 This is a circuit diagram of Timer 68. Timer 68 receives a time length control signal Sbl to generate a reverse blank time signal Sbr. Timer 68 includes a controllable current source Isrc, a switching device SW, a capacitor Cs, and a comparator CP. The controllable current source Isrc includes a first terminal coupled to the power supply terminal VDD; a second terminal; and a control terminal for receiving the time length control signal Sbl. The switching device SW includes a first terminal coupled to the second terminal of the controllable current source Isrc; a second terminal coupled to the ground terminal VSS2; and a control terminal for receiving the comparison result of the filtered voltage difference across the switch and the critical voltage Vth. The capacitor Cs includes a first terminal coupled to the second terminal of the controllable current source Isrc; and a second terminal coupled to the ground terminal VSS2. The comparator CP may include an inverting input terminal coupled to the first terminal of the switching device SW and the first terminal of the capacitor Cs, a non-inverting input terminal for receiving a reference potential VR, and an output terminal for outputting the reverse blank time signal Sbr to generate a pulse. The switching device SW can be implemented using a transistor. The capacitor Cs can be implemented using a transistor or discrete components. The reference potential VR can be a predetermined voltage level.

[0139] The controllable current source Isrc provides charging current based on the time length control signal Sbl. When the time length control signal Sbl is at a low logic level, the controllable current source Isrc provides a basic charging current; when the time length control signal Sbl is at a high logic level, the controllable current source Isrc provides an enhanced charging current, which is greater than the basic charging current. The switching device SW resets timer 68 based on the comparison result of the filtered voltage difference VHPF across the switch and the critical voltage Vth. When the comparison result shows that the filtered voltage difference VHPF across the switch exceeds the critical voltage Vth, the switching device SW can be turned off, and the charging current of the controllable current source Isrc charges capacitor Cs, causing the potential of capacitor Cs to gradually increase. The comparator CP compares the potential of capacitor Cs with the reference potential VR to generate a pulse for the reverse blank time signal Sbr. When the potential of capacitor Cs is less than the reference potential VR, the comparator CP is triggered to output a high logic level, which is used to generate a pulse for the reverse blank time signal Sbr. Charging capacitor Cs with a basic charging current requires a longer time for its potential to exceed the reference potential VR, thus generating a longer pulse in the reverse blanking time signal Sbr. Charging capacitor Cs with an enhanced charging current requires only a shorter time for its potential to exceed the reference potential VR, thus generating a shorter pulse in the reverse blanking time signal Sbr. The shorter pulse is shorter than the longer pulse.

[0140] Figure 8 This is a circuit diagram of envelope detector 61. Envelope detector 61 can receive current ids to generate a pull-up signal isource and an envelope signal iev. Envelope detector 61 includes operational amplifiers U1 and U2, diodes D1 to D3, capacitor C1, resistors R1 to R5, transistor Q1, and reset switch SWr.

[0141] Operational amplifier U1 can act as an input buffer amplifier. Diodes D1 and D3 and capacitor C1 can track and store the peak of the current ids. Transistor Q1 can generate a pull-up signal isource to charge capacitor C1. Resistor R4 consumes current and generates a droop time. Reset switch SWr can reset capacitor C1 according to the reset signal Srst. The pull-up signal isource can be the charging current.

[0142] exist Figure 5 In this embodiment, the flyback converter 1 can automatically adjust the opening conditions of the synchronous rectifier switch Ssr by detecting the envelope of the current ids without setting external pins, thereby reducing the probability of accidentally opening the synchronous rectifier switch Ssr and increasing the working efficiency of the flyback converter 1.

[0143] Figure 9This is a flowchart of a control method 1000 for a flyback converter 1. The control method 1000 includes steps S1002 to S1010, used to automatically adjust the on-state conditions of the control voltage Vc of the synchronous rectifier switch Ssr. Any reasonable technical modifications or adjustments to the steps fall within the scope of this invention. Steps S1002 to S1010 are described below:

[0144] Step S1002: The signal is detected by the detection circuit 160 along the falling edge of the voltage difference Vds across the switch and outputs a fast falling edge signal Sf;

[0145] Step S1004: Blank time circuit 162 detects the peak based on the voltage difference Vds across the switch to generate an envelope signal;

[0146] Step S1006: Blank time circuit 162 generates a time length control signal based on the difference between the voltage difference Vds across the switch and the envelope signal. A larger difference corresponds to a longer time period.

[0147] Step S1008: Blank time circuit 162 generates blank time signal Sb based on the voltage difference Vds across the switch and the time length control signal;

[0148] Step S1010: The output circuit 164 generates an output signal Sgt after performing logical operations based on the blank time signal Sb and the fast falling edge signal Sf, thereby generating a control voltage Vc.

[0149] The details of steps S1002 to S1010 have been explained in the preceding paragraphs and will not be repeated here.

[0150] exist Figure 9 In the embodiments, the control method 1000 for controlling the flyback converter 1 can detect the envelope based on the voltage difference Vds across the switch without setting external pins, thereby automatically adjusting the opening conditions of the synchronous rectifier switch Ssr, reducing the probability of accidentally opening the synchronous rectifier switch Ssr and increasing the working efficiency of the flyback converter 1.

[0151] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of protection of the present invention should be included in the scope of the present invention.

Claims

1. A synchronous rectification control method applicable to a flyback converter, the flyback converter comprising a transformer, a main switch, a synchronous rectification switch, and a synchronous rectification controller, the transformer comprising a primary coil and a secondary coil, the primary coil being coupled to the main switch, the synchronous rectification switch comprising: One end is coupled to the secondary coil and the synchronous rectifier controller; A second terminal is coupled to a power output port and the synchronous rectifier controller, and there is a voltage difference between the two ends of a switch between the first terminal and the second terminal; A control terminal, coupled to the synchronous rectifier controller, is used to receive a control voltage from the synchronous rectifier controller to change the impedance between the first and second terminals of the synchronous rectifier switch. The synchronous rectifier controller includes a signal edge detection circuit, a blanking time circuit, and an output circuit. The method comprises: The signal is generated by detecting a fast falling edge of the voltage difference across the switch along the detection circuit. The blank time circuit detects a peak based on the voltage difference across the switch to generate an envelope signal. The blank time circuit generates a time length control signal based on the voltage difference across the switch and the envelope signal. The blank time circuit generates a blank time signal based on the voltage difference across the switch and the time length control signal; and The output circuit performs a logic operation based on the blank time signal and the fast falling edge signal to generate an output signal, thereby generating the control voltage.

2. The method as described in claim 1, characterized in that, The blank time circuit includes an envelope detector, a voltage-to-current converter, a timer, and an inverter. The blank time circuit detects the wave peak based on the voltage difference across the switch to generate the envelope signal, including: The envelope detector detects the peak of the voltage difference across the switch to generate the envelope signal; The blank time circuit generates the time length control signal based on the voltage difference across the switch and the envelope signal, including: The voltage-to-current converter generates a difference current as the time length control signal based on the difference between the envelope signal and the voltage difference across the switch; and The blank time circuit generates the blank time signal based on the voltage difference across the switch and the time length control signal, including: When the voltage difference across the switch exceeds a critical voltage, the timer generates a reverse blank time signal based on the time length control signal; and The inverter inverts the inverted blank time signal to generate the blank time signal.

3. The method as described in claim 2, characterized in that, The blank time circuit also includes a limiting circuit; and The blank time circuit, which generates the blank time signal based on the voltage difference across the switch and the time length control signal, further includes: The limiting circuit restricts the reverse blank time signal to a predetermined range.

4. The method as described in claim 1, characterized in that, The blank time circuit includes a voltage-to-current converter, an envelope detector, a first comparator, a second comparator, an AND gate, a timer, and an inverter. The blank time circuit detects the wave peak based on the voltage difference across the switch to generate the envelope signal, including: The voltage-to-current converter converts the voltage difference across the switch into a current flow; and The envelope detector detects the peak of the current flowing through it to generate a pull-up signal and the envelope signal. The blank time circuit generates the time length control signal based on the voltage difference across the switch and the envelope signal, including: The first comparator compares the pull-up signal with a critical current to generate a first digital signal; The second comparator compares the envelope signal and the current flow to generate a second digital signal; and The AND gate applies an AND operation to the first digital signal and the second digital signal to generate the time length control signal; and The blank time circuit generates the blank time signal based on the voltage difference across the switch and the time length control signal, including: When the voltage difference across the switch exceeds a critical voltage, the timer generates a reverse blank time signal based on the time length control signal; and The inverter inverts the inverted blank time signal to generate the blank time signal.

5. The method as described in claim 4, characterized in that: The first comparator compares the pull-up signal and the threshold current to generate the first digital signal, including: When the pull-up signal is less than the critical current, the first comparator enables the first digital signal; and The second comparator compares the envelope signal and the current flow to generate the second digital signal, including: When the difference between the envelope signal and the current is less than a preset difference, the second comparator enables the second digital signal.

6. The method as described in claim 4, characterized in that, The blank time circuit also includes a limiting circuit; The blank time circuit, which generates the blank time signal based on the voltage difference across the switch and the time length control signal, further includes: The limiting circuit restricts the reverse blank time signal to a predetermined range.

7. The method as described in claim 1, characterized in that, The signal edge detection circuit includes a filter and a third comparator; The fast falling edge signal that the detection circuit detects the voltage difference across the switch includes: The filter filters the voltage difference across the switch to generate a filtered voltage difference across the switch; and The third comparator compares the voltage difference across the filtered switch with a critical level to generate the fast falling edge signal.

8. The method as described in claim 7, characterized in that, It also includes adjusting the filter during power-on until the fast falling edge signal is detected.

9. The method as described in claim 7, characterized in that, It also includes adjusting the critical level until the fast falling edge signal is detected during power-on.

10. The method as described in claim 1, characterized in that, The output circuit generates the output signal based on the blank time signal and the fast falling edge signal, including: When the blank time signal is disabled, the output circuit generates the output signal based on the fast falling edge signal.

11. A flyback converter, characterized in that, include: A transformer, comprising: A primary coil includes a first terminal for receiving an input signal and a second terminal; and A primary and secondary coil, including a first end and a second end; A main switch is coupled to the second terminal of the primary coil; A synchronous rectifier switch includes: a first terminal coupled to a second terminal of a secondary coil and a synchronous rectifier controller for outputting a voltage difference across the switch; a second terminal coupled to a power output port and the synchronous rectifier controller; and a control terminal coupled to the synchronous rectifier controller for receiving a control voltage to generate an output voltage; and The synchronous rectification controller, coupled to the first terminal and the control terminal of the synchronous rectification switch, includes: A signal edge detection circuit is coupled to the first terminal of the synchronous rectifier switch to detect a fast falling edge of the voltage difference across the switch to generate a fast falling edge signal. A blanking time circuit, coupled to the first terminal of the synchronous rectifier switch, is used to detect a peak based on the voltage difference across the switch to generate an envelope signal, generate a time length control signal based on the voltage difference across the switch and the envelope signal, the time length control signal representing a difference between the envelope signal and the voltage difference across the switch exceeding a predetermined threshold, and generate a blanking time signal based on the voltage difference across the switch and the time length control signal; and An output circuit, coupled to the signal edge detection circuit and the blank time circuit, is used to perform a logic operation based on the blank time signal and the fast falling edge signal to generate an output signal, thereby generating the control voltage.

12. The flyback converter as described in claim 11, characterized in that, The blank time circuit includes: An envelope detector is coupled to the first terminal of the synchronous rectifier switch to detect the peak of the voltage difference across the switch to generate the envelope signal. A voltage-to-current converter, coupled to the envelope detector, is used to generate a difference current as the time length control signal based on a difference between the envelope signal and the voltage difference across the switch. A timer, coupled to the first terminal of the synchronous rectifier switch and the voltage-to-current converter, is used to generate a reverse blanking time signal based on the time length control signal when the voltage difference across the switch exceeds a critical voltage; and An inverter, coupled to the timer, is used to invert the inverted blank time signal to generate the blank time signal.

13. The flyback converter as described in claim 12, characterized in that, The blank time circuit also includes a limiting circuit coupled to the timer and the inverter to limit the reverse blank time signal to a predetermined range.

14. The flyback converter as described in claim 11, characterized in that, The blank time circuit includes: A voltage-to-current converter is coupled to the first terminal of the synchronous rectifier switch to convert the voltage difference across the switch into a current flow. An envelope detector, coupled to the voltage-to-current converter, is used to detect the peak of the current flowing through it to generate a pull-up signal and the envelope signal. A first comparator, coupled to the envelope detector, is used to compare the pull-up signal and a threshold current to generate a first digital signal. A second comparator, coupled to the envelope detector, is used to compare the envelope signal and the current flow to generate a second digital signal; An AND gate, coupled to the first comparator and the second comparator, is used to apply an AND operation to the first digital signal and the second digital signal to generate the time length control signal; A timer, coupled to the first terminal of the synchronous rectifier switch and the AND gate, is used to generate a reverse blanking time signal based on the time length control signal when the voltage difference across the switch exceeds a critical voltage; and An inverter, coupled to the timer, is used to invert the inverted blank time signal to generate the blank time signal.

15. The flyback converter as described in claim 14, characterized in that: When the pull-up signal is less than the threshold current, the first comparator enables the first digital signal; and When the difference between the envelope signal and the current is less than a preset difference, the second comparator enables the second digital signal.

16. The flyback converter as described in claim 14, characterized in that, The blank time circuit also includes a limiting circuit coupled to the timer and the inverter to limit the reverse blank time signal to a predetermined range.

17. The flyback converter as claimed in claim 11, characterized in that, The signal edge detection circuit includes: A filter, coupled to the first terminal of the synchronous rectifier switch, is used to filter the voltage difference across the switch to generate a filtered voltage difference across the switch; and A third comparator, coupled to the filter, is used to compare the voltage difference across the filtered switch with a critical level to detect the fast falling edge signal.

18. The flyback converter as claimed in claim 11, characterized in that, The output circuit generates the output signal based on the fast falling edge signal when the blank time signal is disabled.

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