Drive circuit for power tubes

Abstract

The present disclosure provides a driving circuit for a power tube, which comprises: a first current generating unit for generating a first current indicating that the power tube is locked in an off state when a power-on voltage is in a low power supply voltage stage; and a second current generating unit for generating a second current indicating that the power tube is locked in an on state when the power-on voltage is in a driving control voltage stage, wherein when the power tube is locked in the on state, the driving control voltage is greater than a preset reference voltage, and the gate potential of the power tube is dynamically maintained at a potential state of the driving control voltage to turn on the power tube. Thus, the opening and closing voltage of the power tube can be adjusted to the vicinity of the preset reference voltage, and when the power tube is opened, the driving control voltage applied externally is almost entirely applied to the gate of the power tube, thereby avoiding the consumption of the dynamic range of the driving control voltage, improving the stability and accuracy of the driving circuit, and reducing power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of electronic power technology, and more specifically to a driving circuit for a power transistor. Background Technology

[0002] In power supply systems, electrical energy is converted by controlling the switching power transistors (i.e., power switching transistors) to turn on and off. The control of switching frequency, input and output voltage and current are all key to the conversion of electrical energy, so the drive control of the switching power transistors is essential.

[0003] As is known, power switching transistors include Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Insulated-Gate Bipolar Transistors (IGBTs), and switching characteristics are a crucial feature of power switching transistors. Currently, in power switching transistors, the charging and discharging of the gate capacitor using a gate resistor is often used to control the switching process. If the selected gate resistor is inappropriate, oscillations will occur, increasing the pulse spikes in the collector or drain voltage of the power switching transistor.

[0004] Figure 1 shows a power transistor. The turn-on and turn-off voltage of the power transistor is determined by the threshold voltage VTH, which is determined by the manufacturing process and cannot be arbitrarily adjusted. For example, the typical threshold voltage of an LDMOS transistor in a high-voltage process is about 1.2V. However, some applications require adjustment of the turn-on and turn-off voltage of the power transistor, such as adjusting it to 1.8V, which is not achievable with existing driver circuits. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a driving circuit for power transistors.

[0006] This disclosure provides a driving circuit for a power transistor, the power transistor having a drain coupled to a drain node, a source coupled to a low supply voltage, and a gate coupled to a gate node, wherein the driving circuit includes:

[0007] The first current generation unit is configured to generate a first current flowing into the gate node in response to a power-on voltage low supply voltage phase. The first current is used to indicate that the power transistor is locked in the off state.

[0008] The second current generation unit is configured to generate a second current flowing into the gate node in response to a power-on voltage that is a drive control voltage. This second current is used to indicate that the power transistor is locked into the operating state.

[0009] In this context, the aforementioned power-on voltage is the drive control voltage stage. If the drive control voltage is greater than the preset reference voltage, the second current generation unit adjusts its conduction path to control the gate node potential to maintain the potential state of the drive control voltage in order to turn on the power transistor. If the drive control voltage is not greater than the aforementioned reference voltage, the second current generation unit keeps the power transistor in the off state.

[0010] Preferably, the aforementioned first current generation unit has a first input node that receives the aforementioned drive control voltage, a second input node that receives the aforementioned power-on voltage, an output node connected to the aforementioned gate node, and a source node connected to the aforementioned low power supply voltage.

[0011] Preferably, the aforementioned first current generating unit includes:

[0012] A first current source and a first transistor are connected in series between a first input node and a source node, and the connection node of the first current source and the first transistor is connected to the control terminal of the first transistor.

[0013] A second current source and a second transistor are connected in series between a first input node and a source node, and the connection node between the second current source and the second transistor is connected to the control terminal of the second transistor.

[0014] Preferably, the aforementioned first current generating unit further includes:

[0015] The third, fourth, and fifth transistors are connected in series between the output node and the source node to form the conduction path of the aforementioned first current. The control terminal of the fourth transistor is connected to the control terminal of the first transistor, and the control terminal of the fifth transistor is connected to the control terminal of the second transistor.

[0016] An inverter, whose input terminal serves as the aforementioned second input node, and whose output terminal is connected to the control terminal of the third transistor.

[0017] Preferably, the aforementioned second current generating unit includes:

[0018] A sixth transistor and a third current source are connected in series between the first input node and the source node, and the connection node of the sixth transistor and the third current source is connected to the control terminal of the sixth transistor.

[0019] A seventh transistor and a fourth current source are connected in series between the first input node and the source node, and the connection node of the seventh transistor and the fourth current source is connected to the control terminal of the seventh transistor.

[0020] The eighth transistor, the ninth transistor, and the first resistor are connected in series between the first input node and the source node. The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, and the control terminal of the ninth transistor is connected to the control terminal of the sixth transistor.

[0021] Preferably, the aforementioned second current generating unit further includes:

[0022] The tenth, eleventh, twelfth, and thirteenth transistors are connected in series between the first input node and the output node to form the conduction path for the aforementioned second current.

[0023] Furthermore, the control terminal of the tenth transistor is connected to the control terminal of the seventh transistor, the control terminal of the eleventh transistor is connected to the control terminal of the sixth transistor, the control terminal of the twelfth transistor is connected to the output terminal of the aforementioned inverter, and the control terminal of the thirteenth transistor is connected to the connection node between the aforementioned ninth transistor and the first resistor.

[0024] Preferably, the aforementioned driving circuit further includes:

[0025] The second resistor is connected between the output node and the source node.

[0026] Preferably, the aforementioned power transistor or any one of the aforementioned first to thirteenth transistors is a metal-oxide-semiconductor field-effect transistor device.

[0027] Preferably, the first to fifth transistors mentioned above are all N-channel metal-oxide-semiconductor field-effect transistor devices.

[0028] Preferably, the aforementioned power transistors and the aforementioned sixth to thirteenth transistors are all P-channel metal-oxide-semiconductor field-effect transistor devices.

[0029] The beneficial effects of this disclosure are as follows: The driving circuit for a power transistor provided by this disclosure includes: a first current generating unit configured to generate a first current flowing into the gate node in response to a low power supply voltage stage, the first current being used to indicate that the power transistor is locked in an off state; and a second current generating unit configured to generate a second current flowing into the gate node in response to a drive control voltage stage, the second current being used to indicate that the power transistor is locked in an operating state. In the aforementioned power supply voltage stage, if the drive control voltage is greater than a preset reference voltage, the second current generating unit adjusts its conduction path to dynamically maintain the gate node potential at the drive control voltage potential state to turn on the power transistor. If the drive control voltage is not greater than the aforementioned reference voltage, the second current generating unit maintains the power transistor in an off state. Therefore, the voltage at which the power transistor is turned on and off can be adjusted to be close to a preset reference voltage through circuit design and parameter control. At the same time, when the power transistor is turned on, almost all of the externally applied drive control voltage is applied to the gate of the power transistor to avoid consuming the dynamic range of the drive control voltage, thereby improving the stability and accuracy of the drive circuit and reducing power consumption. Attached Figure Description

[0030] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of the structure of a driving circuit for a power transistor in the prior art is shown;

[0032] Figure 2 A schematic diagram of the structure of a drive circuit for a power transistor provided in an embodiment of this disclosure is shown. Detailed Implementation

[0033] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0035] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0036] Figure 2This diagram illustrates a structural schematic of a drive circuit for a power transistor provided in an embodiment of the present disclosure.

[0037] refer to Figure 2 This disclosure provides a driving circuit 100 for a power transistor M0, the power transistor M0 having a drain coupled to a drain node D, a source coupled to a low supply voltage VS, and a gate coupled to a gate node G. The driving circuit 100 includes a first current generation unit 110 and a second current generation unit 120.

[0038] The first current generation unit 110 is configured to generate a first current I7 flowing into the gate node G in response to the power-on voltage VEN being a low power supply voltage VS stage. The first current I7 is used to indicate that the power transistor M0 is locked in the off state.

[0039] The second current generation unit 120 is configured to generate a second current I6 flowing into the gate node G in response to the power-on voltage VEN being the drive control voltage VG. This second current I6 is used to indicate that the power transistor M0 is locked in the operating state.

[0040] Wherein, the aforementioned power-on voltage VEN is the drive control voltage VG stage (i.e., the power transistor M0 is locked in the working state). If the drive control voltage VG is greater than the preset reference voltage Vref, then the second current generation unit 120 adjusts its conduction path to control the potential of the aforementioned gate node G to maintain the potential state of the drive control voltage VG, so as to turn on the power transistor M0. If the drive control voltage VG is not greater than the aforementioned reference voltage Vref, then the second current generation unit 120 maintains the power transistor M0 in the off state.

[0041] Furthermore, in this embodiment, the aforementioned first current generation unit 110 has a first input node that receives the aforementioned drive control voltage VG, a second input node that receives the aforementioned power-on voltage VEN, and an output node connected to the aforementioned gate node G and a source node S connected to the aforementioned low power supply voltage VS.

[0042] Furthermore, in this embodiment, the aforementioned first current generating unit 110 includes:

[0043] A first current source I1 and a first transistor M12 are connected in series between the first input node and the source node S, and the connection node of the first current source I1 and the first transistor M12 is connected to the control terminal of the first transistor M12.

[0044] The second current source I2 and the second transistor M13 are connected in series between the first input node and the source node S, and the connection node of the second current source I2 and the second transistor M13 is connected to the control terminal of the second transistor M13.

[0045] Furthermore, in this embodiment, the aforementioned first current generating unit 110 further includes:

[0046] The third transistor M9, the fourth transistor M10, and the fifth transistor M11 are connected in series between the output node (i.e., the gate node G, the same below) and the source node S to form the conduction path of the aforementioned first current I7. The control terminal of the fourth transistor M10 is connected to the control terminal of the first transistor M12, and the control terminal of the fifth transistor M11 is connected to the control terminal of the second transistor M13.

[0047] Inverter INV, whose input terminal serves as the aforementioned second input node, and whose output terminal is connected to the control terminal of the third transistor M9.

[0048] Furthermore, in this embodiment, the aforementioned second current generating unit 120 includes:

[0049] The sixth transistor M1 and the third current source I3 are connected in series between the first input node and the source node S, and the connection node of the sixth transistor M1 and the third current source I3 is connected to the control terminal of the sixth transistor M1.

[0050] The seventh transistor M2 and the fourth current source I4 are connected in series between the first input node and the source node S, and the connection node of the seventh transistor M2 and the fourth current source I4 is connected to the control terminal of the seventh transistor M2.

[0051] The eighth transistor M3, the ninth transistor M4, and the first resistor R1 are connected in series between the first input node and the source node S. The control terminal of the eighth transistor M3 is connected to the control terminal of the seventh transistor M2, and the control terminal of the ninth transistor M4 is connected to the control terminal of the sixth transistor M1.

[0052] Furthermore, in this embodiment, the aforementioned second current generating unit 120 further includes:

[0053] The tenth transistor M5, the eleventh transistor M6, the twelfth transistor M7, and the thirteenth transistor M8 are connected in series between the first input node and the output node to form the conduction path for the aforementioned second current I6.

[0054] Furthermore, the control terminal of the tenth transistor M5 is connected to the control terminal of the seventh transistor M2, the control terminal of the eleventh transistor M6 is connected to the control terminal of the sixth transistor M1, the control terminal of the twelfth transistor M7 is connected to the output terminal of the aforementioned inverter INV, and the control terminal of the thirteenth transistor M8 is connected to the connection node between the aforementioned ninth transistor M4 and the first resistor R1.

[0055] Furthermore, in this embodiment, the aforementioned driving circuit 100 further includes:

[0056] The second resistor R2 is connected between the output node and the source node S.

[0057] Furthermore, in this embodiment, any one of the aforementioned power transistor M0, first transistor M12, second transistor M13, third transistor M9, fourth transistor M10, fifth transistor M11, sixth transistor M1, seventh transistor M2, eighth transistor M3, ninth transistor M4, tenth transistor M5, eleventh transistor M6, twelfth transistor M7, and thirteenth transistor M8 is a metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOS transistor) device.

[0058] Furthermore, in this embodiment, the aforementioned first transistor M12, second transistor M13, third transistor M9, fourth transistor M10 and fifth transistor M11 are all N-channel MOS transistor devices.

[0059] Furthermore, in this embodiment, the aforementioned power transistor M0, sixth transistor M1, seventh transistor M2, eighth transistor M3, ninth transistor M4, tenth transistor M5, eleventh transistor M6, twelfth transistor M7 and thirteenth transistor M8 are all P-channel MOS transistor devices.

[0060] As described above, in some practical applications, it is necessary to adjust the on / off voltage of the power transistor. The driving circuit 100 for the power transistor M0 provided in this embodiment is also a circuit for adjusting the on / off voltage of the power transistor M0. Specifically, I‍1‍~I‍4‍ are bias current sources, which respectively provide bias currents to drive the first transistor M12, the second transistor M13, the sixth transistor M1, and the seventh transistor M2‍ to generate a bias voltage. Refer to Figure 2 , in this embodiment, the eighth transistor M3 / the ninth transistor M4‍, the tenth transistor M5 / the eleventh transistor M6, and the fourth transistor M10 / the fifth transistor M11 respectively form current source structures.

[0061] Currently, the driving circuits of the vast majority of power transistors adopt a structure with a gate resistor or separate turn-on and turn-off resistors. Regardless of the magnitude of the output current of the power transistor, its on and off speeds are the same, which will result in excessive losses when the current is large and parasitic oscillations are likely to occur when the current is small. In this embodiment, the second current I‍6‍ is the current for driving the power transistor M0 to turn on. By parameter setting, the resistance value of the second resistor R‍2‍ is made to satisfy I‍6‍>>(V‍G‍ / R‍2‍), then the influence of the second resistor R‍2‍ on the turn-on speed of the power transistor M0 can be ignored.

[0062] The first current I‍7‍ is the current for driving the power transistor M0 to turn off. Further, the twelfth transistor M7 / the third transistor M9 are used as switching transistors. When the power-on voltage V‍EN‍ is the negative power supply voltage V‍S‍, the power transistor M0 is turned off. When the power-on voltage V‍‍EN‍ is the drive control voltage V‍G, the power transistor M0 is in the working state, that is, the on / off of the power transistor M0 is controlled by the drive control voltage V‍G‍.

[0063] Specifically, when V‍EN‍=V‍G‍, we analyze how much V‍ the drive control voltage V‍G‍ is greater than (satisfying the preset reference voltage Vref, Vref=I‍5‍*R‍1‍+‍V‍TH8) when the power transistor M0 is turned on. Let the threshold voltage of the thirteenth transistor M8 be V‍TH8‍. When V‍G‍<Vref, the thirteenth transistor M8 is in the off state, and the gate node potential V‍GINT‍ is discharged to the source node S by the second resistor R‍2‍, and the power transistor M0 is always in the off state.

[0064] When V‍G‍>Vref, the thirteenth transistor M8 is turned on, and the resistance value of the second resistor R‍2‍ can be adjusted so that the voltage drop changes on the tenth transistor M5~the thirteenth transistor M8 caused by R‍2‍ can be ignored. Due to the charging effect of the second current I‍6‍, the gate node potential V‍GINT‍ of the power transistor M0≈V‍G‍.

[0065] Therefore, based on the above, we can see that the drive circuit 100 adjusts the voltage at which the power transistor M0 is turned on and off to a preset reference voltage Vref. At the same time, when the power transistor M0 is turned on, the gate node potential VGINT of the power transistor M0 is approximately equal to VG, meaning that the externally applied drive control voltage VG is almost entirely applied to the gate of the power transistor M0, and the drive circuit 100 does not consume the dynamic range of VG.

[0066] It should be noted that the condition that should be met is I5*R1+VTH8>VTH, that is, Vref>VTH, where VTH is the threshold voltage of the power transistor M0 itself. This means that the drive circuit 100 cannot adjust the voltage at which the power transistor M0 is turned on and off to be less than the threshold voltage of the power transistor M0 itself.

[0067] In summary, the driving circuit 100 for power transistor M0 provided in this disclosure includes: a first current generation unit 100 configured to generate a first current I7 flowing into the gate node G in response to a low power supply voltage VS stage of the power-on voltage VEN, the first current I7 being used to indicate that the power transistor M0 is locked in the off state; and a second current generation unit 120 configured to generate a second current I6 flowing into the gate node G in response to a drive control voltage VG stage of the power-on voltage VEN, the second current I6 being used to indicate that the power transistor M0 is locked in the working state. Specifically, in the aforementioned power-on voltage VEN stage of the drive control voltage VG stage, if the drive control voltage VG is greater than a preset reference voltage Vref, then the second current I6 generation unit adjusts its conduction path to dynamically maintain the potential of the gate node G at the potential state of the drive control voltage VG to turn on the power transistor M0; if the drive control voltage VG is not greater than the aforementioned reference voltage Vref, then the second current I6 generation unit maintains the power transistor M0 in the off state. Thus, the voltage at which the power transistor M0 is turned on and off can be adjusted to be near the preset reference voltage Vref through circuit design and parameter control. At the same time, when the power transistor M0 is turned on, almost all of the externally applied drive control voltage VG is applied to the gate of the power transistor M0 to avoid consuming the dynamic range of the drive control voltage VG, thereby improving the stability and accuracy of the drive circuit 100 and reducing power consumption.

[0068] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0069] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0070] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A driving circuit for a power transistor, the power transistor having a drain coupled to a drain node, a source coupled to a low supply voltage, and a gate coupled to a gate node, characterized in that, The driving circuit includes: The first current generation unit is configured to generate a first current flowing into the gate node in response to the power-on voltage being the low power supply voltage phase, the first current being used to indicate that the power transistor is locked in the off state. The second current generation unit is configured to generate a second current flowing into the gate node in response to the power-on voltage being a drive control voltage phase. This second current is used to indicate that the power transistor is locked into an operating state. Specifically, during the power-on voltage phase of the drive control voltage stage, if the drive control voltage is greater than a preset reference voltage, the second current generation unit adjusts its conduction path to maintain the potential of the gate node at the drive control voltage level, thereby turning on the power transistor. If the drive control voltage is not greater than the reference voltage, the second current generation unit keeps the power transistor in the off state. The first current generating unit includes: The first input node that receives the drive control voltage; The second input node receives the power-on voltage; The output node connected to the gate node; Connect to the source node with the low power supply voltage; A first current source and a first transistor are connected in series between the first input node and the source node, and the connection node between the first current source and the first transistor is connected to the control terminal of the first transistor. The second current source and the second transistor are connected in series between the first input node and the source node, and the connection node between the second current source and the second transistor is connected to the control terminal of the second transistor. A third transistor, a fourth transistor, and a fifth transistor are connected in series between the output node and the source node to form a conduction path for the first current. The control terminal of the fourth transistor is connected to the control terminal of the first transistor, and the control terminal of the fifth transistor is connected to the control terminal of the second transistor. An inverter, the input of which serves as the second input node, and its output connected to the control terminal of the third transistor.

2. The driving circuit according to claim 1, characterized in that, The second current generating unit includes: A sixth transistor and a third current source are connected in series between the first input node and the source node, and the connection node between the sixth transistor and the third current source is connected to the control terminal of the sixth transistor. A seventh transistor and a fourth current source are connected in series between the first input node and the source node, and the connection node between the seventh transistor and the fourth current source is connected to the control terminal of the seventh transistor. An eighth transistor, a ninth transistor, and a first resistor are connected in series between the first input node and the source node. The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, and the control terminal of the ninth transistor is connected to the control terminal of the sixth transistor.

3. The driving circuit according to claim 2, characterized in that, The second current generating unit further includes: The tenth, eleventh, twelfth, and thirteenth transistors are connected in series between the first input node and the output node to form a conduction path for the second current. Furthermore, the control terminal of the tenth transistor is connected to the control terminal of the seventh transistor, the control terminal of the eleventh transistor is connected to the control terminal of the sixth transistor, the control terminal of the twelfth transistor is connected to the output terminal of the inverter, and the control terminal of the thirteenth transistor is connected to the connection node between the ninth transistor and the first resistor.

4. The driving circuit according to claim 3, characterized in that, Also includes: A second resistor is connected between the output node and the source node.

5. The driving circuit according to claim 3, characterized in that, The power transistor and any one of the first to thirteenth transistors are metal-oxide-semiconductor field-effect transistor devices.

6. The driving circuit according to claim 5, characterized in that, The first to the fifth transistors are all N-channel metal-oxide-semiconductor field-effect transistor devices.

7. The driving circuit according to claim 6, characterized in that, The power transistor and the sixth to thirteenth transistors are all P-channel metal-oxide-semiconductor field-effect transistor devices.

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