level shifter

Abstract

A circuit includes a control inverter, a first latch circuit, and a second latch circuit. The control inverter receives a control signal to generate an inverted control signal. The first latch circuit is enabled by the inverted control signal to convert a first input signal ranging from a first supply voltage to ground into a first output signal ranging from a second supply voltage to ground. The second latch circuit is enabled by the inverted control signal to convert a second input signal ranging from the first supply voltage to ground into a second output signal ranging from the second supply voltage to ground. Wherein the first supply voltage and the second supply voltage are different.

Description

Technical Field

[0001] This invention generally relates to a multi-bit level shifter with a shared enable signal. Background Technology

[0002] Level shifters are widely used components in digital circuits for communication between two different power domains: a low-voltage domain and a high-voltage domain. As the requirements for level shifters in circuits increase, the chip area occupied by level shifters also increases significantly. Therefore, how to reduce the area of ​​multi-bit level shifters is a problem that needs to be solved. Summary of the Invention

[0003] This paper presents some architectures for multi-bit level converters. Since all N latch circuits share the same control inverter to generate the inverting control signal, (N-1) inverters or (N-1)*2 transistors are reduced, which is significant when N is a large number. The output signal of the multi-bit level converter can be pulled to the supply voltage or ground to prevent output signal fluctuation. This invention also provides a space-saving method to eliminate antenna effects and provides an area-efficient layout for the multi-bit level converter, which not only improves electrostatic discharge (ESD) performance but also reduces the overall chip area.

[0004] In one embodiment, a circuit includes a control inverter, a first latch circuit, and a second latch circuit. The control inverter receives a control signal to generate an inverted control signal. The inverted control signal is the inverse of the control signal. The first latch circuit is activated by the inverted control signal to convert a first input signal ranging from a first supply voltage to ground into a first output signal ranging from a second supply voltage to ground. The second latch circuit is activated by the inverted control signal to convert a second input signal ranging from the first supply voltage to ground into a second output signal ranging from the second supply voltage to ground. The first supply voltage and the second supply voltage are different.

[0005] In one embodiment of the invention, the circuit further includes a first input inverter, a second input inverter, a third input inverter, and a fourth input inverter. The first input inverter receives a first input signal to generate a first inverted input signal. The second input inverter receives the first inverted input signal to generate a second inverted input signal. The third input inverter receives the second input signal to generate a third inverted input signal. The fourth input inverter receives the third inverted input signal to generate a fourth inverted input signal. The first, second, third, and fourth input inverters are powered by a first supply voltage.

[0006] According to an embodiment of the present invention, a first latching circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor. The first P-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to a first cross-coupled node, and the first terminal is coupled to a second supply voltage. The second P-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to a second cross-coupled node, and the first terminal is coupled to the second supply voltage. The third P-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a first inverted input signal, the first terminal is coupled to the second terminal of the first P-type transistor, and the second terminal is coupled to the second cross-coupled node. A first output signal is generated at the second cross-coupled node. The fourth P-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a second inverted input signal, the first terminal is coupled to the second terminal of the second P-type transistor, and the second terminal is coupled to the first cross-coupled node. The first N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal, and the first terminal is coupled to ground. The second N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a first inverted input signal. The first terminal is coupled to the second terminal of the first N-type transistor, and the second terminal is coupled to a second cross-coupled node. The third N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal, and the first terminal is coupled to ground. The fourth N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a second inverted input signal. The first terminal is coupled to the second terminal of the third N-type transistor, and the second terminal is coupled to a first cross-coupled node.

[0007] In an embodiment of the present invention, the second latch circuit includes a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, and an eighth N-type transistor. The fifth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a third cross-coupled node, and the first terminal is coupled to a second supply voltage. The sixth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a fourth cross-coupled node, and the first terminal is coupled to the second supply voltage. The seventh P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives a third inverted input signal, the first terminal is coupled to the second terminal of the fifth P-type transistor, and the second terminal is coupled to the fourth cross-coupled node. The eighth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives a fourth inverted input signal, the first terminal is coupled to the second terminal of the sixth P-type transistor, and the second terminal is coupled to the third cross-coupled node. A second output signal is generated at the third cross-coupled node. The fifth N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal, and the first terminal is coupled to ground. The sixth N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a third inverted input signal. The first terminal is coupled to the second terminal of the fifth N-type transistor, and the second terminal is coupled to a fourth cross-coupled node. The seventh N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal, and the first terminal is coupled to ground. The eighth N-type transistor includes a control terminal, a first terminal, and a second terminal. The control terminal receives a fourth inverted input signal. The first terminal is coupled to the second terminal of the seventh N-type transistor, and the second terminal is coupled to a third cross-coupled node.

[0008] In an embodiment of the present invention, the first latch circuit further includes a first control transistor. The first control transistor provides a second supply voltage to the second cross-coupled node according to an inverted control signal. The second latch circuit further includes a second control transistor. The second control transistor provides a second supply voltage to the third cross-coupled node according to an inverted control signal.

[0009] According to an embodiment of the present invention, when the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the first control transistor and the second control transistor are turned on, so as to provide a second supply voltage to the first output signal and the second output signal, respectively. When the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the first control transistor and the second control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

[0010] In an embodiment of the invention, the first latch circuit further includes a third control transistor. The third control transistor couples the first cross-coupled node to ground according to a control signal. The second latch circuit further includes a fourth control transistor. The fourth control transistor couples the fourth cross-coupled node to ground according to a control signal.

[0011] According to an embodiment of the present invention, when the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are turned on. A second supply voltage is provided to the first output signal and the second output signal, and the first cross-coupled node and the fourth cross-coupled node are coupled to ground.

[0012] According to another embodiment of the present invention, when the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

[0013] According to another embodiment of the present invention, the first latch circuit further includes a fifth control transistor and a sixth control transistor. The fifth control transistor couples the first output signal to ground according to a control signal. The sixth control transistor provides a second supply voltage to the first cross-coupled node according to an inverted control signal. The second latch circuit further includes a seventh control transistor and an eighth control transistor. The seventh control transistor provides a second supply voltage to the fourth cross-coupled node according to an inverted control signal. The eighth control transistor couples the second output signal to ground according to a control signal.

[0014] According to an embodiment of the present invention, when the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are turned on. The first output signal and the second output signal are coupled to ground, and the second supply voltage is provided to the first cross-coupled node and the fourth cross-coupled node. The first cross-coupled node, the second cross-coupled node, the third cross-coupled node, and the fourth cross-coupled node can be referred to as the first coupling node, the second coupling node, the third coupling node, and the fourth coupling node.

[0015] According to another embodiment of the present invention, when the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

[0016] According to another embodiment of the present invention, the first latching circuit further includes a ninth control transistor. The ninth control transistor couples the first cross-coupled node to ground according to a control signal. The second latching circuit further includes a tenth control transistor. The tenth control transistor couples the fourth cross-coupled node to ground according to a control signal.

[0017] According to an embodiment of the present invention, the circuit further includes a choke transistor. The choke transistor provides a first supply voltage to the first input inverter and the third input inverter according to a control signal.

[0018] According to an embodiment of the present invention, when the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the ninth control transistor and the tenth control transistor are turned on, so as to couple the first cross-coupled node and the fourth cross-coupled node to ground.

[0019] According to an embodiment of the present invention, when the first input signal and the second input signal are at logic high level, the choke transistor based on the logic high level is turned off, and the first inverted input signal and the third inverted input signal are at logic low level, while the second inverted input signal and the fourth inverted input signal are at logic high level.

[0020] According to another embodiment of the present invention, when the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, the seventh N-type transistor and the choke transistor are turned on, and the ninth control transistor and the tenth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

[0021] In one embodiment of the present invention, a P-type transistor and an N-type transistor in the level conversion circuit are arranged along a second direction, the P-type transistor and another P-type transistor in the level conversion circuit are arranged along a first direction, and the N-type transistor and another N-type transistor in the level conversion circuit are arranged along a first direction, wherein the first direction is orthogonal to the second direction.

[0022] In embodiments of the present invention, the circuit further includes a ninth N-type transistor, a tenth N-type transistor, an eleventh N-type transistor, and a twelfth N-type transistor. The ninth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and gate terminal coupled to ground. The tenth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and gate terminal coupled to the drain terminal of the ninth N-type transistor, and the drain terminal coupled to a first input signal. The eleventh N-type transistor includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and gate terminal coupled to ground. The twelfth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and gate terminal coupled to the drain terminal of the eleventh N-type transistor, and the drain terminal coupled to a second input signal.

[0023] The embodiments will now be described in detail with reference to the accompanying drawings. Attached Figure Description

[0024] The invention can be more fully understood by referring to the following detailed description and embodiments, in which:

[0025] Figure 1 This is a block diagram of a multi-bit level converter according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a multi-bit level converter according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention.

[0030] Figure 6 According to an embodiment of the present invention Figure 5 A schematic diagram of the choke transistor, the first input inverter, and the third inverter.

[0031] Figures 7A-7B A method for eliminating antenna effects according to some embodiments of the present invention is shown.

[0032] Figure 8 The layout of a multi-bit level converter according to an embodiment of the present invention is shown.

[0033] Figure 9 The layout of a multi-bit level converter according to another embodiment of the present invention is shown. Detailed Implementation

[0034] The following description is for illustrating the general principles of the invention and should not be construed as limiting. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed. The scope of the invention is best determined with reference to the appended claims.

[0035] It should be understood that although the terms “first,” “second,” etc., may be used to describe various elements in the description herein and throughout the claims, these elements should not be limited to these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0036] It should be understood that the following description provides various embodiments or examples for implementing different features of this application. Specific examples and arrangements of elements described below are for the purpose of simplifying the invention. Of course, these are merely examples and not limiting. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed. Furthermore, the configuration in the following description of a feature connected to and / or coupled to another feature may include embodiments where one feature and another feature are in direct contact, and may also include embodiments where an additional feature exists between one feature and another feature such that one feature and another feature are not in direct contact. Moreover, the term "coupled" is intended to indicate either indirect or direct electrical connection. Thus, if one component is coupled to another component, the connection may be a direct electrical connection or an indirect electrical connection via other components and connections.

[0037] Figure 1 This is a block diagram of a multi-bit level converter according to an embodiment of the present invention. Figure 1 As shown, the multi-bit level converter 100 includes a control inverter INVC, a first level converter LS1, a second level converter LS2, ... and an Nth level converter LSN.

[0038] The inverter INVC inverts the control signal SC to generate an inverted control signal SCB. According to an embodiment of the invention, the control signal SC is provided externally. Based on the control signal SC and the inverted control signal SCB, the first level converter LS1, the second level converter LS2…, and the Nth level converter LSN convert the first input signal IN1, the second input signal IN2…, and the Nth input signal INN into the first output signal SO1, the second output signal SO2…, and the Nth output signal SON, respectively.

[0039] In other words, the first level converter LS1, the second level converter LS2, ..., and the Nth level converter LSN share the same set of control signals SC and inverting control signals SCB, instead of each level converter being controlled by a separate set of control signals SC and inverting control signals SCB. Since N level converters share the same inverter to generate the inverting control signal SCB, (N-1) inverters can be reduced.

[0040] Figure 2 This is a schematic diagram of a multi-bit level converter according to an embodiment of the present invention. Figure 2 As shown, the multi-bit level converter 200 includes a first input inverter INV1, a second input inverter INV2, a third input inverter INV3, a fourth input inverter INV4, a control inverter INVC, a first latch circuit 210, and a second latch circuit 220. Figure 2 The multi-bit level converter 220, which includes two latching circuits, shown in the illustration is for illustrative purposes only and is not intended to be limited thereto. According to other embodiments of the invention, the multi-bit level converter 200 may include any number of level converters.

[0041] The first input inverter INV1 receives the first input signal IN1 and inverts it to generate the first inverted input signal INB1. The second input inverter INV2 receives the first inverted input signal INB1 and inverts it to generate the second inverted input signal INB2. The third input inverter INV3 receives the second input signal IN2 and inverts it to generate the third inverted input signal INB3. The fourth input inverter INV4 receives the third inverted input signal INB3 and inverts it to generate the fourth inverted input signal INB4.

[0042] According to an embodiment of the present invention, the first inverted input signal INB1 is out-phase with the first input signal IN1, the second inverted input signal INB2 is in-phase with the first input signal IN1, the third inverted input signal INB3 is out-phase with the second input signal IN2, and the fourth inverted input signal INB4 is in-phase with the second input signal IN2. Figure 2 As shown, the first input inverter INV1, the second input inverter INV2, the third input inverter INV3, and the fourth input inverter INV4 are powered by the first supply voltage VDD1. The control inverter INVC receives the control signal SC and inverts the control signal SC to generate an inverted control signal SCB.

[0043] The first latching circuit 210 includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a fourth P-type transistor P4, a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, and a first control transistor MX1.

[0044] The first P-type transistor P1 includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to a first cross-coupled node CC1, and the first terminal is coupled to a second supply voltage VDD2. The second P-type transistor P2 includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to a second cross-coupled node CC2, and the first terminal is coupled to the second supply voltage VDD2. In an embodiment of the present invention, the first supply voltage VDD1 and the second supply voltage VDD2 are different.

[0045] The third P-type transistor P3 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a first inverted input signal INB1. The first terminal is coupled to the second terminal of the first P-type transistor P1, and the second terminal is coupled to the second cross-coupled node CC2. The first output signal SO1 is generated at the second cross-coupled node CC2. The fourth P-type transistor P4 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a second inverted input signal INB2. The first terminal is coupled to the second terminal of the second P-type transistor P2, and the second terminal is coupled to the first cross-coupled node CC1.

[0046] The first N-type transistor N1 includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal SCB, and the first terminal is coupled to ground. The second N-type transistor N2 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a first inverted input signal INB1. The first terminal is coupled to the second terminal of the first N-type transistor N1, and the second terminal is coupled to a second cross-coupled node CC2.

[0047] The third N-type transistor N3 includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal SCB, and the first terminal is coupled to ground. The fourth N-type transistor N4 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a second inverted input signal INB2. The first terminal is coupled to the second terminal of the third N-type transistor N3, and the second terminal is coupled to the first cross-coupled node CC1. The first control transistor MX1 ​​provides a second supply voltage VDD2 to the second cross-coupled node CC2 according to the inverted control signal SCB.

[0048] The second latching circuit 220 includes a fifth P-type transistor P5, a sixth P-type transistor P6, a seventh P-type transistor P7, an eighth P-type transistor P8, a fifth N-type transistor N5, a sixth N-type transistor N6, a seventh N-type transistor N7, an eighth N-type transistor N8, and a second control transistor MX2.

[0049] The fifth P-type transistor P5 includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to the third cross-coupled node CC3, and the first terminal is coupled to the second supply voltage VDD2. The sixth P-type transistor P6 includes a control terminal, a first terminal, and a second terminal. The control terminal is coupled to the fourth cross-coupled node CC4, and the first terminal is coupled to the second supply voltage VDD2.

[0050] The seventh P-type transistor P7 includes a control terminal, a first terminal, and a second terminal. The control terminal receives the fourth inverted input signal INB4. The first terminal is coupled to the second terminal of the fifth P-type transistor P5, and the second terminal is coupled to the fourth cross-coupled node CC4. The eighth P-type transistor P8 includes a control terminal, a first terminal, and a second terminal. The control terminal receives the third inverted input signal INB3. The first terminal is coupled to the second terminal of the sixth P-type transistor P6, and the second terminal is coupled to the third cross-coupled node CC3. The second output signal SO2 is generated at the third cross-coupled node CC3.

[0051] The fifth N-type transistor N5 includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal SCB, and the first terminal is coupled to ground. The sixth N-type transistor N6 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a fourth inverted input signal INB4. The first terminal is coupled to the second terminal of the fifth N-type transistor N5, and the second terminal is coupled to the fourth cross-coupled node CC4.

[0052] The seventh N-type transistor N7 includes a control terminal, a first terminal, and a second terminal. The control terminal receives an inverted control signal SCB, and the first terminal is coupled to ground. The eighth N-type transistor N8 includes a control terminal, a first terminal, and a second terminal. The control terminal receives a third inverted input signal INB3. The first terminal is coupled to the second terminal of the seventh N-type transistor N7, and the second terminal is coupled to the third cross-coupled node CC3. The second control transistor MX2 provides a second supply voltage VDD2 to the third cross-coupled node CC3 according to the inverted control signal SCB.

[0053] According to an embodiment of the present invention, the first latch circuit 210 and the second latch circuit 220 are activated by the control signal SC and the inverting control signal SCB. More specifically, when the control signal SC is at a logic high level and the inverting control signal SCB is at a logic low level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5, and the seventh N-type transistor N7 are turned off to deactivate the first latch circuit 210 and the second latch circuit 220, and the first control transistor MX1 ​​and the second control transistor MX2 are turned on to pull the first output signal SO1 and the second output signal SO2 to the second supply voltage VDD2.

[0054] In addition, when the control signal SC is at a logic low level and the inverting control signal SCB is at a logic high level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5 and the seventh N-type transistor N7 are turned on, and the first control transistor MX1 ​​and the second control transistor MX2 are turned off, thereby activating the first latch circuit 210 and the second latch circuit 220.

[0055] Therefore, the first latch circuit 210 converts the first inverted input signal INB1 and the second inverted input signal INB2 (i.e., the first input signal IN1) which range from the first supply voltage VDD1 to ground into the first output signal SO1 which ranges from the second supply voltage VDD2 to ground. The second latch circuit 220 converts the third inverted input signal INB3 and the fourth inverted input signal INB4 (i.e., the second input signal IN2) which range from the first supply voltage VDD1 to ground into the second output signal SO2 which ranges from the second supply voltage VDD2 to ground.

[0056] Figure 3 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention. Figure 3 Multi-level converter 300 and Figure 2 Compared to the multi-level converter 200, the first latch circuit 310 further includes a third control transistor MX3, and the second latch circuit 320 further includes a fourth control transistor MX4. The third control transistor MX3 couples the first cross-coupled node CC1 to ground according to the control signal SC. The fourth control transistor MX4 couples the fourth cross-coupled node CC4 to ground according to the control signal SC.

[0057] According to an embodiment of the present invention, when the control signal SC is at a logic high level and the inverting control signal SCB is at a logic low level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5, and the seventh N-type transistor N7 are turned off to deactivate the first latch circuit 310 and the second latch circuit 320. Furthermore, the first control transistor MX1 ​​and the second control transistor MX2 are turned on, pulling the first output signal SO1 and the second output signal SO2 high to the second supply voltage VDD2. The third control transistor MX3 and the fourth control transistor MX4 are turned on, coupling the first cross-coupled node CC1 and the fourth cross-coupled node CC4 to ground, respectively.

[0058] According to another embodiment of the present invention, when the control signal SC is at a logic low level and the inverting control signal SCB is at a logic high level, the operation of the first latch circuit 310 and the second latch circuit 320 is the same as that of the first latch circuit 210 and the second latch circuit 220, and will not be described again here.

[0059] Figure 4 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention. The multi-bit level converter 400 and... Figure 3 The multi-level converter 300 in the first latch circuit 310 is compared with the first control transistor MX1 ​​and the third control transistor MX3 in the first latch circuit 310. The first control transistor MX1 ​​and the third control transistor MX3 in the first latch circuit 410 are replaced with the fifth control transistor MX5 and the sixth control transistor MX6 in the first latch circuit 410. The second control transistor MX2 and the fourth control transistor MX4 in the second latch circuit 320 are replaced with the seventh control transistor MX7 and the eighth control transistor MX8 in the second latch circuit 420.

[0060] The fifth control transistor MX5 couples the first output signal SO1 to ground according to the control signal SC. The sixth control transistor MX6 provides the second supply voltage VDD2 to the first cross-coupled node CC1 according to the inverted control signal SCB. The seventh control transistor MX7 provides the second supply voltage VDD2 to the fourth cross-coupled node CC4 according to the inverted control signal SCB. The eighth control transistor MX8 couples the second output signal SO2 to ground according to the control signal SC.

[0061] According to one embodiment of the present invention, when the control signal SC is at a logic high level and the inverting control signal SCB is at a logic low level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5, and the seventh N-type transistor N7 are turned off to deactivate the first latch circuit 410 and the second latch circuit 420. The fifth control transistor MX5 and the eighth control transistor MX8 are turned on to pull the first output signal SO1 and the second output signal SO2 to ground. The sixth control transistor MX6 and the seventh control transistor MX7 are turned on to provide the second supply voltage VDD2 to the first cross-coupled node CC1 and the fourth cross-coupled node CC4.

[0062] According to another embodiment of the present invention, when the control signal SC is at a logic low level and the inverting control signal SCB is at a logic high level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5 and the seventh N-type transistor N7 are turned on, and the fifth control transistor MX5, the sixth control transistor MX6, the seventh control transistor MX7 and the eighth control transistor MX8 are turned off, so that the first latch circuit 410 and the second latch circuit 420 operate normally.

[0063] Figure 5 This is a schematic diagram of a multi-bit level converter according to another embodiment of the present invention. The multi-bit level converter 500 and... Figure 4In the comparison of the multi-bit level converter 400, the fifth control transistor MX5 and the sixth control transistor MX6 in the first latch circuit 410 are replaced by the ninth control transistor MX9 in the first latch circuit 510, and the seventh control transistor MX7 and the eighth control transistor MX8 in the second latch circuit 420 are replaced by the tenth control transistor MX10 in the second latch circuit 520. Furthermore, the multi-bit level converter 500 also includes a choke transistor MC.

[0064] The ninth control transistor MX9 couples the first cross-coupled node CC1 to ground according to the control signal SC. The tenth control transistor MX10 couples the fourth cross-coupled node CC4 to ground according to the control signal SC. The choke transistor MC provides the first supply voltage VDD1 to the first input inverter INV1 and the third input inverter INV3 according to the control signal SC.

[0065] According to an embodiment of the present invention, when the control signal SC is at a logic high level and the inverting control signal SCB is at a logic low level, after the first N-type transistor N1 and the third N-type transistor N3, the fifth N-type transistor N5 and the seventh N-type transistor N7 are turned off to deactivate the first latch circuit 510 and the second latch circuit 520, and the ninth control transistor MX9 and the tenth control transistor MX10 are turned on to couple the first cross-coupled node CC1 and the fourth cross-coupled node CC4 to ground.

[0066] In addition, when the first input signal IN1 and the second input signal IN2 are also at logic high level, the choke transistor MC is turned off according to the logic high level control signal SC, the first inverting input signal INB1 and the third inverting input signal INB3 are at logic low level, and the second inverting input signal INB2 and the fourth inverting input signal INB4 are at logic high level.

[0067] According to another embodiment of the present invention, when the control signal SC is at a logic low level and the inverting control signal SCB is at a logic high level, the first N-type transistor N1, the third N-type transistor N3, the fifth N-type transistor N5, the seventh N-type transistor N7 and the choke transistor MC are turned on, and the ninth control transistor MX9 and the tenth control transistor MX10 are turned off, so that the first latch circuit 510 and the second latch circuit 520 operate normally.

[0068] Figure 6 According to an embodiment of the present invention Figure 5 A schematic diagram of the choke transistor, the first input inverter, and the third inverter. (See diagram below.) Figure 6As shown, the first input inverter INV1 includes a first P-type inverter transistor PI1 and a first N-type inverter transistor NI1. The third input inverter INV3 includes a second P-type inverter transistor PI2 and a second N-type inverter transistor NI2.

[0069] The first P-type inverter transistor PI1 provides the first supply voltage VDD1 from the choke transistor MC to the first inverting input signal INB1 according to the first input signal IN1. The first N-type inverter transistor NI1 couples the first inverting input signal INB1 to ground according to the first input signal IN1. The second P-type inverter transistor PI2 provides the first supply voltage VDD1 from the choke transistor MC to the third inverting input signal INB3 according to the second input signal IN2. The second N-type inverter transistor NI2 couples the third inverting input signal INB3 to ground according to the second input signal IN2.

[0070] like Figure 6 As shown, when the control signal SC, the first input signal IN1, and the second input signal IN2 are at logic high levels, the choke transistor MC is turned off based on the logic high level control signal SC. Based on the logic high levels of the first input signal IN1 and the second input signal IN2, the first P-type inverter transistor PI1 and the second P-type inverter transistor PI2 are turned off. The first N-type inverter transistor NI1 and the second N-type inverter transistor NI2 are turned on, causing the first inverted input signal INB1 and the third inverted input signal INB3 to be pulled down to ground.

[0071] Figures 7A-7B Methods for eliminating antenna effects according to some embodiments of the present invention are illustrated. For example... Figure 7A As shown, the first input signal IN1 is coupled to ground through the first reverse-biased diode DI1, and the second input signal IN2 is coupled to ground through the second reverse-biased diode DI2. Therefore, the charge accumulated on the first input signal IN1 or the second input signal IN2 can be discharged to ground through the first diode DI1 or the second diode DI2, respectively. However, the first diode DI1 and the second diode DI2 occupy a large area of ​​the chip.

[0072] like Figure 7B As shown, the first input signal IN1 is coupled to ground through the ninth N-type transistor N9 and the tenth N-type transistor N10, and the second input signal IN2 is coupled to ground through the eleventh N-type transistor N11 and the twelfth N-type transistor N12.

[0073] The ninth N-type transistor N9 includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and the gate terminal coupled to ground. The tenth N-type transistor N10 includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and the gate terminal coupled to the drain terminal of the ninth N-type transistor N9, and the drain terminal coupled to the first input signal NI1.

[0074] The eleventh N-type transistor N11 includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and the gate terminal coupled to ground. The twelfth N-type transistor N12 includes a source terminal, a gate terminal, and a drain terminal, with the source terminal and the gate terminal coupled to the drain terminal of the eleventh N-type transistor N11, and the drain terminal coupled to the second input signal IN2.

[0075] According to an embodiment of the present invention, when charge accumulates on the first input signal IN1 or the second input signal IN2, the accumulated charge can be discharged to ground through the ninth N-type transistor N9 and the tenth N-type transistor N10, or through the eleventh N-type transistor N11 and the twelfth N-type transistor N12. However, the area occupied by the ninth N-type transistor N9 and the tenth N-type transistor N10 (or the eleventh N-type transistor N11 and the twelfth N-type transistor N12) on the chip is much smaller than the area occupied by the first diode DI1 (or the second diode DI2) on the chip, thus significantly reducing the chip area.

[0076] Figure 8 The layout of a multi-bit level converter according to an embodiment of the present invention is shown. Figure 8 As shown, layout 800 includes a first P-type transistor layout PM1, a second P-type transistor layout PM2, a first N-type transistor layout NM1, and a second N-type transistor layout NM2, wherein the first N-type transistor layout NM1 and the second N-type transistor layout NM2 are surrounded by an N-type guard ring NR. According to an embodiment of the present invention, Figure 8 Another layout 800 is shown, arranged in layout 800 such that the first P-type transistor layout PM1 and the second P-type transistor layout PM2 are surrounded by a P-type guard ring PR. For example... Figure 8 As shown in the embodiment, the first P-type transistor layout PM1, the P-type guard ring PR, the N-type guard ring NR, the first N-type transistor layout NM1, the second N-type transistor layout NM2, and the second N-type transistor layout PM2 are arranged along the first direction D1.

[0077] According to some embodiments of the present invention, Figure 2-6 Multi-bit level converter Each transistor can be arranged in a layout 800 configuration. For example... Figure 8 As shown, layout 800 also includes a power line PL and a ground line GL.

[0078] The power line PL includes a first via landing region VIA1 and a second via landing region VIA2, wherein the first via landing region VIA1 and the second via landing region VIA2 are used to supply the power supply voltage provided by the power line PL to the first P-type transistor layout PM1 and the second P-type transistor layout PM2.

[0079] The ground line GL includes a third via placement area VIA3, wherein the third via placement area VIA3 is used to couple the first N-type transistor layout NM1 and the second N-type transistor layout NM2 to ground. According to an embodiment of the present invention, the power line PL and the ground line GL may be formed of the same metal layer or different metal layers, and the first via placement area VIA1, the second via placement area VIA2 and the third via placement area VIA3 may be formed of the same or different via layers.

[0080] Figure 9 A layout of a multi-bit level shifter according to another embodiment of the present invention is shown. A P-type transistor and an N-type transistor in the level shifting circuit are arranged along a second direction, the P-type transistor and another P-type transistor in the level shifting circuit are arranged along a first direction, and the N-type transistor and another N-type transistor in the level shifting circuit are arranged along the first direction, which is orthogonal to the second direction. In an alternative embodiment, the second direction is perpendicular to the direction of the power line and / or ground line. Figure 9 As shown, P-type transistor layouts PM3 and PM4 and N-type transistor layouts NM3 and NM4 are arranged along a second direction D2, wherein the first direction D1 and the second direction D2 are orthogonal. In an embodiment of the invention, the first direction D1 is the Y-axis, and the second direction D2 is the X-axis. Furthermore, a P-type guard ring PR also surrounds the third P-type transistor layout PM3 and the fourth P-type transistor layout PM4, and an N-type guard ring NR also surrounds the third N-type transistor layout NM3 and the fourth N-type transistor layout NM4.

[0081] like Figure 9 As shown, the power line PL crosses the third P-type transistor layout PM3 and the fourth P-type transistor layout PM4, and provides power supply voltage to the third P-type transistor layout PM3 and the fourth P-type transistor layout PM4 via the fourth via placement area VIA4. The ground line GL crosses the third N-type transistor layout NM3 and the fourth N-type transistor layout NM4, and couples the third N-type transistor layout NM3 and the fourth N-type transistor layout NM4 to ground via the fifth via placement area VIA5.

[0082] Layout 900 and Figure 8In layout 800, P-type guard ring PR, P-type transistors (including third P-type transistor layout PM3 and fourth P-type transistor layout PM4), P-type guard ring PR, N-type guard ring NR, N-type transistors (including third N-type transistor layout NM3 and fourth N-type transistor layout NM4) and N-type guard ring NR are arranged along the second direction D2, such that the via placement area of ​​power line PL or ground line GL is twice the via placement area of ​​layout 800, and power line PL or ground line GL has half the height of layout 800 along the first direction D1.

[0083] In other words, compared to layout 800, the via placement area of ​​layout 900 is doubled because the P-type guard ring PR and N-type guard ring NR of layout 900 are arranged along the second direction D2 to separate the P-type transistor and the N-type transistor along the second direction D2.

[0084] Furthermore, because layout 900 separates the P-type transistor layout and the N-type transistor layout, it is compatible with... Figure 8 Compared to layout 800, layout 900 can significantly reduce the overall area.

[0085] This paper presents some architectures for multi-bit level converters. Since all N latch circuits share the same control inverter to generate the inverting control signal, (N-1) inverters or (N-1)*2 transistors are reduced, which is a significant reduction when N is large. The output signal of the multi-bit level converter can be pulled to the supply voltage or ground to prevent output signal fluctuation. This invention also provides a space-saving method to eliminate antenna effects, and an effective area layout for multi-bit level converters that not only improves ESD performance but also reduces the overall chip area.

[0086] While some embodiments of the invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. For example, those skilled in the art will readily understand that some features, functions, processes, and materials described herein can be varied while remaining within the scope of the invention. Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure of this invention, processes, machines, manufactures, compositions of matter, means, methods, or steps that are currently existing or will be developed thereafter and perform substantially the same function or achieve substantially the same effect as the corresponding embodiments described herein can be used. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A level conversion circuit, characterized in that, include: The inverter is controlled to receive a control signal to generate an inverted control signal, wherein the inverted control signal is the inverse of the control signal; The first latching circuit is activated by the inverting control signal to convert a first input signal ranging from a first supply voltage to ground into a first output signal ranging from a second supply voltage to ground. as well as The second latching circuit is activated by the inverting control signal to convert a second input signal ranging from the first supply voltage to ground into a second output signal ranging from the second supply voltage to ground, wherein the first supply voltage and the second supply voltage are different. In this circuit, a P-type transistor and an N-type transistor are arranged along a second direction, a P-type transistor and another P-type transistor are arranged along a first direction, and an N-type transistor and another N-type transistor are arranged along a first direction, wherein the first direction is orthogonal to the second direction.

2. The circuit as described in claim 1, characterized in that, Also includes: A first input inverter receives the first input signal to generate a first inverted input signal; The second input inverter receives the first inverted input signal to generate the second inverted input signal; The third input inverter receives the second input signal to generate a third inverted input signal; as well as The fourth input inverter receives the third inverted input signal to generate a fourth inverted input signal, wherein the first input inverter, the second input inverter, the third input inverter, and the fourth input inverter are powered by the first supply voltage.

3. The circuit as described in claim 2, characterized in that, The first latch circuit includes: A first P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a first cross-coupled node, and the first terminal is coupled to a second supply voltage; The second P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a second cross-coupled node, and the first terminal is coupled to a second supply voltage. The third P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the first inverted input signal, the first terminal is coupled to the second terminal of the first P-type transistor, and the second terminal is coupled to the second cross-coupled node, wherein the first output signal is generated at the second cross-coupled node. The fourth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the second inverted input signal, the first terminal is coupled to the second terminal of the second P-type transistor, and the second terminal is coupled to the first cross-coupled node. A first N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the inverted control signal, and the first terminal is coupled to ground; The second N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the first inverted input signal, the first terminal is coupled to the second terminal of the first N-type transistor, and the second terminal is coupled to the second cross-coupled node. A third N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the inverted control signal, and the first terminal is coupled to ground; and The fourth N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the second inverted input signal, the first terminal is coupled to the second terminal of the third N-type transistor, and the second terminal is coupled to the first cross-coupled node.

4. The circuit as described in claim 3, characterized in that, The second latch circuit includes: The fifth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a third cross-coupled node, and the first terminal is coupled to the second supply voltage; The sixth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a fourth cross-coupled node, and the first terminal is coupled to the second supply voltage. The seventh P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the fourth inverting input signal, the first terminal is coupled to the second terminal of the fifth P-type transistor, and the second terminal is coupled to the fourth cross-coupled node. The eighth P-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the third inverting input signal, the first terminal is coupled to the second terminal of the sixth P-type transistor, and the second terminal is coupled to the third cross-coupled node, wherein the second output signal is generated at the third cross-coupled node. The fifth N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the inverted control signal, and the first terminal is coupled to the ground; The sixth N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the fourth inverting input signal, the first terminal is coupled to the second terminal of the fifth N-type transistor, and the second terminal is coupled to the fourth cross-coupled node. A seventh N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the inverted control signal, and the first terminal is coupled to ground; and The eighth N-type transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal receives the third inverted input signal, the first terminal is coupled to the second terminal of the seventh N-type transistor, and the second terminal is coupled to the third cross-coupled node.

5. The circuit as described in claim 4, characterized in that, The first latch circuit further includes: The first control transistor provides the second power supply voltage to the second cross-coupled node according to the inverted control signal; The second latch circuit further includes: The second control transistor provides the second supply voltage to the third cross-coupled node according to the inverted control signal.

6. The circuit as described in claim 5, characterized in that, When the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the first control transistor and the second control transistor are turned on to provide the second supply voltage to the first output signal and the second output signal, respectively. When the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the first control transistor and the second control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

7. The circuit as described in claim 5, characterized in that, The first latch circuit further includes: A third control transistor couples the first cross-coupled node to the ground according to the control signal; The second latch circuit further includes: The fourth control transistor couples the fourth cross-coupled node to the ground according to the control signal.

8. The circuit as described in claim 7, characterized in that, When the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are turned on. The second supply voltage is provided to the first output signal and the second output signal, and the first cross-coupled node and the fourth cross-coupled node are coupled to the ground.

9. The circuit as described in claim 7, characterized in that, When the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

10. The circuit as described in claim 4, characterized in that, The first latch circuit further includes: The fifth control transistor couples the first output signal to the ground according to the control signal; The sixth control transistor provides the second supply voltage to the first cross-coupled node according to the inverted control signal; The second latch circuit further includes: The seventh control transistor provides the second supply voltage to the fourth cross-coupled node according to the inverted control signal; and The eighth control transistor couples the second output signal to the ground according to the control signal.

11. The circuit as described in claim 10, characterized in that, When the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are turned on. The first output signal and the second output signal are coupled to ground, and the second supply voltage is provided to the first cross-coupled node and the fourth cross-coupled node.

12. The circuit as described in claim 10, characterized in that, When the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned on, and the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

13. The circuit as described in claim 4, characterized in that, The first latch circuit further includes: The ninth control transistor couples the first cross-coupled node to the ground according to the control signal; The second latch circuit further includes: The tenth control transistor couples the fourth cross-coupled node to the ground according to the control signal.

14. The circuit as described in claim 13, characterized in that, Also includes: A choke transistor provides the first supply voltage to the first input inverter and the third input inverter according to the control signal.

15. The circuit as described in claim 14, characterized in that, When the control signal is at a logic high level and the inverting control signal is at a logic low level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, and the seventh N-type transistor are turned off, and the ninth control transistor and the tenth control transistor are turned on, so as to couple the first cross-coupled node and the fourth cross-coupled node to the ground.

16. The circuit as described in claim 15, characterized in that, When the first input signal and the second input signal are at a logic high level, the choke is turned off based on the control signal at a logic high level, and the first inverted input signal and the third inverted input signal are at a logic low level, and the second inverted input signal and the fourth inverted input signal are at a logic high level.

17. The circuit as described in claim 15, characterized in that, When the control signal is at a logic low level and the inverting control signal is at a logic high level, the first N-type transistor, the third N-type transistor, the fifth N-type transistor, the seventh N-type transistor, and the choke transistor are turned on, and the ninth control transistor and the tenth control transistor are turned off, so that the first latch circuit and the second latch circuit operate normally.

18. The circuit as described in claim 1, characterized in that, Also includes: A ninth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are coupled to ground; The tenth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are coupled to the drain terminal of the ninth N-type transistor, and the drain terminal is coupled to the first input signal; An eleventh N-type transistor includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are coupled to the ground; as well as The twelfth N-type transistor includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal and the gate terminal are coupled to the drain terminal of the eleventh N-type transistor, and the drain terminal is coupled to the second input signal.

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