Image reading method with double conversion gain, imaging apparatus, and readable storage medium

Abstract

The application provides a dual conversion gain image reading method, an imaging device and a readable storage medium. The image reading method comprises the following steps: starting a high conversion gain reset mode, and controlling a readout circuit to quantize a high conversion gain reset signal; starting a high conversion gain image mode, and controlling the readout circuit to quantize a high conversion gain image signal; starting a low conversion gain reset mode, and controlling the readout circuit to quantize a low conversion gain reset signal; and starting a low conversion gain image mode, and controlling the readout circuit to quantize a low conversion gain image signal. Through the optimized gain signal quantization sequence, the same column readout circuit can be used to complete the reading operation of a column of pixel signals, the reading time is greatly reduced, and the reading speed is accelerated.

Description

Technical Field

[0001] This application relates to the field of high dynamic range image processing technology, specifically to an image reading method, imaging device, and readable storage medium with dual conversion gain. Background Technology

[0002] Dynamic range (DR) is a key indicator characterizing the maximum range of input light signals that a CMOS image sensor (CIS) can recognize. Some applications require very high dynamic range; a higher dynamic range allows for more vivid and richer representation of bright and dark areas in an image. In the design of CMOS image sensor (CIS) imaging, achieving high dynamic range (HDR) is currently a mainstream approach by using dual conversion gain (DCG) to read multiple frames and then synthesizing them.

[0003] A traditional pixel structure and control timing for high dynamic range (HDR) is implemented using dual conversion gain (DCG). Two modes, high conversion gain (HCG) and low conversion gain (LCG), are switched by toggling a DCG switch. Each mode reads a reset (rst) signal and an image (sig) signal, for a total of four signals. The applicant found that in the traditional readout scheme, two readout circuits process the HCG and LCG signals of one column of pixel bit lines respectively, meaning only one readout circuit is active at a time, wasting some readout circuitry and thus increasing readout time. Summary of the Invention

[0004] This application provides a dual-conversion-gain image reading method, imaging device, and readable storage medium to alleviate the problem of slow image reading speed.

[0005] In one aspect, this application provides a dual-conversion-gain image reading method, specifically, the image reading method includes:

[0006] Enable high conversion gain reset mode and control the readout circuit to quantize the high conversion gain reset signal;

[0007] Enable the high conversion gain image mode and control the readout circuit to quantize the high conversion gain image signal;

[0008] Enable the low conversion gain reset mode and control the readout circuit to quantize the low conversion gain reset signal;

[0009] Enable the low conversion gain image mode and control the readout circuit to quantize the low conversion gain image signal.

[0010] Optionally, after executing the control of the readout circuit to quantize the high conversion gain image signal and the low conversion gain image signal, the image reading method further includes, respectively, the following:

[0011] The readout circuit is controlled to store the quantization result.

[0012] Optionally, the readout circuit includes a comparator and a counter, and the readout circuit sequentially quantizes the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal using the same comparator and counter.

[0013] Optionally, the image reading method includes the following steps in the process of executing the control readout circuit to quantize the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal:

[0014] Based on the high conversion gain reset signal at the first input of the comparator, a high conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down.

[0015] When the state of the comparator's output signal flips, the counter is controlled to stop counting;

[0016] Based on the high conversion gain image signal at the first input terminal of the comparator, a high conversion gain ramp voltage is input to the second input terminal of the comparator, and the counter is controlled to count upwards.

[0017] When the state of the comparator's output signal flips, the counter is controlled to stop counting;

[0018] Based on the low conversion gain reset signal at the first input of the comparator, a low conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down.

[0019] When the state of the comparator's output signal flips, the counter is controlled to stop counting;

[0020] Based on the low conversion gain image signal at the first input terminal of the comparator, a low conversion gain ramp voltage is input to the second input terminal of the comparator, and the counter is controlled to count upwards.

[0021] When the state of the comparator's output signal flips, the counter is controlled to stop counting.

[0022] Optionally, before the readout circuit quantizes the high conversion gain reset signal and the low conversion gain reset signal, it further includes:

[0023] The conversion gain of the comparator in the readout circuit is cleared to zero.

[0024] Optionally, the step of enabling the high conversion gain reset mode may be preceded by:

[0025] The on-reset switch and the switching gain switch are reset by the floating diffusion node.

[0026] Optionally, the readout circuit further includes the following before quantizing the high conversion gain reset signal:

[0027] Disconnect the reset switch and the conversion gain switch to read the high conversion gain reset signal.

[0028] Optionally, the readout circuit further includes the following before quantizing the high conversion gain image signal:

[0029] Keep the reset switch and conversion gain switch off, turn them on, and then turn the transmission switch off to read the high conversion gain image signal.

[0030] Optionally, enabling the low conversion gain reset mode includes:

[0031] Keep the reset switch open and turn on the conversion gain switch to read the low conversion gain reset signal.

[0032] Optionally, the readout circuit further includes the following before quantizing the low-gain image signal:

[0033] Keep the reset switch off and the gain switching switch on, then turn the transmission switch off to read the low-gain image signal.

[0034] Optionally, the step of enabling the low conversion gain reset mode includes:

[0035] Increase the capacitance of the floating diffusion node to the preset capacitance range.

[0036] On the other hand, this application also provides an imaging device, specifically, the imaging device includes a control circuit and a pixel circuit and a readout circuit respectively connected to the control circuit, the readout circuit including a comparator;

[0037] The pixel circuit is configured to output a pixel signal according to the control signal of the control circuit and is connected to the readout circuit; the readout circuit is configured to quantize the pixel signal output by the pixel circuit through the comparator.

[0038] The control circuit is used to control the pixel circuit to output pixel signals and implement the image reading method described above.

[0039] Optionally, the pixel circuit includes a photodiode and a transmission switch, wherein the photodiode is connected to the floating diffusion node through the transmission switch; and the control terminal of the transmission switch is connected to the control circuit.

[0040] Optionally, the pixel circuit includes a supplementary capacitor, a reset switch, and a conversion gain switch. The control terminals of the reset switch and the conversion gain switch are connected to the control circuit. The first terminal of the supplementary capacitor is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor is connected between the reset switch and the conversion gain switch, and is connected to the floating diffusion node through the conversion gain switch.

[0041] Optionally, the readout circuit further includes a counter, the pixel circuit is connected to the first input terminal of the comparator, the second input terminal of the comparator receives a ramp signal, and the output terminal of the comparator is connected to the input terminal of the counter.

[0042] Optionally, the readout circuit further includes a memory, and the output of the counter is connected to the input of the memory.

[0043] Optionally, the pixel circuit includes a supplementary capacitor and a supplementary switch. The first terminal of the supplementary capacitor is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor is connected to the floating diffusion node through the supplementary switch. The control terminal of the supplementary switch is connected to the control circuit, and the control circuit is configured to control the supplementary switch to be turned on when a low conversion gain image mode is enabled.

[0044] On the other hand, this application also provides a readable storage medium, specifically, the readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the image reading method described above.

[0045] As described above, the dual-conversion-gain image reading method, imaging device, and readable storage medium provided in this application, through optimized gain signal quantization order, can use the same column of readout circuits to read in the order of high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal. Without changing the structure of the pixel circuit, the reading operation of a column of pixel signals can be completed, greatly reducing the reading time and speeding up the reading speed. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0047] Figure 1 This is a basic structural block diagram of an image sensor system.

[0048] Figure 2 This is a pixel circuit connection diagram in one embodiment of this application.

[0049] Figure 3 This is a pixel circuit connection diagram of a two-path photosensitive pixel shared structure in one embodiment of this application.

[0050] Figure 4 This is a flowchart of a dual-conversion-gain image reading method according to an embodiment of this application.

[0051] Figure 5 This is a block diagram of an imaging device according to an embodiment of this application.

[0052] Figure 6 This is a schematic diagram of the readout circuit in one embodiment of this application.

[0053] Figure 7 This is a circuit timing diagram of an image reading method according to an embodiment of this application.

[0054] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0056] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0057] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0058] The following detailed description of the contents of this application is provided in conjunction with the accompanying drawings. Figure 1 This is a basic structural block diagram of an image sensor system.

[0059] like Figure 1 As shown, the image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to the pixel array 101.

[0060] Functional logic unit 103 is connected to readout circuit 102 to perform logic control on the reading of pixel circuits. Readout circuit 102 and control circuit 104 are connected to status register 105 to implement readout control of pixel array 101. Pixel array 101 includes multiple pixel circuits arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by pixel array 101 are output to readout circuit 102 via column lines. In one embodiment, after each pixel circuit acquires image data, the image data is read out by readout circuit 102 using the readout mode specified by status register 105, and then transmitted to functional logic unit 103. In specific applications, readout circuit 102 may include analog-to-digital converter (ADC) circuit, amplification circuit, and others. In some application embodiments, status register 105 may include a programmed selection system to determine whether the readout system reads out in rolling shutter mode or global shutter mode. Functional logic unit 103 may store only image data or image data applied or processed through image effects. In one application example, readout circuit 102 may be located along readout column lines (e.g., ...). Figure 1As shown, image data is read out one line at a time, or various other methods may be used to read out image data. The operation of control circuit 104 can be determined by the current setting of status register 105. For example, control circuit 104 generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global exposure signal that allows all pixels of pixel array 101 to acquire their image data simultaneously through a single acquisition window. In some other applications, this shutter signal may be a rolling exposure signal, where each pixel row is read out continuously through the acquisition window.

[0061] First Embodiment

[0062] Figure 2 This is a pixel circuit connection diagram in one embodiment of this application. The pixel array of the image sensor contains multiple pixels arranged in rows and columns, such as... Figure 2 The pixel circuit shown includes a photosensitive pixel in each pixel circuit, comprising a photodiode (PD) and a transfer switch (TX). The transfer switch (TX) transfers electrons generated by the photodiode (PD) through the photoelectric effect to a floating diffusion point (FD). The dual conversion gain control circuit includes a conversion gain switch (DCG) and a supplementary capacitor (Cdcg), connected between a reset switch (RST) and the floating diffusion point (FD), used to enable the pixel circuit to operate in either a low conversion gain or high conversion gain mode according to a control signal.

[0063] The pixel signal is amplified by the source follower switch SF and output to the column line (pixelout output) via the row selection switch RS. In another specific embodiment, the pixel circuit may be a photosensitive pixel with a shared structure.

[0064] Second Embodiment

[0065] Figure 3 This is a pixel circuit connection diagram of a two-path photosensitive pixel shared structure in one embodiment of this application.

[0066] like Figure 3 As shown, photodiode PD1 and transmission switch TX1, along with photodiode PD2 and transmission switch TX2, constitute a shared structure of photosensitive pixels, sharing and connecting to the floating diffusion point FD. Using a shared structure in the pixel circuit reduces the number of switches in the pixel circuit, thus reducing the chip design area. Understandably, without changing the pixel circuit design area, the area of ​​the photosensitive region can be increased, thereby improving the light sensitivity of the pixel circuit and enhancing its performance. The figures and embodiments provided in this application are not limited to a two-way shared photosensitive pixel mode. In some specific embodiments, a four-way shared photosensitive pixel structure design can be adopted, such as a photosensitive pixel sharing unit consisting of PD1 and TX1, PD2 and TX2, PD3 and TX3, and PD4 and TX4 connected in a four-way shared structure and sharing the floating diffusion point FD.

[0067] Please continue to refer to this. Figure 2 The supplementary capacitor Cdcg can be the device capacitor or the parasitic capacitance to ground at the connection point of the reset switch RST and the conversion gain switch DCG. Figure 2 In one embodiment, the supplementary capacitor Cdcg is a device capacitor, with the other terminal connected to voltage VC. In another embodiment, the supplementary capacitor Cdcg is the parasitic capacitance to ground at the connection point of the reset switch RST and the switching gain switch DCG, and the other terminal of the capacitor can be grounded.

[0068] Third Embodiment

[0069] In another embodiment, the pixel circuit includes a supplementary capacitor and a supplementary switch. A first terminal of the supplementary capacitor is grounded or connected to a fixed voltage source, and a second terminal of the supplementary capacitor is connected to the floating diffusion node via the supplementary switch. The control terminal of the supplementary switch is connected to a control circuit configured to control the supplementary switch to conduct when a low conversion gain image mode is enabled.

[0070] When entering the low conversion gain reset mode, the control circuit can control the supplementary switch to turn on, so that the supplementary capacitor is connected in parallel to the floating diffusion node to increase the capacitance at the floating diffusion node.

[0071] Fourth embodiment

[0072] This application provides a dual-conversion-gain image reading method. Figure 4 This is a flowchart of a dual-conversion-gain image reading method according to an embodiment of this application.

[0073] Please see Figure 4 In one embodiment, the image reading method includes:

[0074] S10: Enables high conversion gain reset mode and controls the readout circuit to quantize the high conversion gain reset signal.

[0075] The image sensor can be controlled to disconnect the reset switch and the conversion gain switch to enable the high conversion gain reset mode. First, the high conversion gain reset signal is read.

[0076] In one embodiment, the process may include the following steps before performing the step of enabling the high conversion gain reset mode:

[0077] The on-reset switch and the switching gain switch are reset by the floating diffusion node.

[0078] Resetting the floating diffusion node before quantizing an image signal readout ensures the accuracy of the readout circuit's quantization.

[0079] In one embodiment, the comparator's conversion gain can be cleared to zero before the readout circuit quantizes the high conversion gain reset signal. The readout circuit includes a comparator and a counter, and the step of controlling the readout circuit to quantize the high conversion gain reset signal may include:

[0080] Based on the high conversion gain reset signal at the first input of the comparator, a high conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down.

[0081] When the state of the comparator's output signal flips, the control counter stops counting.

[0082] The reset signal level can be converted from analog to digital by counting downwards, thus quantizing the reset signal of the image sensor.

[0083] S20: Enables high conversion gain image mode and controls the readout circuit to quantize the high conversion gain image signal.

[0084] The control image sensor keeps the reset switch and conversion gain switch off, turns them on, and then disconnects the transmission switch to guide the charge from the photodiode to the floating diffusion node, entering a high conversion gain image mode, thereby enabling the readout circuit to read the high conversion gain image signal.

[0085] In one embodiment, enabling a high conversion gain image mode can turn on a transmission switch in the pixel circuit; then, after a preset time, the transmission switch is turned off. The step of executing the control readout circuit to quantize the high conversion gain image signal includes:

[0086] Based on the high conversion gain image signal at the first input of the comparator, a high conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count upwards.

[0087] When the state of the comparator's output signal flips, the control counter stops counting.

[0088] A short-time conduction transmission switch allows the charge from the photodiode to be directed to a floating diffusion node, enabling a high-conversion-gain image mode. An up-counting method can then be used for A / D conversion of the image signal level, achieving image signal quantization from the image sensor.

[0089] S30: Enables low conversion gain reset mode and controls the readout circuit to quantize the low conversion gain reset signal.

[0090] In one embodiment, the step of enabling the low conversion gain reset mode includes:

[0091] Increase the capacitance of the floating diffusion node to the preset capacitance range.

[0092] The image sensor can be controlled to keep the reset switch open and the conversion gain switch open, with the parasitic capacitance or device capacitance between the reset switch and the conversion gain switch connected to the floating diffusion node. By increasing the capacitance of the floating diffusion node, a low conversion gain reset mode is enabled, and a high conversion gain reset signal is read. In another embodiment, the capacitance of the floating diffusion node can also be increased by connecting other capacitors.

[0093] In one embodiment, the comparator's conversion gain can be cleared to zero before the readout circuit quantizes the low conversion gain reset signal. The step of controlling the readout circuit to quantize the low conversion gain reset signal may include:

[0094] Based on the low conversion gain reset signal at the first input of the comparator, a low conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down.

[0095] When the state of the comparator's output signal flips, the control counter stops counting.

[0096] The reset signal level can be converted from analog to digital by counting downwards, thus quantizing the reset signal of the image sensor.

[0097] S40: Enables low conversion gain image mode and controls the readout circuit to quantize the low conversion gain image signal.

[0098] The control image sensor keeps the reset switch off and the conversion gain switch on. After the switch is turned on, the transmission switch is turned off to guide the residual charge of the photodiode into the floating diffusion node, entering a low conversion gain image mode, thereby enabling the readout circuit to read the high conversion gain image signal.

[0099] In one embodiment, enabling a low conversion gain image mode can turn on a transmission switch in the pixel circuit; then, after a preset time, the transmission switch is turned off. The step of controlling the readout circuit to quantize the low conversion gain image signal includes:

[0100] Based on the low conversion gain image signal at the first input of the comparator, a low conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count upwards.

[0101] When the state of the comparator's output signal flips, the control counter stops counting.

[0102] A short-time conduction transmission switch can direct residual charge from the photodiode to a floating diffusion node, entering a low conversion gain image mode. An A / D conversion of the image signal level can be performed using an up-counting method, achieving image signal quantization from the image sensor.

[0103] In one embodiment, after the control readout circuit quantizes the high conversion gain image signal and the low conversion gain image signal, it further includes:

[0104] The readout circuit is controlled to store the quantization results.

[0105] After high-conversion-gain and low-conversion-gain quantization is completed, the quantization results are stored so that the functional logic unit can easily read them when data needs to be processed.

[0106] In this embodiment, the readout circuit sequentially quantizes the high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal using the same comparator and counter. By optimizing the gain signal quantization order, the same column of readout circuits can read the quantization results in the order of high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal. This allows for the reading of a column of pixel signals without altering the pixel circuit structure, significantly reducing reading time and accelerating the reading speed. It should be noted that the method provided in this application can also be used in traditional two-column readout circuits that read high conversion gain and low conversion gain quantization signals separately.

[0107] Fifth Embodiment

[0108] This application also provides an imaging device. Figure 5 This is a block diagram of an imaging device according to an embodiment of this application.

[0109] Please refer to Figure 5 In one embodiment, the imaging device includes a control circuit 104 and a pixel circuit 30 and a readout circuit 102, which are respectively connected to the control circuit 104. The readout circuit 102 includes a comparator (not shown in the figure).

[0110] The pixel circuit 30 is configured to output a pixel signal according to the control signal of the control circuit 104 and is connected to the readout circuit 102. The readout circuit 102 is configured to quantize the pixel signal output by the pixel circuit 30 using a comparator.

[0111] The control circuit 104 is used to implement the image reading method described above.

[0112] By optimizing the gain signal quantization sequence, the same column of readout circuits can read the signal in the order of high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal. Without changing the structure of the pixel circuit, the reading operation of a column of pixel signals can be completed, greatly reducing the reading time and speeding up the reading process.

[0113] Please also refer to Figure 2 and Figure 5 In one embodiment, the pixel circuit 30 includes a photodiode PD and a transmission switch TX. The photodiode PD is connected to the floating diffusion node FD through the transmission switch TX. The control terminal of the transmission switch TX is connected to the control circuit 104.

[0114] In one embodiment, the pixel circuit 30 further includes a supplementary capacitor Cdcg, a reset switch RST, and a conversion gain switch DCG. The control terminals of the reset switch RST and the conversion gain switch DCG are connected to the control circuit 104. The first terminal of the supplementary capacitor Cdcg is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor Cdcg is connected between the reset switch RST and the conversion gain switch DCG. The floating diffusion node FD is connected through the conversion gain switch DCG.

[0115] Figure 6 This is a schematic diagram of the readout circuit in one embodiment of this application.

[0116] like Figure 6 As shown, in one embodiment, the readout circuit further includes a counter 502 and a memory 503. The pixel circuit is connected to the first input terminal Vinn of comparator 501, and the second input terminal Vinp of comparator 501 receives the ramp signal vramp. The output terminal Vout of comparator 501 is connected to the input terminal of counter 502. The output terminal of counter 502 is connected to memory 503. Comparator 501 can be cleared by closing the conversion gain clear switch cmp_az.

[0117] In one embodiment, the pixel circuit includes a supplementary capacitor and a supplementary switch. The first terminal of the supplementary capacitor is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor is connected to a floating diffusion node through the supplementary switch. The control terminal of the supplementary switch is connected to a control circuit, which is configured to control the supplementary switch to turn on when a low conversion gain image mode is enabled.

[0118] Sixth Embodiment

[0119] Figure 7 This is a circuit timing diagram of an image reading method according to an embodiment of this application. Please refer to... Figure 2 , Figure 5 and Figure 7 The specific timing sequence is as follows:

[0120] At time t0, the column selection switch RS is turned on, the row selection signal rowsel is set to high level, and the pixel circuit is connected to the first input terminal of the comparator.

[0121] At time t1, the conversion gain clearing switch cmp_az is turned on, shorting the two input terminals and the output terminal of the comparator together, and the comparator begins to clear to zero.

[0122] At time t2, the reset switch rst and the conversion gain switch dcg are disconnected to obtain the high conversion gain reset signal HCGrst.

[0123] At time t3, the conversion gain clear switch cmp_az is disconnected, allowing the first input of the comparator to sample the high conversion gain reset signal HCG rst through capacitive coupling.

[0124] At time t4, the enable signal cmp_integ_en is set to high level, and at the same time, the ramp voltage vramp begins to decrease. This signal is capacitively coupled into the second input terminal of the comparator.

[0125] At time t5, the enable signal count_en is set to high level, and the counter starts counting down. When the signals at the two input terminals of the comparator overlap, the state of the comparator flips, the counter stops counting, and the reading of the high conversion gain reset signal HCGrst is completed.

[0126] At time t6, the enable signal count_en is set to low, and at time t7, the enable signal cmp_integ_en is set to low, and the ramp voltage vramp returns to the reference state.

[0127] From time t8 to t9, the transmission switch tx is turned on, the control signal is set to high level, and the photodiode PD is connected to the floating diffusion node FD. Under the action of potential difference, the photogenerated charge drifts from the photodiode PD to the floating diffusion node FD, which reduces the node potential of the floating diffusion node FD, and the pixel circuit obtains the high conversion gain image signal HCG sig.

[0128] At time t10, the enable signal cmp_integ_en is set to high, and the ramp voltage vramp begins to decrease.

[0129] At time t11, the enable signal count_en is set to high level, causing the counter to start counting upwards. When the signals at the two input terminals of the comparator overlap, the state of the comparator flips, the counter stops counting, and the reading of the high conversion gain image signal HCG sig is completed. At this point, the quantization of the two signals of high conversion gain HCG is finished, the counter obtains the count value of the pixel signal, and writes the value into the memory.

[0130] At time t12, the enable signal count_en is set to low level, and at time t13, the enable signal cmp_integ_en is set to low level, and the ramp voltage vramp returns to the reference state.

[0131] At time t14, the conversion gain switch dcg is turned on, the conversion gain control signal is set to high level, and the additional supplementary capacitor Cx increases the floating diffusion node FD capacitor and the potential rises. At this time, the pixel circuit receives the low conversion gain reset signal LCGrst.

[0132] At times t15 to t16, the conversion gain clearing switch cmp_az is turned on, shorting the two input terminals and the output terminal of the comparator together, and the comparator begins to clear to zero.

[0133] After time t16, close the conversion gain reset switch cmp_az, so that the comparator input can sample the low conversion gain reset signal LCG rst;

[0134] At time t17, the enable signal cmp_integ_en is set to high level, and the ramp voltage vramp begins to decrease.

[0135] At time t18, the enable signal count_en is set to high level, causing the counter to start counting down. When the signals at the two input terminals of the comparator overlap, the state of the comparator flips, the counter stops counting, and the reading of the low conversion gain reset signal LCG rst is completed.

[0136] At time t19, the enable signal count_en is set to low level, and at time t20, the enable signal cmp_integ_en is set to low level, and the ramp voltage vramp returns to the reference state.

[0137] From time t21 to t22, the transmission switch tx is turned on, the control signal is set to high level, the photodiode PD is connected to the floating diffusion node FD, the remaining charge of the photodiode PD when the control signal was set to high level in the previous time and the extra charge generated by exposure between the two high-level control signal operations are transferred to the floating diffusion node FD, causing the potential of the floating diffusion node FD to drop, and thus obtaining the low conversion gain image signal LCG sig;

[0138] At time t23, the enable signal cmp_integ_en is set to high level, and the ramp voltage vramp begins to decrease.

[0139] At time t24, the enable signal count_en is set to a high level, causing the counter to start counting upwards. When the signals at the two input terminals of the comparator overlap, the state of the comparator flips, the counter stops counting, and the reading of the low conversion gain image signal LCG sig is completed. At this point, the quantization of the two signals of the low conversion gain LCG is finished, the counter obtains the count value of the pixel signal, and writes the value into the memory.

[0140] At time t25, the enable signal count_en is set to low level, and at time t26, the enable signal cmp_integ_en is set to low level, and the ramp voltage vramp returns to the reference state.

[0141] At time t27, the reset switch rst is closed, and the reset signal is set to high level;

[0142] At time t28, the column select switch RS is disconnected, and the row select signal rowsel is set to low. This completes one quantization cycle of the pixel output.

[0143] Seventh Embodiment

[0144] On the other hand, this application also provides a readable storage medium, optionally storing a computer program that, when executed by a processor, implements the steps of the image reading method described above.

[0145] As described above, the dual-conversion-gain image readout method, imaging apparatus, and readable storage medium provided in this application, through optimized gain signal quantization sequence, allow the same column of readout circuits to read the quantization results in the order of high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal. This allows for the reading operation of a column of pixel signals without altering the pixel circuit structure, significantly reducing readout time and accelerating readout speed. It should be noted that the method provided in this application can also be used in conventional two-column readout circuits that read high conversion gain and low conversion gain quantization signals separately.

[0146] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for reading images with dual conversion gain, characterized in that, include: Enable high conversion gain reset mode and control the readout circuit to quantize the high conversion gain reset signal; Enable the high conversion gain image mode and control the readout circuit to quantize the high conversion gain image signal; Enable the low conversion gain reset mode and control the readout circuit to quantize the low conversion gain reset signal; Enable the low conversion gain image mode and control the readout circuit to quantize the low conversion gain image signal; Before the readout circuit completes the quantization of the low conversion gain image signal, it also includes: Keep the reset switch off and the conversion gain switch on, then turn the transmission switch off to read the low conversion gain image signal; The readout circuit is a column readout circuit, which sequentially quantizes the high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal of a column of pixels using the same comparator and counter.

2. The method as described in claim 1, characterized in that, The control circuit for quantizing the high-conversion-gain image signal and the low-conversion-gain image signal further includes: The readout circuit is controlled to store the quantization result.

3. The method as described in claim 1, characterized in that, The steps of quantizing the high conversion gain reset signal, high conversion gain image signal, low conversion gain reset signal, and low conversion gain image signal by the control readout circuit include: Based on the high conversion gain reset signal at the first input of the comparator, a high conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down. When the state of the comparator's output signal flips, the counter is controlled to stop counting; Based on the high conversion gain image signal at the first input terminal of the comparator, a high conversion gain ramp voltage is input to the second input terminal of the comparator, and the counter is controlled to count upwards. When the state of the comparator's output signal flips, the counter is controlled to stop counting; Based on the low conversion gain reset signal at the first input of the comparator, a low conversion gain ramp voltage is input to the second input of the comparator, and the counter is controlled to count down. When the state of the comparator's output signal flips, the counter is controlled to stop counting; Based on the low conversion gain image signal at the first input terminal of the comparator, a low conversion gain ramp voltage is input to the second input terminal of the comparator, and the counter is controlled to count upwards. When the state of the comparator's output signal flips, the counter is controlled to stop counting.

4. The method as described in claim 1, characterized in that, Before the readout circuit quantizes the high conversion gain reset signal and the low conversion gain reset signal, it further includes the following: The comparator in the readout circuit is cleared to zero.

5. The method as described in claim 1, characterized in that, The step of activating the high conversion gain reset mode is preceded by: The on-reset switch and the switching gain switch are reset by the floating diffusion node.

6. The method as described in claim 5, characterized in that, Before the readout circuit completes the quantization of the high conversion gain reset signal, it also includes: Disconnect the reset switch and the conversion gain switch to read the high conversion gain reset signal.

7. The method as described in claim 6, characterized in that, Before the readout circuit completes the quantization of the high conversion gain image signal, it also includes: Keep the reset switch and conversion gain switch off, turn them on, and then turn the transmission switch off to read the high conversion gain image signal.

8. The method as described in claim 7, characterized in that, The activation of the low conversion gain reset mode includes: Keep the reset switch open and turn on the conversion gain switch to read the low conversion gain reset signal.

9. The method as described in claim 1, characterized in that, The step of enabling the low conversion gain reset mode includes: Increase the capacitance of the floating diffusion node to the preset capacitance range.

10. An imaging device, characterized in that, It includes a control circuit and a pixel circuit and a readout circuit respectively connected to the control circuit, wherein the readout circuit includes a comparator; The pixel circuit is configured to output pixel signals according to the control signals of the control circuit and is connected to the readout circuit; The readout circuit is configured to quantize the pixel signal output by the pixel circuit through the comparator; The control circuit is used to control the pixel circuit to output pixel signals and implement the image reading method as described in any one of claims 1-9.

11. The imaging apparatus as claimed in claim 10, characterized in that, The pixel circuit includes a photodiode and a transmission switch. The photodiode is connected to the floating diffusion node through the transmission switch. The control terminal of the transmission switch is connected to the control circuit.

12. The imaging apparatus as claimed in claim 10, characterized in that, The pixel circuit includes a supplementary capacitor, a reset switch, and a conversion gain switch. The control terminals of the reset switch and the conversion gain switch are connected to the control circuit. The first terminal of the supplementary capacitor is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor is connected between the reset switch and the conversion gain switch, and is connected to the floating diffusion node through the conversion gain switch.

13. The imaging apparatus as claimed in claim 10, characterized in that, The readout circuit further includes a counter, the pixel circuit is connected to the first input terminal of the comparator, the second input terminal of the comparator receives a ramp voltage, and the output terminal of the comparator is connected to the input terminal of the counter.

14. The imaging apparatus as claimed in claim 13, characterized in that, The readout circuit also includes a memory, and the output of the counter is connected to the input of the memory.

15. The imaging apparatus as claimed in claim 10, characterized in that, The pixel unit includes a supplementary capacitor and a supplementary switch. The first terminal of the supplementary capacitor is grounded or a fixed voltage source. The second terminal of the supplementary capacitor is connected to the floating diffusion node through the supplementary switch. The control terminal of the supplementary switch is connected to the control circuit. The control circuit is configured to control the supplementary switch to be turned on when the low conversion gain image mode is enabled.

16. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the image reading method as described in any one of claims 1 to 15.

Images