Memory device, method of manufacturing the same, and electronic device including the memory device

Abstract

A memory device, a manufacturing method thereof, and an electronic device including the memory device are disclosed. The memory device can include: a plurality of device layers vertically stacked on a substrate, each device layer including an array of active regions of select transistors, the array including rows in a first direction and columns in a second direction, the active regions including a lower source / drain region, a channel portion, and an upper source / drain region; a plurality of bit lines arranged in the second direction, each bit line extending in the first direction along a corresponding row; a plurality of word line layers vertically stacked and corresponding to the device layers, each word line layer including a plurality of word lines arranged in the first direction, each word line extending in the second direction to at least partially surround the channel portions in a corresponding column of the device layers; a plurality of sub-bit lines vertically extending from each bit line, each sub-bit line electrically connected to the lower source / drain regions of a corresponding row in each device layer above the bit line; and a storage element electrically connected to the upper source / drain regions of each active region.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically to memory devices, methods of manufacturing the same, and electronic devices including such memory devices. Background Technology

[0002] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are not easily miniaturized further. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to miniaturize than horizontal devices. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a memory device with improved integration density, a method of manufacturing the same, and an electronic device including such a memory device.

[0004] According to one aspect of this disclosure, a memory device is provided, comprising: a plurality of device layers stacked on a substrate in a vertical direction relative to the substrate, each device layer including an array of active regions of selection transistors, wherein the active regions in the array are arranged in rows in a first direction and in columns in a second direction, the active regions including lower source / drain regions and upper source / drain regions at different heights relative to the substrate, and a channel portion between the lower source / drain regions and the upper source / drain regions; a plurality of bit lines arranged in the second direction, each of the plurality of bit lines extending along a corresponding row in the array in the first direction; and in the vertical direction... A plurality of word line layers stacked and corresponding to the plurality of device layers, wherein each of the plurality of word line layers includes a plurality of word lines arranged in a first direction, each of the plurality of word lines extending in a second direction to at least partially surround a channel portion of an active region in a corresponding column of a corresponding device layer of the word line layer; a plurality of sub-bit lines extending vertically from each of the plurality of bit lines, each of the plurality of sub-bit lines being electrically connected to a lower source / drain region of an active region in a corresponding row of a bit line in a device layer above the bit line; and a memory element electrically connected to an upper source / drain region of each active region.

[0005] According to another aspect of this disclosure, a method for manufacturing a memory device is provided, comprising: forming a plurality of device layers on a substrate, each device layer including a first source / drain layer, a channel defining layer, and a second source / drain layer sequentially stacked in a vertical direction relative to the substrate, and an isolation defining layer disposed between each device layer; forming a plurality of vertically extending first processing channels in the plurality of device layers, the plurality of first processing channels being arranged in a first direction and extending along a second direction intersecting the first direction, the bottom of each first processing channel being defined by a first source / drain layer in the lowest device layer of the plurality of device layers; and, via the first processing channels, causing the channel defining layer in each device layer to be disposed in a first source / drain layer in a second source / drain layer in a third ... An end in one direction is recessed in the first direction relative to the corresponding ends of the first source / drain layer and the second source / drain layer, and a first gate position holding layer is formed in the resulting recess; a portion of the isolation defining layer adjacent to the first processing channel is replaced with an isolation layer via the first processing channel; the second source / drain layer in each device layer exposed in the first processing channel is recessed in the first direction relative to the first source / drain layer via the first processing channel; on the first source / drain layer in the lowest device layer exposed at the bottom of the first processing channel, a sub-bit line is formed along the sidewall of the first processing channel, and the sub-bit line contacts the first source / drain layer in each device layer exposed in the first processing channel; in the plurality of devices A plurality of vertically extending second processing channels are formed in the device layers. These second processing channels are alternately arranged with the first processing channels in a first direction and extend along a second direction, respectively. The device layers form a stepped structure at the second processing channels. Through the second processing channels, the end of the channel defining layer in each device layer is recessed in the first direction relative to the corresponding ends of the first and second source / drain layers, forming a second gate position holding layer in the resulting recess. Through the second processing channels, the remaining portion of the isolation defining layer near the second processing channel is replaced with an isolation layer. A plurality of third processing channels are formed penetrating the plurality of device layers. Processing channels are arranged in a second direction and extend along a first direction respectively; a channel layer is grown on the sidewalls exposed in the third processing channel of each device layer by selective epitaxial growth; a plurality of fourth processing channels are formed through the plurality of device layers, the plurality of fourth processing channels being alternately arranged with the third processing channels in the second direction and extending along the first direction respectively; a channel defining layer and a first gate position holding layer and a second gate position holding layer are removed via the fourth processing channels; and word line layers corresponding to each device layer are formed on the substrate, each word line layer including a plurality of word lines extending along the second direction to at least partially surround the portion of the channel layer between the first source / drain layer and the second source / drain layer.

[0006] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned storage device.

[0007] According to embodiments of the present disclosure, a novel three-dimensional (3D) memory device architecture is provided. In this 3D architecture, the select transistors in each memory cell are vertically stacked, which provides greater design space, reduces footprint, and enhances device performance. The vertically stacked transistors can be connected to corresponding bit lines using sub-bit lines. In the manufacturing process according to embodiments of the present disclosure, various self-aligned processes can be used, thereby reducing area, space, cost, and increasing yield. Attached Figure Description

[0008] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1(a) schematically shows a partial perspective view of a select transistor array in a memory device according to an embodiment of the present disclosure, and Figure 1(b) schematically shows a partial perspective view of the select transistor array in the memory device according to the embodiment after stripping the word lines and the active region.

[0010] Figures 2 to 46(b) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown;

[0011] Figure 47 An equivalent circuit diagram of a storage device according to an embodiment of the present disclosure is schematically shown.

[0012] in, Figure 3(a) , 25(a) Figures 33(a), 41(a), and 45(a) are top views. Figure 3(a) shows the position of line AA′, Figure 25(a) shows the position of line BB′, and Figure 33(a) shows the positions of lines DD′ and EE′.

[0013] Figure 2 , 3(b) Figures 4 to 24, 25(b), 33(b), 40(a), 41(b), 42(a), and 44(a) are cross-sectional views along line AA′. Figure 25(b) shows the position of line CC′.

[0014] Figure 25(c) , 26 Figures 27, 28(a), 29, 30(a), 31(a), 32(a), 33(c), 34(a), 35(a), 36(a), 37(a), 38(a), 39(a), and 40(b) are cross-sectional views along line BB′.

[0015] Figure 25(d) , 28(b)Figures 30(b), 31(b), 32(b), 33(d), 34(b), 35(b), 36(b), 37(b), 39(b), and 40(c) are cross-sectional views along line CC′.

[0016] Figure 33(e) , 34(c) Figures 35(c), 41(c), and 42(b) are cross-sectional views along line DD′.

[0017] Figure 33(f) , 34(d) Figures 35(d), 41(d), 43, 44(b), 45(b), 46(a), and 46(b) are cross-sectional views along line EE′.

[0018] Figure 37(c) is a cross-sectional view along the dotted line in Figure 37(a), Figure 38(b) is a cross-sectional view along the dotted line in Figure 38(a), Figure 42(c) is a cross-sectional view corresponding to Figure 37(c), and Figure 42(d) is a cross-sectional view corresponding to Figure 38(b).

[0019] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0020] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0021] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0022] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0023] Figure 1(a) schematically shows a partial perspective view of a select transistor array in a memory device according to an embodiment of the present disclosure, and Figure 1(b) schematically shows a partial perspective view of the select transistor array in the memory device according to the embodiment, after stripping the word lines and the active region.

[0024] like Figure 1(a) and 1(b) As shown, a memory device according to an embodiment may include a three-dimensional (3D) array 100 of select transistors and memory elements electrically connected to the select transistors (e.g., see capacitor 1087 in FIG. 46(a), or magnetic tunnel junction 1089 in FIG. 46(b)). Such a memory device may include dynamic random access memory (DRAM) or magnetic random access memory (MRAM). Each select transistor and the memory element electrically connected thereto may constitute a memory cell (MC).

[0025] The figure schematically illustrates some of the selection transistors in the 3D array 100, such as the lower-layer selection transistors TR_1-1-1, TR_1-2-1, TR_2-1-1, TR_2-2-1 and the upper-layer selection transistors TR_1-1-2, TR_1-2-2, TR_2-1-2, TR_2-2-2. Although only two layers of the 3D array 100 are shown here, this disclosure is not limited to this and may include more layers, such as L layers (L is a natural number greater than or equal to 2). Additionally, the figure shows each layer comprising a 2×2 selection transistor array. This is merely for illustrative purposes. In fact, each layer may include, for example, an M (rows) × N (columns) selection transistor array (M and N are natural numbers greater than or equal to 2). Therefore, the 3D array 100 may include M×N×L selection transistors, where each selection transistor can be represented as TR_i-jk (1≤i≤M, i can be called row index; 1≤j≤N, j can be called column index; 1≤k≤L, k can be called layer index).

[0026] In a 3D array, select transistors can be addressed via word lines and bit lines. Multiple bit lines BL_1, BL_2, ..., BL_i, ..., BL_M (only two are shown in the figure) extending along a first direction can be arranged in a second direction to correspond to M rows respectively. As described below, each bit line BL_i can be self-aligned to its corresponding row (row i). Furthermore, word lines can form the gate electrodes of the select transistors, and therefore can have L layers (only two are shown in the figure) to correspond to each layer of select transistors. Within each layer, multiple bit lines extending along the second direction can be arranged in the first direction to correspond to N columns respectively. For example, in the first layer, there are bit lines WL_1-1, WL_2-1, ..., WL_j-1, ..., WL-N-1 (only two of them are shown in the figure); in the second layer, there are bit lines WL_1-2, WL_2-2, ..., WL_j-2, ..., WL-N-2 (only two of them are shown in the figure); ...; in the k-th layer, there are bit lines WL_1-k, WL_2-k, ..., WL_j-k, ..., WL-Nk (not shown in the figure); ...; in the L-th layer, there are bit lines WL_1-L, WL_2-L, ..., WL_j-L, ..., WL-NL (not shown in the figure). The bit lines in each layer can be substantially coplanar.

[0027] According to embodiments of this disclosure, the bit lines can be located at the bottom of the array and can be substantially coplanar. From each bit line BL_i, multiple sub-bit lines Sub_BL_i-1, Sub_BL_i-2, ..., Sub_BL_i-j, ..., Sub_BL_i-N can extend vertically to correspond to N columns respectively, and thus connect to the selection transistors (more specifically, the lower source / drain regions described below) in the corresponding rows (i-th row) of the upper layers in each column (columns 1 to N). Only two sub-bit lines Sub_BL_1-1 and Sub_BL_1-2 extending from bit line BL_1 and two sub-bit lines Sub_BL_2-1 and Sub_BL_2-2 extending from bit line BL_2 are shown in the figure.

[0028] Therefore, each selection transistor TR_i-jk can be electrically connected to the corresponding bit line BL_i via the sub-bit line Sub_BL_i-j, and its gate electrode is defined by the corresponding word line WL_j-k, and thus electrically connected between the word line WL_j-k and the bit line BL_i. Each selection transistor TR_i-jk in the 3D array can be addressed via the word line BL_i (1≤i≤M) and the bit line WL_j-k (1≤j≤N, 1≤k≤L). Some contacts are schematically shown in Figure 1(a), such as the contacts to bit lines BL_1, BL_2, and the contacts to word lines WL_1-1, WL_1-2. Electrical signals can be applied through these contacts to address and access the selection transistors. Note that the contacts to word lines WL_2-1, WL_2-2 are not shown for clarity.

[0029] Sub-bit lines can be positioned on one side of the corresponding column. For example, as shown, for each column (column j), sub-bit lines Sub_BL_i-j (1≤i≤M) extending from each bit line can be electrically connected from one side of that column (column j) in a first direction to the select transistor in that column. Sub-bit lines Sub_BL_i-j (1≤i≤M) corresponding to the same column (column j) can be substantially aligned (e.g., substantially coplanar) in a second direction.

[0030] Furthermore, as shown in the figure, sub-line parameters can be set in pairs. For example, for a certain column (e.g., column j), its corresponding sub-line Sub_BL_i-j (1≤i≤M) can be set on the first side of the first direction in that column (column j); while for the adjacent column (e.g., column j+1 or column j-1), its corresponding sub-line Sub_BL_i-(j+1) or Sub_BL_i-(j-1) (1≤i≤M) can be set on the second side of the first direction in that column (column j+1 or column j-1), opposite to the first side. Thus, sub-line parameters can be set in pairs between adjacent columns, every other column. For example, between adjacent columns (2n-1) and 2n (where n is a natural number greater than 0), sub-line Sub_BL_i-(2n-1) and Sub_BL_i-2n (1≤i≤M) can be set; between adjacent columns (2n) and (2n+1), no sub-line can be set; in addition, between adjacent columns (2n+1) and (2n+1), sub-line Sub_BL_i-(2n+1) and Sub_BL_i-2(n+1) (1≤i≤M) can be set; and so on.

[0031] Each sub-bit line Sub_BL_i-j may include a vertical extension portion VP extending vertically from the corresponding bit line BL_i and a lateral extension portion extending laterally from the vertical extension portion VP toward the corresponding selection transistor TR_i-jk. The vertical extension portions VP of the paired sub-bit lines Sub_BL_i-(2n-1) and Sub_BL_i-2n may face each other, while their respective lateral extension portions HP may extend in opposite directions.

[0032] The selected transistor TR_i-jk can be a vertical device. A vertical device can include active regions disposed on a substrate in a vertical direction (generally perpendicular to the substrate surface), including source / drain regions (which may be referred to as the upper source / drain region and the lower source / drain region, respectively) disposed at different vertical heights (e.g., at the upper and lower ends), and a channel portion located between the upper and lower source / drain regions. A conductive path can be formed between the upper and lower source / drain regions through a channel region formed in the channel portion. Active regions in the same layer can be substantially coplanar (e.g., on a plane parallel to the surface of the substrate). Corresponding rows and columns in different layers can be substantially aligned with each other in the vertical direction (e.g., substantially coplanar).

[0033] Furthermore, the active region of each select transistor TR_i-jk may include a lower source / drain layer S / C_L, an upper source / drain layer S / C_U, and a channel layer CH including a portion extending between the lower source / drain layer S / C_L and the upper source / drain layer S / C_U (defining the aforementioned "channel portion"). The lower source / drain region may include the lower source / drain layer S / C_L, for example, defined within the lower source / drain layer S / C_L by doping. Similarly, the upper source / drain region may include the upper source / drain layer S / C_U, for example, defined within the upper source / drain layer S / C_U by doping. The lower source / drain layers S / C_L of the active regions of the select transistors in rows M and columns N of each layer may be substantially coplanar, and the upper source / drain layers S / C_U may be substantially coplanar.

[0034] In the active regions of each selectable transistor TR_i-jk, the channel layer CH can be an epitaxial layer grown on the sidewalls (in the second direction) of the lower source / drain layer S / C_L and the upper source / drain layer S / C_U. The channel layer CH can extend from the sidewall of the lower source / drain layer S / C_L to the sidewall of the upper source / drain layer S / C_U, thus having a portion extending between the lower source / drain layer S / C_L and the upper source / drain layer S / C_U (defining a channel portion). The channel layer CH can also extend to the sidewalls of the sub-bit lines and bit lines, for example, when the sub-bit lines and bit lines include (doped) semiconductor material. Thus, when viewed from the first direction, the active region can be C-shaped, that is, the shape in which the lower source / drain layer S / C_L and the upper source / drain layer S / C_U extend from the channel layer CH.

[0035] As shown in the figure, the C-shapes of the active regions of the select transistors in adjacent rows can be opposite each other. For example, for a certain row (e.g., row i), the channel layer CH of the active region of the select transistor can be disposed on the first side of the lower source / drain layer S / C_L and the upper source / drain layer S / C_U in the second direction; while in the adjacent row (e.g., row i+1 or row i-1), the channel layer CH of the active region of the select transistor can be disposed on the second side of the lower source / drain layer S / C_L and the upper source / drain layer S / C_U in the second direction opposite to the first side. Thus, for each pair of adjacent columns, the channel layer CH in the respective active region can be disposed on the opposite sidewalls of the corresponding lower source / drain layer S / C_L and upper source / drain layer S / C_U.

[0036] In the active region of each select transistor TR_i-jk, the portion of the channel layer CH extending between the lower source / drain layer S / C_L and the upper source / drain layer S / C_U (the channel portion) may be recessed in the first direction relative to the corresponding ends of the lower source / drain layer S / C_L and the upper source / drain layer S / C_U. This recess provides space for the word line to bypass the channel portion and extend continuously in the second direction.

[0037] In the active region of each select transistor TR_i-jk, one end of the lower source / drain layer S / C_L in a first direction (which may be referred to as "the first end of (lower source / drain layer S / C_L")) may extend in the first direction relative to the corresponding end of the upper source / drain layer S / C_U (which may be referred to as "the first end of (upper source / drain layer S / C_U)") to connect to the corresponding sub-bit line, particularly the lateral extension of the sub-bit line. The lower source / drain layer S / C_L may be substantially aligned (e.g., substantially coplanar) with the lateral extension of the corresponding sub-bit line. The first ends of the lower source / drain layer S / C_L of each select transistor in the same column (e.g., column j) may be substantially aligned (e.g., substantially coplanar), and the first ends of the upper source / drain layer S / C_U may be substantially aligned (e.g., substantially coplanar). The first ends of the lower source / drain layers S / C_L of the select transistors TR_i-jk (1≤k≤L) in the same row (e.g., row i) and the same column (e.g., column j) in different layers can be substantially aligned in the vertical direction (e.g., substantially coplanar), and the first ends of the upper source / drain layers S / C_U can be substantially aligned (e.g., substantially coplanar).

[0038] In the active regions of each select transistor TR_i-jk, the other end of the lower source / drain layer S / C_L in the first direction (which may be referred to as the "second end of (lower source / drain layer S / C_L)") may be substantially aligned (e.g., substantially coplanar) with the corresponding end of the upper source / drain layer S / C_U (which may be referred to as the "second end of (upper source / drain layer S / C_U)") in the vertical direction. The second ends of the respective lower source / drain layer S / C_L and upper source / drain layer S / C_U of the select transistors in the same column (e.g., column j) may be substantially aligned (e.g., substantially coplanar). The second ends of the lower source / drain layer S / C_L and upper source / drain layer S / C_U of the select transistors in the lower layer may extend relative to the second ends of the lower source / drain layer S / C_L and upper source / drain layer S / C_U of the select transistors in the same row and column in the upper layer. Therefore, the second ends of the lower source / drain layers S / C_L and upper source / drain layers S / C_U of the active regions of the selection transistors TR_i-jk (1≤k≤L) in the same row (e.g., row i) and the same column (e.g., column j) can form a stepped structure. This stepped structure facilitates the formation of contacts to the active regions in each layer (especially the upper source / drain layers S / C_U), for example, the (protruding) second ends of each upper source / drain layer S / C_U can be used as bonding pads for such contacts. In Figure 1(a), for ease of illustration, only the contacts to transistors TR_2-2-1 and TR_2-2-2 (the respective upper source / drain layers S / C_U) are shown.

[0039] Word lines WL_j-k can extend along a second direction to surround at least a portion of the outer periphery of the channel portion of the select transistor TR_i-jk (1≤i≤M), thus overlapping at least one side of the channel portion and thereby forming the gate electrode of the select transistor TR_i-jk. In Figure 1(a), to clearly show the structure of the word lines surrounding the channel portion, word lines WL_2-1 and WL_2-2 are only partially shown to expose the channel portion they surround. Word lines WL_j-k can surround the outer periphery of the channel portion of the select transistor, thereby forming a gate all-around (GAA) configuration.

[0040] According to other embodiments, word lines WL_j-k may surround one (or more) sides of the outer periphery of the channel portion, but not the other (or more) sides of the outer periphery of the channel portion, and thus can form a single-sided device. For example, word lines WL_j-k may extend between the channel portions of adjacent select transistors with C-shaped openings facing each other in the corresponding column (j-th column), bypassing the opposite ends of these channel portions in a first direction to extend in a second direction, but not extending between the channel portions of adjacent select transistors with C-shaped openings facing away from each other. This will be described in further detail below.

[0041] Such a storage device can be manufactured, for example, as follows.

[0042] A stack comprising two or more device layers (e.g., L layers as described above) can be formed on a substrate. Each device layer can be used to define a corresponding level of select transistor array (e.g., M rows × N columns as described above), which may include, for example, a first source / drain layer, a channel defining layer, and a second source / drain layer stacked sequentially. Additionally, isolation defining layers can be provided between the device layers for isolation between devices. These isolation defining layers can be replaced with an isolation material in subsequent processes. This vertically stacked device layer can then define a 3D array of select transistors (e.g., an M × N × L 3D array as described above).

[0043] Each select transistor can be electrically connected at one end to a memory element such as a capacitor or MTJ, and at the other end to a bit line to receive data from the bit line (e.g., write data) or send data to the bit line (e.g., read data). According to embodiments of this disclosure, a sub-bit line can be provided on one side of the select transistor to electrically connect it to a corresponding bit line, and a contact portion can be provided on the other side to electrically connect it to a corresponding memory element.

[0044] To establish sub-bit lines, a plurality of vertically extending first processing channels can be formed in the stack. These first processing channels can be arranged in a first direction (e.g., the bit line extension direction) and each extends along a second direction (e.g., the word line extension direction) intersecting (e.g., perpendicular to) the first direction. Considering that each select transistor requires a sub-bit line only on one side, a first processing channel can be provided in the region of every two columns of select transistors, so that each column of select transistors can be adjacent to a first processing channel only on one side. Considering the electrical connection between the bit line and the select transistor, for the bottommost device layer, one of its first source / drain layer and second source / drain layer (e.g., the first source / drain layer) can be used to form the bit line through subsequent processes. Therefore, the bottom of the first processing channel can be defined by the first source / drain layer of the bottommost device layer. Of course, this disclosure is not limited to this. Such bit lines can be configured separately.

[0045] The sub-line can be formed along the sidewall of the first source / drain layer of the lowest device layer using a sidewall forming process, and therefore can be self-aligned. Before forming the sub-line, the second source / drain layers in each device layer exposed in the first processing channel can be recessed relative to the first source / drain layer in a first direction via the first processing channel, so that the sub-line formed along the sidewall of the first processing channel can only contact and thus be electrically connected to the first source / drain layer, while being spaced apart from the second source / drain layers and electrically isolated from each other (due to the subsequently filled dielectric).

[0046] Additionally, via a first processing channel, the end of the channel defining layer in each device layer in the first direction can be recessed in the first direction relative to the corresponding ends of the first source / drain layer and the second source / drain layer, and a first gate position holding layer is formed in the resulting recess. The first gate position holding layer can provide space for subsequent word lines to extend continuously in the second direction around the channel portion.

[0047] Alternatively, a portion of the isolation layer near the first processing channel can be replaced with an isolation layer via the first processing channel.

[0048] In this way, each column select transistor can have a sub-bit line on one side of the first direction. The other side of each column select transistor in the first direction can be processed to facilitate the provision of contacts for electrical connection to the memory element.

[0049] To this end, a plurality of vertically extending second processing channels can be formed in the stack. These second processing channels can be arranged alternately with the first processing channels in a first direction (these channels can be filled during formation to avoid affecting existing structures such as sub-bit lines), and each extends along a second direction. For example, the second processing channels can be located approximately in the middle between every two adjacent first processing channels. When forming the second processing channels, a stepped structure formation process can be used, so that the device layers in the stack can form a stepped structure at the second processing channels, such that the lower device layer extends relative to the upper device layer in the first direction to form a step. For example, the stepped structure can be formed by photoresist trimming combined with successive etching.

[0050] Similarly, via a second processing channel, the end of the channel defining layer in each device layer in the first direction can be recessed in the first direction relative to the corresponding ends of the first source / drain layer and the second source / drain layer, and a second gate position holding layer can be formed in the resulting recess. The second gate position holding layer can provide space for the subsequent word lines to extend continuously in the second direction around the channel portion.

[0051] Similarly, the remaining portion of the isolation layer adjacent to the second processing channel can be replaced with the isolation layer via the second processing channel. An interface or boundary may exist between the isolation layer replaced via the first processing channel and the isolation layer replaced via the second processing channel.

[0052] In the above process, the first and second processing channels do not penetrate the stack, but can stop at the first source / drain layer of the bottommost device layer. This is to ensure the continuity of the first source / drain layer in the first direction, so that it can be used as a bit line thereafter.

[0053] In this way, each device layer is divided into multiple columns arranged in the first direction through the first and second processing channels (which can be filled to prevent subsequent processing from affecting the already formed structures such as sub-bit lines and stepped structures), and each column extends along the second direction. Next, each device layer can be divided in the second direction to form an array of rows and columns.

[0054] For example, multiple third processing channels can be formed throughout the stack. These multiple third processing channels can be arranged in a second direction and each extend along a first direction. Channel layers can be grown on the sidewalls of each device layer exposed in the third processing channels by selective epitaxial growth. Due to selective epitaxial growth, the channel layers can maintain substantially the same shape as the sidewalls exposed in the third processing channels of the device layers. The portion of the channel layer grown on the sidewalls of the channel defining layer can define a channel portion. The channel layer can be in the form of a nanosheet.

[0055] Multiple fourth processing channels can be formed throughout the stack. These multiple fourth processing channels can be arranged alternately with the third processing channel in the second direction, and each extends along the first direction. The channel defining layer, the first gate position holding layer, and the second gate position holding layer can be removed via the fourth processing channels. In this way, a gate receiving space is left around the channel portion (the space released due to the removal of the channel defining layer, the first gate position holding layer, and the second gate position holding layer, as well as the third and fourth processing channels).

[0056] Word line layers corresponding to each device layer can be formed on the substrate. For example, interlayer dielectric layers and gate conductor layers can be formed alternately, with each gate conductor layer located at a height corresponding to the channel portion in each device layer. The gate conductor layers (together or separately) can be patterned as word lines extending along a second direction, at least partially surrounding the outer periphery of the channel portion (through the gate dielectric layer).

[0057] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0058] Figures 2 to 46(b) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown.

[0059] like Figure 2 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0060] On substrate 1001, memory devices, particularly non-volatile memory devices such as DRAM or MRAM, can be formed as described below. The memory cells in the memory device may include selection transistors as n-type or p-type devices, and capacitors or magnetic tunnel junctions (MTJs) as storage elements. Here, an n-type selection transistor is described as an example, for which a p-type well (not shown) may be formed in substrate 1001. Therefore, the following description, particularly regarding the doping type, pertains to the formation of n-type selection transistors. However, this disclosure is not limited thereto.

[0061] On substrate 1001, a first device layer L1, a second device layer L2, and a third device layer L3 can be formed, for example, by epitaxial growth. The active regions of the selectable transistors can be defined from each device layer L1, L2, and L3. For example, the first device layer L1 may include a first source / drain layer 10031, a channel defining layer 10051, and a second source / drain layer 10071. Similarly, the second device layer L2 may include a first source / drain layer 10032, a channel defining layer 10052, and a second source / drain layer 10072, and the third device layer L3 may include a first source / drain layer 10033, a channel defining layer 10053, and a second source / drain layer 10073. Furthermore, for subsequent electrical isolation, isolation defining layers 10091, 10092, and 10093 may be included between device layers L1, L2, and L3. These semiconductor layers can have good crystal quality and can be single-crystal structures. Clear crystal interfaces can be present between adjacent semiconductor layers.

[0062] These semiconductor layers can include a variety of suitable semiconductor materials, such as elemental semiconductors like group IV elemental semiconductors like Si or Ge, compound semiconductors like group IV compound semiconductors like SiGe, or group III-V compound semiconductors like InP and GaAs. The material of the semiconductor layer can be selected based on factors such as the properties of the substrate and the desired device performance.

[0063] In this embodiment, each semiconductor layer formed on the Si wafer can be a Si-based material. Furthermore, considering subsequent processes, there can be etching selectivity between adjacent semiconductor layers. For example, each source / drain layer can include Si, and each channel defining layer and isolation defining layer can include SiGe (e.g., the atomic percentage of Ge can be about 10% to 30%).

[0064] The semiconductor layers in each device layer can be appropriately doped according to the conductivity type of the selective transistor to be formed. For example, the first source / drain layer and the second source / drain layer can be heavily doped (e.g., doping concentration of about 1E19 to 1E21 cm⁻¹). -3 The conductivity type is the same as that of the selection transistor to be implemented. Alternatively, for tunneling devices, the first source / drain layer and the second source / drain layer in the same device layer can be doped with opposite conductivity types. Doping of semiconductor layers can be achieved by in-situ doping during epitaxial growth or by other doping methods such as ion implantation. Doping concentration interfaces can exist between adjacent semiconductor layers.

[0065] Each semiconductor layer can have a suitable (vertical) thickness. For example, the first and second source / drain layers can each have a thickness of about 20 to 200 nm, the isolation layer can have a thickness of about 10 to 30 nm, and the channel layer can have a thickness of about 20 to 50 nm. Considering subsequent processes, the thickness of each channel layer can be greater than the thickness of each isolation layer, and the thickness of the lower first source / drain layer in each device layer (except the bottommost device layer L1) can be less than the thickness of the upper second source / drain layer.

[0066] Additionally, a hard mask layer 1011 can be formed above the semiconductor layer to assist in patterning. For example, the hard mask layer 1011 may include a nitride (e.g., silicon nitride) with a thickness of about 30 to 100 nm.

[0067] exist Figure 2 The diagram illustrates three device layers L1, L2, and L3, from which three layers of select transistors can subsequently be formed. However, this disclosure is not limited thereto. More or fewer device layers (e.g., L layers as described above) can be provided, and select transistors of corresponding levels can be formed.

[0068] Vertically extending sub-bit lines can be created to electrically connect vertically stacked select transistors to the corresponding bit lines.

[0069] For example, such as Figure 3(a) and 3(b)As shown, photoresist 1013 can be formed on the hard mask layer 1011 and patterned by photolithography to have a series of openings arranged in a first direction (e.g., x direction) and extending along a second direction (e.g., y direction) that intersects (e.g., is perpendicular to) the first direction, which can define the position of the sub-bit line.

[0070] like Figure 4 As shown, the photoresist 1013 can be configured as an etching mask, and the layers on the substrate 1001 can be etched by anisotropic etching, such as reactive ion etching in a vertical direction (e.g., perpendicular to the substrate surface), to form first processing channels T1. The RIE can stop at the first source / drain layer 10031 of the bottommost device layer L1. Thus, a series of vertical first processing channels T1 are left on the substrate 1001. Afterwards, the photoresist 1013 can be removed.

[0071] A gate position retention layer may be formed at the end of the channel defining layers 10051, 10052, and 10053 in a first direction (e.g., the x-direction). For example, as Figure 5 As shown, via the first processing channel T1, selective etching can be used to recess the channel defining layers 10051, 10052, and 10053 (in this example, SiGe) in each device layer relative to the source / drain layers (in this example, Si) in a first direction to provide space for subsequently accommodating the gate stack. In this example, the isolation defining layers 10091, 10092, and 10093 (in this example, also SiGe as the channel defining layers) are also recessed relative to each other in the first direction to approximately the same degree. Considering the following plug (see... Figure 7 The formation of 1015′ in the middle can have an etching depth (or relative recess) greater than half the thickness of the largest of the isolation limiting layers 10091, 10092, and 10093.

[0072] To avoid the gate position holding layer forming in the relative recesses of the isolation limiting layers 10091, 10092, and 10093 (which is undesirable), plugs can be formed in the relative recesses of the isolation limiting layers 10091, 10092, and 10093. For example, as Figure 6As shown, a plug material layer 1015 can be deposited with a thickness greater than half the maximum thickness of the isolation layers 10091, 10092, and 10093 but less than half the minimum thickness of the channel layers 10051, 10052, and 10053. Thus, the deposited plug material layer 1015 can completely fill the relative recesses of the isolation layers 10091, 10092, and 10093, but can maintain a generally conformal thin film form in the relative recesses of the channel layers 10051, 10052, and 10053. Considering etching selectivity in subsequent processes, the plug material layer 1015 can include, for example, SiC. The deposited plug material layer 1015 can be etched back to a certain thickness (e.g., slightly larger than the deposition thickness), so that the plug material layer 1015 can remain in the relative recesses of the isolation limiting layers 10091, 10092, 10093 to form plug 1015', and be removed from the relative recesses of the channel limiting layers 10051, 10052, 10053, as shown below. Figure 7 As shown. To better control the etching depth, atomic layer etching (ALE) can be used.

[0073] When the isolation limiting layers 10091, 10092, and 10093 have etching selectivity relative to the channel limiting layers 10051, 10052, and 10053, the formation of the plug 1015' can be omitted.

[0074] In addition, such as Figure 8 As shown, via the first processing channel T1, selective etching can be used to further recess the channel defining layers 10051, 10052, and 10053 in each device layer in the first direction, for example, by about 10 nm to 40 nm, to provide a larger gate accommodating space. In the above combination Figure 5 In the selective etching step described, the channel defining layers 10051, 10052, 10053 (and the isolation defining layers 10091, 10092, 10093) are not recessed so much in order to facilitate the formation of the plug 1015', because excessive recesses would make it difficult to conformally deposit and etch back the plug material layer 1015 in such recesses.

[0075] After that, as Figure 9 As shown, a gate position holding layer 1017 (which may be referred to as the "first gate position holding layer") can be formed in the relative recesses of the channel defining layers 10051, 10052, and 10053. The first gate position holding layer 1017 may include a material having etching selectivity relative to the plug 1015′ (in this example, SiC) and the hard mask layer 1011 (in this example, nitride), such as an oxide (e.g., silicon oxide). For example, the first gate position holding layer 1017 can be formed by depositing an oxide and performing vertical RIE on the deposited oxide.

[0076] Similarly, such as Figure 10 As shown, the plug 1015' in the relative recesses of the isolation defining layers 10091, 10092, and 10093 can be removed by selective etching via the first processing channel T1, thereby exposing the isolation defining layers 10091, 10092, and 10093 to be further recessed in the first direction, for example, by about 15 nm to 60 nm. Alternatively, the plug 1019 can be formed in the further recesses of the isolation defining layers 10091, 10092, and 10093 by deposition and etching back. Considering etching selectivity, the plug 1019 may comprise SiC.

[0077] Currently, the sidewalls of the first and second source / drain layers in each device layer are exposed in the first processing channel T1. It is desirable that the formed sub-bit lines connect to the source / drain region defined by one of the first and second source / drain layers (e.g., the first source / drain layer), but not to the source / drain region defined by the other (e.g., the second source / drain layer), which can be connected to memory elements such as capacitors, MTJs, etc. Therefore, for example, the second source / drain layer can be recessed relative to the first source / drain layer in a first direction.

[0078] To achieve a relative recess between the first and second source / drain layers, which have no etch selectivity relative to each other, a combination similar to the one described above can be used. Figure 6 and 7 The described process involves forming plugs 1021 at the ends of the first source / drain layers 10032, 10033 that are desired to protrude relative to each other (for connection to the sub-line), as shown in the image. Figure 11 As shown. Since the thickness of the first source / drain layers 10032 and 10033 in each device layer (except the bottommost device layer L1) is less than the thickness of the second source / drain layers 10072 and 10073, such a plug 1021 can be formed. Considering the etching selectivity in subsequent processes, the plug 1021 may include a nitride. Furthermore, an etch stop layer (not shown), such as an oxide layer, may be provided between the nitride plug 1021 and the source / drain layers. As described above, if the first source / drain layer and the second source / drain layer have etching selectivity relative to each other, the formation of the plug 1021 can be omitted.

[0079] To prevent the etching involved in forming plug 1021 from affecting the first source / drain layer 10031 in the lowest device layer L1, a protective layer can be formed at the bottom of the first processing channel T1 before the process of forming plug 1021 begins. For example, an oxide can be deposited to fill the first processing channel T1, and the deposited oxide can be planarized, such as by chemical mechanical polishing (CMP, which may stop at hard mask layer 1011). Then, the planarized oxide can be etched back by vertical RIE, so that its top surface is lowered to expose the sidewalls of each source / drain layer except for the first source / drain layer 10031 in the lowest device layer L1 (e.g., the top surface is at the height between the top and bottom surfaces of the first channel defining layer 10051 in the lowest device layer L1). In this example, the oxide thus formed and the previously formed gate position holding layer 1017 both consist of oxide and are therefore integrally shown as 1017'.

[0080] like Figure 12 As shown, the second source / drain layers 10071, 10072, and 10073 in each device layer can be further recessed in the first direction, for example, by about 10 nm to 30 nm, via selective etching through the first processing channel T1. Thus, the second source / drain layers 10071, 10072, and 10073 are recessed in the first direction relative to the first source / drain layers 10031, 10032, and 10033. Furthermore, the second source / drain layers 10071, 10072, and 10073 can still extend relative to the channel defining layers 10051, 10052, and 10053, thereby defining a gate receiving space together with the first source / drain layers 10031, 10032, and 10033 on the outer side of the ends of each channel defining layer 10051, 10052, and 10053.

[0081] After the end of each device layer is patterned as described above on one side of the first processing channel T1, a sub-bit line can be formed in the first processing channel T1.

[0082] like Figure 13As shown, dielectric material can be filled into the voids below the hard mask layer 1011 caused by the patterning of the device layers. For example, the isolation layer 1023 can be formed by depositing and etching back (e.g., vertical RIE) SiC. Alternatively, before depositing SiC, the first gate position holding layer 1017 can be selectively etched to a small extent (thus recessing it to a certain depth in the first direction). In this way, the subsequently formed isolation layer 1023 can cover the sidewalls of the first gate position holding layer 1017. This can increase the electrical distance between the gate stack that subsequently replaces the first gate position holding layer 1017 and the sub-bit lines formed in the first processing channel T1, and thus reduce parasitic capacitance. In the following figures and description, for convenience only, the case where the first gate position holding layer 1017 is not etched is used as an example.

[0083] like Figure 14 As shown, the plug 1021 can be removed by selective etching to expose the sidewalls of the first source / drain layers 10032 and 10033 in device layers L2 and L3 (so that they can be connected to the subsequently formed sub-bit lines). Alternatively, the protective layer 1017' at the bottom of the first processing channel T1 can be removed by selective etching, for example, along a vertical RIE, thereby exposing the first source / drain layer 10031 of the lowermost device layer L1 at the bottom of the first processing channel T1 (but the first gate position holding layer 1017 remains at the ends of each channel defining layer).

[0084] According to embodiments of this disclosure, sub-bit lines can be formed in a self-aligned manner.

[0085] For example, such as Figure 15 As shown, the sub-line 1025 extending along the sidewall of the first processing channel T1 can be formed using a spacer forming process. For example, a conductive material, such as doped polysilicon, can be deposited in a generally conformal manner, and then anisotropic etching, such as a vertical RIE, can be performed on the deposited conductive material to remove the lateral extension portion of the deposited conductive material, leaving its vertical extension portion, thereby forming the sub-line 1025 in the form of a sidewall. Here, since the sidewalls of the first source / drain layers 10032 and 10033 are relatively recessed, the sub-line 1025 also protrudes accordingly, thus contacting the sidewalls of the first source / drain layers 10032 and 10033 in device layers L2 and L3. In addition, the sub-line 1025 contacts the first source / drain layer 10031 of the bottommost device layer L1 at the bottom. Therefore, the sub-line 1025 can contact the first source / drain layers 10031, 10032, and 10033 in each device layer.

[0086] After that, as Figure 16As shown, the first processing channel T1 can be backfilled by depositing and planarizing a dielectric material to achieve electrical isolation between the first processing channel T1 and the device layers on both sides. For example, the deposited dielectric material can be the same material as the isolation layer 1023 (SiC in this example) and is therefore integrally shown as 1027.

[0087] Note that the first source / drain layer defining the lower source / drain region in each device layer is connected to the sub-bit line. In DRAM, the second source / drain layer defining the upper source / drain region can be connected to memory elements such as capacitors, MTJs, etc., to realize memory cells. Considering the vertical stacking configuration between the device layers, a stepped structure can be formed to achieve electrical connections to the corresponding device layer of the memory element (especially the second source / drain layer therein). For example, such a stepped structure can be formed on the side of each device layer opposite to the side where the sub-bit line is formed in the first direction.

[0088] There are several ways to form a stepped structure. For example, a stepped structure can be patterned using photoresist trimming combined with successive etching. During patterning, device layers L1, L2, and L3 can each be considered as "one layer," thus steps can be formed between the first device layer L1 and the second device layer L2, and between the second device layer L2 and the third device layer L3.

[0089] For example, such as Figure 17 As shown, photoresist 1029 can be formed on the hard mask layer 1011 and patterned by photolithography to have a series of openings arranged in a first direction (e.g., the x-direction) extending along a second direction (e.g., the y-direction), which can define the location of the stepped structure. These openings in the photoresist 1029 can be located, for example, approximately at the center between each pair of adjacent first processing channels T1 (which have now been backfilled) in the first direction.

[0090] The photoresist 1029 can be configured as a mask to etch down the hard mask layer 1011 to expose the underlying device layer, and then the device layer can be etched. When etching the device layer, an etching formula that is substantially non-selective towards each layer in the device layer (e.g., Si and SiGe) can be selected. Here, the etching depth D1 can be controlled to correspond to the thickness of the first device layer L1 (excluding the first source / drain layer 10031, since the first source / drain layer 10031 does not need to be etched) (i.e., the thickness of the channel defining layer 10051 + the thickness of the second source / drain layer 10071).

[0091] After that, as Figure 18As shown, the photoresist 1029 can be trimmed. More specifically, the width of the opening in the photoresist 1029 in the first direction can be increased, and the increase can correspond to the width of the desired step in the first direction. The trimmed photoresist 1029 can be used as a mask to continue etching the device layer. Similarly, the etching depth D2 can be controlled to correspond to the thickness of the second device layer L2 (i.e., the thickness of the first source / drain layer 10032 + the thickness of the channel defining layer 10052 + the thickness of the second source / drain layer 10072) + the thickness of the isolation defining layer 10091 (because the isolation defining layer 10091 can be recessed relative to the underlying first device layer L1, just like the second device layer L2, so as to expose the underlying first device layer L1).

[0092] Similarly, such as Figure 19 As shown, the photoresist 1029 can be further modified to increase the width of the opening in the first direction, with the increase corresponding to the width of the desired step in the first direction. The modified photoresist 1029 can be used as a mask to continue etching the device layer. Similarly, the etching depth D3 can be controlled to correspond to the thickness of the third device layer L3 (i.e., the thickness of the first source / drain layer 10033 + the thickness of the channel defining layer 10053 + the thickness of the second source / drain layer 10073) + the thickness of the isolation defining layer 10092 (because the isolation defining layer 10092 can be recessed relative to the underlying second device layer L2, just like the third device layer L3, to expose the underlying second device layer L2) + the thickness of the isolation defining layer 10093 (because the isolation defining layer 10093 can be recessed relative to the underlying second device layer L2, just like the third device layer L3, to expose the underlying second device layer L2).

[0093] Thus, a stepped structure is formed in the device layer. For example... Figure 19 As shown, the lower device layer extends relative to the upper device layer in a first direction, thereby forming a step. The portion of the lower device layer that extends relative to the upper device layer can then be used as a bonding pad for the contact portion of that device layer (particularly the second source / drain layer therein).

[0094] In the case of multiple layers, the photoresist can be similarly trimmed, and the device layers can be etched sequentially according to the thickness of each device layer (including the thickness of the corresponding isolation layer if necessary), thereby forming more steps. Afterwards, the photoresist 1029 can be removed.

[0095] Furthermore, due to the aforementioned process, a second processing channel T2 is formed that penetrates each device layer (except for the first source / drain layer 10031 of the bottommost device layer L1) in the vertical direction. Thus, each device layer (except for the first source / drain layer 10031 of the bottommost device layer L1) is separated into separate portions in the first direction by the second processing channel T2 and the first processing channel T1 (which is filled with an isolation layer), i.e., multiple columns (e.g., N columns as described above) extending in the second direction and arranged in the first direction. Each column has a sub-bit line on one side of the first direction and a stepped structure on the opposite side.

[0096] Similarly, such as Figure 20 As shown, via the second processing channel T2, selective etching can be used to recess the channel defining layers 10051, 10052, and 10053 (in this example, SiGe) in each device layer relative to the respective source / drain layers (in this example, Si) in a first direction to provide space for subsequently accommodating the gate stack. As described above... Figures 5 to 8 As described above, a plug 1031 can be formed to prevent the subsequent formation of a second gate position holding layer (see...). Figure 21 1033) is also formed at the ends of the isolation limiting layers 10091, 10092, and 10093.

[0097] After that, as Figure 21 As shown, a second gate position holding layer 1033 can be formed in the relative recesses of the channel defining layers 10051, 10052, and 10053 by deposition followed by etching back, for example, oxide. Thus, a first gate position holding layer 1017 and a second gate position holding layer 1033 are formed at opposite ends of each channel defining layer 10051, 10052, and 10053 in the first direction, respectively. This facilitates the subsequent word lines to extend continuously along the second direction around the channel layers and also facilitates the formation of a GAA configuration.

[0098] The isolation layer can be replaced with an isolation material to achieve electrical isolation between adjacent device layers in the vertical direction. For example, ... Figure 22 As shown, the plug 1031 can be removed by selective etching to expose the isolation layers 10091, 10092, and 10093. Then, the isolation layers 10091, 10092, and 10093 can be removed by selective etching. Figure 24As shown, the spaces left by the removal of isolation layers 10091, 10092, and 10093 can be filled with an isolation material, for example, by deposition followed by etching back (e.g., vertical RIE). For example, the filled isolation material can include SiC, similar to the previous isolation layer 1027, and is therefore integrally shown as 1037. Note that between the device layers, the isolation layer 1037 may include dielectric interfaces or boundaries, such as… Figure 24 The dashed lines in the figures illustrate this. This is because the isolation layers between the device layers can be filled from the first processing channel T1 and the second processing channel T2, respectively. For convenience, such dielectric interfaces or boundaries are not shown in the other figures.

[0099] Optionally, to reduce contact resistance before filling with the isolation material, the surfaces of the first and second source / drain layers exposed by each device layer can be silicided via the second processing channel T2 to form silicide 1035. For example, a metal such as Ni or NiPt can be deposited and annealed at a temperature of about 300 to 700°C, causing the deposited metal to react with the semiconductor elements in the first and second source / drain layers to generate a metal-semiconductor compound such as NiSi or NiPtSi. Thus, silicide 1035 can be formed on the sidewalls and part of the lower surface of the first source / drain layer on the side of the second processing channel T2, or on the sidewalls and part of the upper surface of the second source / drain layer on the side of the second processing channel T2. Afterwards, any unreacted residual metal can be removed, and the isolation layer 1037 can be formed as described above.

[0100] Similarly, such as Figures 25(a) to 25(d) The second processing channel T2 can be backfilled by depositing and planarizing a dielectric material. Here, the deposited dielectric material can be the same material as the isolation layer 1037 (SiC in this example) and is therefore integrally shown as 1039. Furthermore, before depositing the dielectric material, the hard mask layer 1011 can be removed by selective etching such as RIE. This is because the device layers have already been separated in the first direction (separated into N columns) using the hard mask layer 1011.

[0101] Furthermore, in the following process, a spacer image transfer technique is utilized to achieve finer patterning. For this purpose, a mandrel layer 1041 can be formed on the isolation layer 1039, for example, by deposition. Considering etching selectivity, the mandrel layer 1041 may comprise (polycrystalline) silicon. A hard mask layer 1043 may be additionally formed on the mandrel layer 1041 to aid in patterning, particularly in separating device layers in a second direction (e.g., the y-direction). For example, the hard mask layer 1043 may comprise a nitride with a thickness of approximately 30 to 100 nm.

[0102] Photoresist 1045 can be formed on the hard mask layer 1043 and patterned by photolithography into a series of lines arranged in a second direction (e.g., the y direction) extending along a first direction (e.g., the x direction).

[0103] like Figure 26 As shown, photoresist 1045 can be used as a mask, and hard mask layer 1043 and core mold layer 1041 can be sequentially etched by anisotropic etching, such as vertical RIE. Thus, the line pattern of photoresist 1045 is transferred to hard mask layer 1043 and core mold layer 1041. Afterwards, photoresist 1045 can be removed. Sidewalls 1047 can be formed on the sidewalls of the linear hard mask layer 1043 and core mold layer 1041 extending along a first direction (e.g., x-direction) using a sidewall forming process. For example, sidewall 1047 may include nitride, and its thickness in a second direction (e.g., y-direction) can define the scale of the active region of the selection transistor in the second direction (e.g., y-direction). Additionally, the width of core mold layer 1041 in the second direction (e.g., y-direction) can define the spacing between adjacent selection transistors in the second direction (e.g., y-direction).

[0104] like Figure 27 As shown, a hard mask layer 1043 and sidewalls 1047 can be used as masks to etch the underlying isolation layer 1039 and each device layer through anisotropic etching, such as a vertical RIE, to form a third processing channel T3 extending along a first direction (e.g., the x-direction). The etching can stop in the first source / drain layer 10031 of the bottommost device layer L1. Thus, the third processing channel T3 can separate each device layer (except for the first source / drain layer 10031 of the bottommost device layer L1) into portions that are separated from each other in a second direction (e.g., the y-direction). Here, the sidewalls of the first source / drain layer 10031 can be partially exposed in the third processing channel T3.

[0105] A protective sidewall 1049 can be formed on the sidewall of the third processing channel T3 using a sidewall formation process. For example, the protective sidewall 1049 may include a nitride with a thickness of approximately 2 nm to 10 nm. To better control the thickness of the protective sidewall 1049, atomic layer deposition (ALD) can be used in the sidewall formation process. Figure 28(a) and 28(b)As shown, with the protective sidewall 1049 present, the hard mask layer 1043 and the sidewall 1047 can be used as masks to further etch the first source / drain layer 10031. Here, an etching formulation with lateral action can be used, thereby forming an undercut in the first source / drain layer 10031. The presence of the protective sidewall 1049 prevents interference with other source / drain layers. The undercut does not extend into the channel defining layer 10051 and the well region in the substrate 1001 below, to prevent leakage.

[0106] In the undercut thus formed, a metal strip 1051 can be formed by depositing and then etching back (e.g., vertical RIE) metals such as tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. This metal strip 1051 is embedded in the first source / drain layer 10031 at the bottom of each third processing channel T3 and extends along the first direction.

[0107] like Figure 29 As shown, the first source / drain layer 10031 can be further etched using the hard mask layer 1043 and sidewalls 1047 (and protective sidewalls 1049) as masks, through anisotropic etching such as vertical RIE, and the etching can stop in the well region in the substrate 1001. This deepens the third processing channel T3 and further separates the first source / drain layer 10031 into portions that are separated from each other in a second direction (e.g., the y-direction). A certain thickness of nitride can be etched selectively to remove the protective sidewalls 1049, but the hard mask layer 1043 and sidewalls 1047 can be retained. Additionally, in the third processing channel T3, an isolation layer 1053 can be formed by depositing, planarizing, and then etching back a dielectric material. For example, the isolation layer 1053 may include the same material as the isolation layer 1039 (SiC in this example), and the height of its top surface is such that the isolation layer 1053 can shield the metal strip 1051 from damage during the subsequent epitaxial growth of the channel layer, but can expose part of the sidewall of the first source / drain layer 10031.

[0108] like Figure 30(a) and 30(b) As shown, the channel layer 1055 can be formed, for example, by selective epitaxial growth. For instance, the channel layer 1055 may comprise a semiconductor material such as Si that has etch selectivity relative to the channel defining layer, and its thickness may be from about 3 nm to 15 nm. Although the channel layer 1055 is shown as a single layer in the figure, it can be a multilayer structure.

[0109] Because it is a selective epitaxial growth, the channel layer 1055 can be self-aligned to the sidewalls of each device layer exposed in the third processing channel T3, and can maintain substantially the same shape as these exposed sidewalls (see Figure 33(e), where the shape of the channel layer 1055 is clearly shown). Note that in the case where the sub-line 1025 comprises (doped) polysilicon, the channel layer 1055 can also be grown on the sidewalls of the sub-line 1025 exposed in the third processing channel T3.

[0110] The 1055 channel layer may be undoped or lightly doped through in-situ doping during growth to improve short-channel effects and adjust the device threshold voltage (V). t For example, for n-type selection transistors, p-type doping can be performed, with a doping concentration of approximately 1E17-1E19 cm⁻¹. -3 This light doping of the channel layer 1055 does not cause short circuits between the source / drain layers and the sub-bit lines, even though the channel layers 1055 grown on their respective sidewalls extend continuously to each other as shown in Figure 33(e).

[0111] Additionally, annealing can be performed to drive the dopant from the source / drain layers into the corresponding portions of the channel layer 1055, thereby reducing external resistance and improving device performance. Figure 33(e) schematically illustrates the interface between the portions of the channel layer 1055 used as sources / drains (the portions grown on the sidewalls of each source / drain layer) and the portions used as channels (the portions grown on the sidewalls of the channel defining layer, also referred to as "channel portions") with dashed lines. This interface can be defined by the doping concentration. The diffusion of dopant into the portions of the channel layer 1055 used as sources / drains can have substantially the same characteristics, thus the portions of the channel layer 1055 used as channels can be self-aligned to the corresponding channel defining layers.

[0112] In the other accompanying drawings, for ease of illustration only, the distinction between the portion of the channel layer 1055 used as a source / drain and the portion used as a channel is not shown.

[0113] After that, as Figure 31(a) and 31(b) As shown, the third processing channel T3 can be backfilled by depositing and planarizing a dielectric material to achieve electrical isolation between the third processing channel T3 and the device layers on both sides. For example, the deposited dielectric material can be the same material as the isolation layer 1053 (SiC in this example) and is therefore integrally shown as 1057. Here, when planarizing the dielectric material, the mandrel layer 1045 can be used as a stop point, so the hard mask layer 1047 on top of the mandrel layer 1045 can be removed. In addition, the mandrel layer 1045 can be exposed. The mandrel layer 1045 can be removed by selective etching. Thus, a linear sidewall 1047 extending along the first direction is left.

[0114] The sidewall 1047 can be used as a mask to sequentially etch the isolation layer 1057 and each device layer using anisotropic etching, such as vertical RIE. Similarly, the etching can stop in the well region in the substrate 1001, thereby forming the fourth processing channel T4. Since the etching of the isolation layer 1057 is involved, the top surface of the isolation layer 1057 can be lowered relative to the top of the sidewall 1047.

[0115] Therefore, each device layer is separated into separate portions in the second direction by the fourth processing channel T4 and the third processing channel T3 (which are filled with an isolation layer), i.e., multiple rows (e.g., M rows as described above) extending along the first direction arranged in the second direction. Thus, each device layer is divided into active regions for selecting transistors arranged along the first and second directions. These active regions are arranged in an array (e.g., M rows × N columns). As described above, the first source / drain layer 10031 in the lowest device layer L1 can extend continuously in the first direction and can therefore be used as a bit line. The bit line extending in the first direction can be electrically connected to the first source / drain layer in the upper device layers (for the lowest first device layer L1, the bit line itself constitutes its first source / drain layer) via sub-bit lines 1025 extending in the vertical direction. Embedding the bit line with the metal strip 1051 as described above can reduce the resistance of the bit line, but this is not necessarily required. Alternatively, if the above combination... Figure 28(a) and 28(b) If the undercut is deep during the undercut process, the etching of the fourth processing channel T4 may cause the sidewalls of the metal strip 1051 formed during the undercut to be directly exposed in the fourth processing channel T4. Therefore, the bit line may include a stacked structure of the first source / drain layer 10031 and the metal strip 1051, more specifically, a structure in which the lower part of the first source / drain layer 10031, the metal strip 1051, and the upper part of the first source / drain layer 10031 are stacked sequentially. In this case, the "metal strip" 1051 can also be referred to as the "metal layer" 1051.

[0116] Next, we can create the letter lines.

[0117] like Figure 32(a) and 32(b)As shown, the fourth processing channel T4 can be backfilled by depositing and planarizing a dielectric material (e.g., SiC). Then, the deposited dielectric material and the isolation layer 1057 can be etched back to reopen the third and fourth processing channels T3 and T4, thereby exposing the respective channel defining layers. Additionally, the etching formulation used during the etch-back can have a certain lateral effect, allowing the isolation layer 1057 to be relatively recessed in the second direction (e.g., at least the thickness of the channel layer 1055, so that the isolation layer 1057 between the channel layers 1055 in the vertical direction can be removed), allowing the sidewalls of the gate position holding layers to be exposed in the third and fourth processing channels T3 and T4. However, the etch-back does not completely remove the isolation layer 1057 between the device layers, thus supporting the vertical stacking structure of the device layers. The etched-back dielectric material and the isolation layer 1057 are shown together as 1059.

[0118] like Figures 33(a) to 33(f) As shown, the first gate position holding layer 1017 and the second gate position holding layer 1033 can be removed by selective etching. This releases gate accommodating spaces T5 on opposite sides of each channel defining layer (and the channel portions of the channel layers 1055 grown on their sidewalls) in the first direction. As shown in FIG33(d), these gate accommodating spaces T5 communicate with the third processing channel T3 and the fourth processing channel T4 in the second direction, thereby allowing word lines to be subsequently formed that extend continuously in the second direction via the gate accommodating spaces T5 around the channel portions.

[0119] Additionally, the channel defining layers 10051, 10052, and 10053 can be selectively etched away. This releases gate accommodating spaces T6 between the first and second source / drain layers in each device layer. As shown in Figure 33(c), these gate accommodating spaces T6 communicate with the fourth processing channel T4 on one side. Furthermore, these gate accommodating spaces T6 communicate with the third processing channel T3 on the other side via gate accommodating space T5. The gate accommodating space T5, which communicates with the gate accommodating space T6, is schematically shown as a dashed line in Figure 33(f).

[0120] That is, for the channel portion in each device layer, there exists a space surrounding it: on one side in the second direction, there is a gate accommodating space T6 (connected to the fourth processing channel T4), and on the other side in the second direction, there is a third processing channel T3 (see Figure 33(c)); on opposite sides in the first direction, there are gate accommodating spaces T5 (see Figure 33(e)), wherein the gate accommodating space T5 is connected to both the third processing channel T3 and the fourth processing channel T4 (see Figure 33(d)). Therefore, word lines surrounding the channel portion in each device layer can then be formed, thus obtaining a GAA configuration.

[0121] like Figures 34(a) to 34(d)As shown, the gate dielectric layer 1061 can be formed by deposition in a generally conformal manner. For example, the gate dielectric layer 1061 may include a high-k dielectric such as HfO2 with a thickness of about 1 nm to 5 nm. Before forming the high-k gate dielectric, an oxide interface layer (not shown) with a thickness of, for example, about 0.3 nm to 2 nm may also be formed. It can be seen that the surface of the active region (including the first source / drain layer, the second source / drain layer, and the channel layer) can be covered by the gate dielectric layer 1061.

[0122] Next, gate conductor layers corresponding to each device layer (especially the channel portion of the channel layer) can be formed, thereby constituting bit lines.

[0123] For example, such as Figures 35(a) to 35(d) As shown, the first gate conductor layer 1063 can be formed by deposition, planarization (which may stop at the sidewall 1047), and then etch-back (e.g., vertical RIE). The first gate conductor layer 1063 may include a work function adjustment layer, such as a conductive nitride like TaN or TiN, and a gate conductive material layer, such as a metal like tungsten (W). For example, the work function adjustment layer may be formed in a generally conformal manner, and the gate conductive material layer may fill the gaps left in the structure. Due to the etch-back, the top surface of the first gate conductor layer 1063 in the third processing channel T3 and the fourth processing channel T4 may be lowered to the height between the top and bottom surfaces of the first source / drain layer 10032 in the second device layer L2. In addition, the first gate conductor layer 1063 may also remain in the recess caused by the isolation layer 1059 (in the second direction) being relatively concave relative to the adjacent layer, and in the gate housing spaces T5 and T6.

[0124] like Figure 36(a) and 36(b) As shown, a protective sidewall 1065 can be formed on the first gate conductor layer 1063 using a sidewall forming process. Considering etching selectivity, the protective sidewall 1065 may include, for example, an oxide. The protective sidewall 1065 can extend vertically on the first gate conductor layer 1063, and can shield the first gate conductor layer 1063 remaining in the gate receiving spaces T5 and T6 (and the recess at the end of the isolation layer 1059) above the bottom surface of the device layer L2.

[0125] like Figures 37(a) to 37(c)As shown, with the protective sidewall 1065 present, the first gate conductor layer 1063 can be further etched using isotropic etching. Etching the first gate conductor layer 1063 lowers its top surface in the third processing channel T3 and the fourth processing channel T4, for example, to near (e.g., slightly below) the bottom surface of the second source / drain layer 10071 in device layer L1, thereby reducing the overlap between the first gate conductor layer 1063 and the second source / drain layer 10071, thus reducing parasitic capacitance and improving device reliability. Furthermore, due to isotropic etching, any remaining first gate conductor layer 1063 in the recess at the end of the isolation layer 1059 between device layers L1 and L2 can be removed.

[0126] Therefore, as shown in FIG37(c), the first gate conductor layer 1063 can fill the bottom of the third processing channel T3 and the fourth processing channel T4, as well as the gate receiving spaces T5 and T6, thereby surrounding the channel portion in the first device layer L1. As clearly shown in FIG37(b), the first gate conductor layer 1063 can extend continuously in the second direction.

[0127] Subsequently, the protective sidewall 1065 can be removed by selective etching.

[0128] As can be seen, in the gate housing spaces T5 and T6, the first gate conductor layer 1063, located between the first source / drain layer 10031 and the second source / drain layer 10071 (or the channel layer 1055 grown on their sidewalls), can be self-aligned with the channel portion of the first device layer L1. However, in the third processing channel T3, the first gate conductor layer 1063 may not be completely aligned with the channel portion. According to another embodiment, instead of forming a GAA structure, a single-sided structure is formed. For example, as... Figure 38(a) and 38(b) As shown, photoresist (not shown) can be formed on the first gate conductor layer 1063, and the first gate conductor layer 1063 is patterned using the photoresist (and sidewall 1047) to be removed from the sidewall facing the third processing channel T3 from the channel layer 1055. Thus, although the first gate conductor layer 1063 can still maintain continuous extension in the second direction (the cross-sectional view along the CC′ line can remain substantially the same as the interface view shown in FIG. 37(b), it mainly overlaps with the channel layer 1055 from one side (the side facing the gate receiving space T6). In this case, the portion of the first gate conductor layer 1063 near the channel layer 1055 can be self-aligned with the channel portion.

[0129] The following description will still use the GAA structure as an example, but these descriptions also apply to one-sided structures.

[0130] like Figure 39(a) and 39(b)As shown, an interlayer dielectric layer 1067 can be formed on the first gate conductor layer 1063 by deposition, planarization (which may stop at the sidewall 1047), and then etch-back (e.g., vertical RIE). The interlayer dielectric layer 1067 may include the same material as the isolation layer 1059 (SiC in this example). The top surface of the interlayer dielectric layer 1067 in the third processing channel T3 and the fourth processing channel T4 may be close to (e.g., slightly lower than) the top surface of the first source / drain layer 10032 of the second device layer L2. Since the protective sidewall 1065 is formed above, the first gate conductor layer 1063 remains in the gate accommodating spaces T5 and T6 in the second device layer L2 and the third device layer L3 above it, and therefore the interlayer dielectric layer 1067 does not enter these gate accommodating spaces.

[0131] Next, as Figures 40(a) to 40(c) As shown, it can be combined according to the above. Figures 35(a) to 37(c) The process described above is used to similarly form the second gate conductor layer 1069 for the second device layer L2, and can be combined as described above. Figure 39(a) and 39(b) The process described above forms the interlayer dielectric layer 1071, and similarly forms the third gate conductor layer 1073 and the interlayer dielectric layer 1075 for the third device layer L3. Here, the uppermost interlayer dielectric layer 1075 can be planarized so that its top surface is substantially coplanar with the top surface of the sidewall 1047. Each gate conductor layer can have the same material, and each interlayer dielectric layer can have the same material.

[0132] As previously described, and particularly as shown in the cross-sectional view of Figure 37(c), each gate conductor layer can extend continuously in a plane defined by a first direction and a second direction. Each gate conductor layer can be patterned as a word line extending along the second direction (e.g., the y-direction) (and thus intersecting with a bit line extending along the first direction).

[0133] For example, such as Figures 41(a) to 41(d) As shown, photoresist 1077 can be formed on the interlayer dielectric layer 1075 and patterned by photolithography to cover a series of strips extending along a second direction (e.g., the y-direction), which will subsequently define word lines. In the first direction, these strips can cover at least a portion of the corresponding channels in the underlying device layers (between the first processing channels T1 and the second processing channels T2 that are adjacent to each other) and the fifth processing channels T5 on opposite sides of the channels.

[0134] like Figures 42(a) to 42(c)As shown, photoresist 1077 can be used as a mask to etch downwards (e.g., through a vertical RIE) the interlayer dielectric layers 1075, 1071, 1067 and the isolation layer 1059, as well as the gate conductor layers 1073, 1069, and 1063. Etching can stop at the underlying Si material (e.g., substrate 1001, the first source / drain layer 10031 of the lowermost first device layer L1, and the channel layer 1055 grown on its sidewalls). Thus, the gate conductor layers 1063, 1069, and 1073 can be patterned as strips extending in a second direction (e.g., the y-direction) as defined by photoresist 1077, serving as word lines (WL). Such word lines extending in the second direction (e.g., the y-direction) in the first device layer L1 are clearly shown in the cross-sectional view of Figure 42(c). Afterwards, photoresist 1077 can be removed.

[0135] The cross-sectional view in Figure 42(d) shows the word line in the case of a single-sided device. Similarly, the word line may extend along a second direction (e.g., the y-direction) and may cover (only) one side of the channel portion, without covering the other sides of the channel portion.

[0136] During etching, the selected etching formulation can be selective relative to the sidewalls 1047, so that the sidewalls 1047 can be substantially unaffected (see Figure 41(d), where the structure remains substantially the same after etching at the EE′ section shown). According to another embodiment, such as Figure 43 As shown, the sidewall 1047 can also be etched. The following description still uses the example of the sidewall 1047 not being etched, but these descriptions also apply to the case where the sidewall 1047 is etched.

[0137] According to another embodiment, instead of patterning all gate conductor layers with a common mask, the above can be combined... Figures 35(a) to 37(c) When forming the gate conductor layer for each device layer using the aforementioned process, the formed gate conductor layer is directly patterned as a strip extending along the second direction. Then, an interlayer dielectric layer is similarly formed, and the gate conductor layer of the upper device layer is formed on the interlayer dielectric layer, patterned as a strip extending along the second direction. That is, gate conductor layers can be formed layer by layer and patterned as word lines.

[0138] like Figure 44(a) and 44(b) As shown, electrical isolation can be achieved by depositing and planarizing a dielectric material in the gaps created by the pattern of the word lines (which can stop at the sidewall 1047) to fill the gaps. The filled dielectric material can be the same as the previously formed isolation layer and interlayer dielectric layer, such as SiC, and is therefore integrally shown as 1079.

[0139] Thus, a 3D array of selectable transistors is obtained. Such an array is, for example, combined as described above. Figure 1(a) and 1(b) What is mentioned is only Figure 1(a) and 1(b) The active region of the selection transistor and the word line and bit line structure are mainly shown, but other components such as isolation layers and interlayer dielectric layers are not shown.

[0140] An array of memory elements can be fabricated and electrically connected to a 3D array of selected transistors.

[0141] For example, such as Figure 45(a) and 45(b) As shown, contacts 1083 to each select transistor (particularly its source / drain regions) can be formed in the interlayer dielectric layer 1079. For example, holes can be etched in the interlayer dielectric layer 1079 and filled with metals such as W, Ru, Co, etc., to form the contacts 1083. Due to the stepped structure described above, the contacts 1083 of the select transistors in different layers can be independent of each other.

[0142] Additionally, a redistribution layer can be formed on the 3D array of selected transistors. The redistribution layer may include an interlayer dielectric layer 1081 (e.g., oxide) and redistribution structures 1085 disposed within the interlayer dielectric layer 1081. The redistribution structures 1085 may include redistribution wiring 1085L and redistribution vias 1085V. The redistribution wiring 1085L may extend in a plane substantially parallel to, for example, the surface of the substrate to facilitate wiring routing. The redistribution vias 1085V may enable electrical connections between redistribution wiring 1085L layers. Depending on the design, one or more layers of redistribution wiring 1085L and / or one or more layers of redistribution vias 1085V may be formed. The redistribution wiring 1085L and redistribution vias 1085V may include conductive materials such as copper (Cu).

[0143] Figure 45(a) schematically illustrates the layout of the uppermost redistribution via 1085V in the redistribution structure. Although the redistribution via 1085V is shown herein as arranged substantially along the sidewall 1047, this disclosure is not limited thereto. For example, the redistribution vias 1085V may be arranged substantially uniformly in a plane. Different layouts of the redistribution vias 1085V can be achieved by designing the redistribution structure differently in order to optimize device footprint and device performance. In particular, the 3D array of transistors can be optimized (e.g., less affected or even unaffected by the layout of memory elements) to save area and increase the effective device width or conduction current.

[0144] like Figure 46(a) and 46(b)As shown, a memory element can be formed in the interlayer dielectric layer 1081. For example, as shown in FIG46(a), the memory element 1087 may include a capacitor having a lower electrode 1087L, an upper electrode 1087U, and an intermediate dielectric layer 1087I between them. The lower electrode 1087L and the upper electrode 1087U may include a metal film, and the intermediate dielectric layer 1087I may include a high-k dielectric. Alternatively, as shown in FIG46(b), the memory element 1089 may include an MTJ having a fixed layer 1089L, a tunnel barrier layer 1089I, and a free layer 1089U. For example, the fixed layer 1089L may include CoFeB with a metal film (e.g., Ta, Ru, or Cr) disposed on its lower surface to contact the redistribution via 1085V; the free layer 1089U may include CoFeB with a metal film (e.g., Ta, Ru, or Cr) disposed on its upper surface to contact the subsequently formed contact portion; the tunnel barrier layer 1089I may include, for example, MgO with a thickness of about 0.3 nm to 3 nm. In a planar view, each MTJ may have a diameter of about 10 nm to 100 nm.

[0145] Each storage element can be electrically connected to the uppermost redistribution via 1085V on one side (bottom of the figure) and to a corresponding contact on the other side (top of the figure), such as ground.

[0146] Additionally, an interlayer dielectric layer can be further formed to cover the memory element and the corresponding contacts. This interlayer dielectric layer is shown integrally with the previous interlayer dielectric layer as 1081′.

[0147] Figure 47 An equivalent circuit diagram of a storage device according to an embodiment of the present disclosure is shown schematically.

[0148] like Figure 47 As shown, a memory device according to an embodiment includes an array of memory cells MC. Each MC may include a select transistor and a memory element. One end of the memory element may be connected to a corresponding select transistor to be electrically connected to a corresponding bit line, so as to receive data from the bit line (e.g., in a write operation) or send stored data to the bit line (e.g., in a read operation). The other end of the memory element may be grounded, for example. The gate of the select transistor may be electrically connected to a corresponding word line. The select transistor can be addressed via the word line and the bit line.

[0149] As described above, the select transistors can be configured as a 3D array, such as an M×N×L 3D array. In each of the layers 1 to L, the select transistors can be arranged as an array of M rows × N columns. Accordingly, M bit lines BL_1, BL_2, ..., BL_M can be provided. The select transistors in the corresponding row (e.g., the i-th row) of each layer can be electrically connected to the corresponding bit line BL_i via sub-bit lines Sub_BL_i-1, Sub_BL_i-2, ..., Sub_BL_i-N. Corresponding to each of the layers 1 to L, L word line layers can be provided, and each word line layer (e.g., the k-th layer) can include N word lines WL_1-k, WL_2-k, ..., WL-Nk. Each word line can surround at least a portion of the outer periphery of the channel portion of the select transistor in the corresponding column of the corresponding layer.

[0150] Therefore, each select transistor TR_i-jk can be electrically connected to the corresponding bit line BL_i via the sub-bit line Sub_BL_i-j, and its gate electrode is defined by the corresponding word line WL_j-k, and is thus electrically connected between the word line WL_j-k and the bit line BL_i.

[0151] The storage device according to embodiments of this disclosure can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that works in conjunction with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include, for example, smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

[0152] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0153] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage device, comprising: Multiple device layers are stacked on a substrate along a vertical direction relative to the substrate. Each device layer includes an array of active regions for selecting transistors. The active regions in the array are arranged in rows in a first direction and in columns in a second direction. The active regions include lower source / drain regions and upper source / drain regions at different heights relative to the substrate, and a channel portion between the lower source / drain regions and the upper source / drain regions. Multiple bit lines arranged in the second direction, each of the multiple bit lines extending in the first direction along a corresponding row in the array; A plurality of word line layers are stacked in the vertical direction and correspond to the plurality of device layers respectively, wherein each of the plurality of word line layers includes a plurality of word lines arranged in the first direction, and each of the plurality of word lines extends along the second direction to at least partially surround the channel portion of the active region in the corresponding column of the corresponding device layer of the word line layer; Multiple sub-bit lines extending vertically from each of the multiple bit lines, each of the multiple sub-bit lines being electrically connected to the lower source / drain region of the active region in the corresponding row of the bit line in each device layer above the bit line; and The storage element is electrically connected to the source / drain region of each active region.

2. The storage device according to claim 1, wherein, Each of the multiple bit lines is self-aligned to the corresponding row in the array.

3. The storage device according to claim 1, wherein, The multiple bit lines constitute the lower source / drain region of the active region in the lowest device layer among the multiple device layers.

4. The storage device according to claim 1, wherein, Each of the multiple bit lines also includes: A metal strip extending along the first direction, embedded from one side of the bit line in the second direction.

5. The storage device according to claim 4, wherein, The metal strips in each pair of adjacent bit lines are respectively embedded into the corresponding bit lines from the opposite sides of the two bit lines.

6. The storage device according to claim 1, wherein, Each of the plurality of bit lines further includes a metal layer extending along the first direction.

7. The storage device according to claim 1, wherein, The word line extends along the second direction to surround the channel portion of the active region.

8. The storage device according to claim 1, wherein, The word line extends along the second direction to partially surround the channel portion of the active region.

9. The storage device according to claim 8, wherein, For each channel portion in the corresponding column of the corresponding device layer, the word line extends between the channel portion and one of the two adjacent channel portions adjacent to the channel portion in the second direction, but does not extend between the channel portion and the other of the two adjacent channel portions. The word line extends continuously in the second direction from both sides of the channel portion in the first direction around the channel portion.

10. The storage device according to claim 1, wherein, The sub-bit lines are self-aligned with the corresponding bit lines.

11. The storage device according to claim 1, wherein, On each bit line, a pair of sub-bit lines are set for every pair of adjacent active regions, and the sub-bit lines of each of the multiple bit lines are arranged in a column in the second direction.

12. The storage device according to claim 11, wherein, The sub-line includes: A vertical extension portion extending vertically from the corresponding bit line; and A lateral extension that extends laterally from the vertical extension toward the lower source / drain region. The lateral extensions of each of the pair of sub-bit lines extend in opposite directions.

13. The storage device according to claim 12, wherein, The lateral extension is self-aligned with the lower source / drain region.

14. The storage device according to claim 1, wherein, The active region includes: Lower source / drain layer, wherein the lower source / drain region includes the lower source / drain layer; Upper source / drain layer, wherein the upper source / drain region includes the upper source / drain layer; and The channel layer includes a portion extending between the lower source / drain layer and the upper source / drain layer, the portion defining the channel portion. Wherein, the portion of the channel layer extending between the lower source / drain layer and the upper source / drain layer has its opposite ends in the first direction recessed relative to the corresponding ends of the lower source / drain layer and the upper source / drain layer in the first direction, so that the word line extends through the space defined by the lower source / drain layer and the upper source / drain layer at the opposite ends of the portion of the channel layer extending between the lower source / drain layer and the upper source / drain layer in the first direction and extends in the second direction.

15. The storage device according to claim 14, wherein, The channel layer is an epitaxial layer formed on one sidewall of the lower source / drain layer and the upper source / drain layer in the second direction.

16. The storage device according to claim 15, wherein, In each column, the channel layer for each pair of adjacent active regions is disposed on the back-to-back sidewalls of the lower source / drain layer and the upper source / drain layer of each pair of active regions.

17. The storage device according to claim 15, wherein, The sub-line comprises doped polycrystalline silicon, and the epitaxial layer extends to the sidewalls of the sub-line.

18. The storage device according to claim 14, wherein, The lower source / drain layer and upper source / drain layer of the active region in the lower device layer extend from the opposite side of the sub-bit line to which they are connected, relative to the corresponding ends of the lower source / drain layer and upper source / drain layer of the active region in the upper device layer. The storage device further includes: A contact portion is attached to the extended end of the upper source / drain layer, wherein the storage element is electrically connected to the upper source / drain layer through the contact portion.

19. The storage device of claim 18, further comprising: The redistribution layer includes redistribution lines and redistribution vias. The storage element is electrically connected to the contact portion through the redistribution layer.

20. The storage device of claim 18, further comprising: A metal silicide layer is disposed on the end of the lower source / drain layer of the active region, wherein the metal silicide layer extends on the sidewalls and upper surface of the lower source / drain layer at that end; and A metal silicide layer is disposed on the end of the upper source / drain layer in the active region, wherein the metal silicide layer extends on the sidewall and lower surface of the upper source / drain layer at that end.

21. The storage device according to claim 14, wherein, The lower source / drain layer of each active region extends from the end of the upper source / drain layer of that active region on the side of the sub-bit line to which it is connected.

22. The storage device according to claim 21, wherein, The ends of the lower source / drain layers with active regions in different device layers are substantially aligned in the vertical direction, and the ends of the upper source / drain layers are substantially aligned in the vertical direction.

23. The storage device according to claim 1, further comprising: An isolation layer between different device layers, wherein the isolation layer includes a dielectric interface or boundary.

24. The storage device according to claim 1, wherein, The storage element includes a capacitor or a magnetic tunnel junction.

25. A method for manufacturing a storage device, comprising: Multiple device layers are disposed on a substrate, each device layer including a first source / drain layer, a channel defining layer and a second source / drain layer sequentially stacked in a vertical direction relative to the substrate, and an isolation defining layer is disposed between each device layer; A plurality of vertically extending first processing channels are formed in the plurality of device layers. The plurality of first processing channels are arranged in a first direction and extend along a second direction intersecting the first direction. The bottom of each first processing channel is defined by a first source / drain layer in the lowest device layer of the plurality of device layers. Through the first processing channel, the end of the channel defining layer in each device layer is recessed in the first direction relative to the corresponding ends of the first source / drain layer and the second source / drain layer in the first direction, and a first gate position holding layer is formed in the resulting recess. A portion of the isolation limiting layer adjacent to the first processing channel is replaced with an isolation layer via the first processing channel; The second source / drain layer in each device layer exposed in the first processing channel is recessed relative to the first source / drain layer in a first direction via the first processing channel. On the first source / drain layer of the lowest device layer exposed at the bottom of the first processing channel, a sub-bit line is formed along the sidewall of the first processing channel, and the sub-bit line is in contact with the first source / drain layer of each device layer exposed in the first processing channel. Multiple vertically extending second processing channels are formed in the plurality of device layers. The plurality of second processing channels are alternately arranged with the first processing channel in a first direction and extend along a second direction respectively. The plurality of device layers form a stepped structure at the second processing channels. Through the second processing channel, the end of the channel defining layer in each device layer is recessed in the first direction relative to the corresponding ends of the first source / drain layer and the second source / drain layer in the first direction, and a second gate position holding layer is formed in the resulting recess. The remaining portion of the isolation limiting layer near the second processing channel is replaced with an isolation layer via the second processing channel; Multiple third processing channels are formed that penetrate the multiple device layers, and the multiple third processing channels are arranged in the second direction and extend along the first direction respectively; By selective epitaxial growth, a trench layer is grown on the sidewalls exposed in the third processing channel of each device layer; Multiple fourth processing channels are formed that penetrate the multiple device layers. The multiple fourth processing channels are arranged alternately with the third processing channels in the second direction and extend along the first direction, respectively. The channel defining layer, the first gate position holding layer, and the second gate position holding layer are removed via the fourth processing channel; and A word line layer corresponding to each device layer is formed on the substrate. Each word line layer includes multiple word lines that extend along a second direction to at least partially surround the portion of the channel layer between the first source / drain layer and the second source / drain layer.

26. The method according to claim 25, wherein, The plurality of device layers and the isolation limiting layer are formed by epitaxial growth.

27. The method of claim 25, wherein, The word line passes through the space held by the first gate position holding layer and the second gate position holding layer to bypass the portion of the channel layer between the first source / drain layer and the second source / drain layer and extends continuously in a second direction.

28. The method according to claim 25, wherein, The sub-line is formed using a sidewall forming process.

29. The method according to claim 25, wherein, There is an interface or boundary between the isolation layer replaced by the first processing channel and the isolation layer replaced by the second processing channel.

30. The method according to claim 25, wherein, Forming the plurality of third processing channels includes: Multiple core mold layers are formed that extend along the first direction; A sidewall extending in a first direction is formed on the sidewall of each core mold layer; and Using the plurality of core mold layers and the sidewalls on their respective sidewalls as etching masks, the plurality of device layers are selectively etched. Forming the plurality of fourth processing channels includes: Remove the plurality of core mold layers; and Using the sidewall as an etching mask, the multiple device layers are selectively etched.

31. The method according to claim 25, wherein, Replacing the remaining portion of the isolation layer with an isolation layer via the second processing channel includes removing the remaining portion of the isolation layer via the second processing channel. The method further includes: siliconizing the surface portion of the device layer exposed by the second processing channel and the remaining portion of the isolation limiting layer.

32. The method of claim 25, further comprising: The character lines are patterned such that they cover the surface of the channel layer on one side of the channel defining layer, but do not cover the surface of the channel layer on the side opposite to the channel defining layer.

33. An electronic device comprising a storage device as claimed in any one of claims 1 to 24.

34. The electronic device according to claim 33, wherein, The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

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