Storage device and method of manufacturing the same

Abstract

The application provides a storage device, comprising: a stack structure, and a first source / drain region and a second source / drain region in substrates on both sides of the stack structure; a first self-aligned contact window connected to the first source / drain region; a second self-aligned contact window on the second source / drain region; a first liner structure between the first self-aligned contact window and a first sidewall of the stack structure; and a second liner structure between the second self-aligned contact window and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and are not covered above the stack structure.

Description

Technical Field

[0001] This invention relates to a flash memory device and a method for manufacturing the same. Background Technology

[0002] Flash memory is widely used in many electronic devices because it preserves data even when power is off. Sufficient distance must exist between the gate and source (or drain) contacts of a flash memory chip for electrical isolation. If the distance is too close, leakage current can occur, leading to decreased device reliability. Summary of the Invention

[0003] The present invention provides a flash memory device and a method for manufacturing the same, which can have a large process window when forming a self-aligned contact window and can ensure sufficient distance between the contact window and the gate (word line) to avoid or reduce gate (word line) leakage current and improve device reliability.

[0004] According to an embodiment of the present invention, a storage device is provided, comprising: a substrate having a plurality of isolation structures therein; a first source / drain (S / D) region and a plurality of second (S / D) regions located in the substrate; a stacked structure located on the substrate between the first (S / D) region and the plurality of second (S / D) regions; a first dielectric layer located on the substrate, wherein the first dielectric layer includes a plurality of dielectric pillars separated from each other, located on the plurality of isolation structures; a first self-aligned contact window located on the substrate and connecting the first (S / D) region; a plurality of second self-aligned contact windows located between the plurality of dielectric pillars on the substrate and connecting the plurality of second (S / D) regions; a first liner structure located between the first self-aligned contact windows and a first sidewall of the stacked structure; and a second liner structure located between the plurality of second self-aligned contact windows and a second sidewall of the stacked structure, wherein the first liner structure and the second liner structure are not connected and do not cover the stacked structure.

[0005] According to an embodiment of the present invention, a method for manufacturing a storage device is provided, comprising: forming a plurality of stacked structures on a substrate; forming a plurality of first (S / D) regions and a plurality of second (S / D) regions in the substrate, wherein each first (S / D) region extends along a first direction and the plurality of second (S / D) regions are arranged along the first direction; forming a liner structure on the top surface and sidewalls of the plurality of stacked structures and on the surface of the substrate between the plurality of stacked structures; forming a plurality of sacrificial walls on the liner structure between the plurality of stacked structures; patterning a portion of the plurality of sacrificial walls to form a plurality of alternating first openings and a plurality of sacrificial pillars, and a plurality of... The sacrificial pillars correspond to a plurality of second (S / D) regions, and the plurality of first openings correspond to a plurality of isolation structures between the plurality of second (S / D) regions; a plurality of dielectric pillars are formed in the plurality of first openings; the plurality of sacrificial walls and sacrificial pillars located above and the liner structure below them are removed to form a plurality of first self-aligned contact window openings that expose the plurality of first (S / D) regions and a plurality of second self-aligned contact window openings that expose the plurality of second (S / D) regions; and a plurality of first self-aligned contact windows and a plurality of second self-aligned contact windows are formed in the plurality of first self-aligned contact window openings and the plurality of second self-aligned contact window openings, respectively.

[0006] The method for manufacturing a memory device according to embodiments of the present invention can have a large process window when forming a self-aligned contact window, and can ensure a sufficient distance between the contact window and the gate to avoid or reduce gate leakage current and improve device reliability. Attached Figure Description

[0007] Figures 1A-1N This is a cross-sectional schematic diagram of a method for manufacturing NOR flash memory according to an embodiment of the present invention;

[0008] Figures 2A-2C This is a top view of a method for manufacturing NOR flash memory according to an embodiment of the present invention. Detailed Implementation

[0009] refer to Figure 1A A method for manufacturing NOR flash memory includes the following steps: A substrate 100 is provided, such as a silicon substrate. The substrate 100 has a memory cell region R1 and a peripheral region R2. A plurality of isolation structures 104 are formed in the substrate 100. A plurality of stacked structures 110 extending along the X direction are formed on the substrate 100 in the memory cell region R1, and a stacked structure 120 extending along the X direction is formed on the substrate 100 in the peripheral region R2.

[0010] The stacked structure 110 includes, for example, a tunneling dielectric layer 111, a floating gate 112, an inter-gate dielectric layer 113, a control gate 114, and a capping layer 115 sequentially stacked along the Z-direction on a substrate 100. The tunneling dielectric layer 111 is, for example, silicon oxide. The floating gate 112 is, for example, doped polysilicon. The inter-gate dielectric layer 113 is, for example, a composite layer of silicon oxide, silicon nitride, and silicon oxide (ONO). The control gate 114 is, for example, doped polysilicon. The capping layer 115 is, for example, silicon oxide. The control gate 114 and the capping layer 115 can be strip-shaped structures along the direction of penetration into the paper.

[0011] The stacked structure 120 includes a gate dielectric layer 121 and a gate conductor layer 122 stacked along the Z direction. The gate dielectric layer 121 is, for example, silicon oxide, silicon oxynitride, or a combination thereof. The gate conductor layer 122 is, for example, doped polysilicon.

[0012] refer to Figure 1A and Figure 2A An ion implantation process is performed on the substrate 100 of the memory cell region R1 to form a source / drain (S / D) region 102S and multiple S / D regions 102D on both sides of each stacked structure 110. The S / D region 102S can serve as the source region, and is therefore simply referred to as the source region 102S; the S / D region 102D can serve as the drain region, and is therefore simply referred to as the drain region 102D. Figure 2A As shown, the source region 102S can be a strip-shaped structure extending along the Y direction; while the multiple drain regions 102D can be multiple block-shaped structures arranged along the Y direction sandwiched between two adjacent stacked structures 110. The source region 102S and drain region 102D are, for example, N-type or P-type doped regions. Figure 2A Only a portion of the components are shown. Figure 1A The storage cell area R1 is Figure 2A A cross-sectional view of line I-I'.

[0013] refer to Figure 1AA liner structure 130 is formed comprehensively on the substrate 100. The liner structure 130 may be a plurality of stacked structures 110 conformally formed in the memory cell region R1 and on the gate conductor layer 122 of the peripheral region R2. The liner structure 130 may cover the top surface 110a, sidewalls 110s1 and 1102s2 of the stacked structures 110 and the surface of the substrate 100 adjacent to the stacked structures 110. In the memory cell region R1, the liner structure 130 is conformally formed on the stacked structures 110 and does not fill the gaps between the stacked structures 110, thus forming an opening 116. The mobile ions mentioned herein are, for example, Fe, Cu, Al, In, Co ions. Since the top surface 110a and side walls 110s1 and 1102s2 of the stacked structure 110 are all covered by the liner structure 130, the liner structure 130 can protect the stacked structure 110 from interference by ions, reduce or prevent ions from diffusing into the stacked structure 110 and thus causing damage to the storage device.

[0014] The liner structure 130 may include a material different from the top cap layer 115. The liner structure 130 may be a dielectric material, such as an oxide or nitride. The liner structure 130 may be a single layer or multiple layers. The liner structure 130 may be layers 130a, 130b, and 130c sequentially stacked on the stack structure 110. Layers 130a / 130b / 130c may be, for example, silicon oxide / silicon nitride / silicon oxide layers.

[0015] Subsequently, a sacrificial material layer 132 is formed all over the substrate 100 to fill the openings 116 between the stacked structures 110 and cover the liner structure 130. The sacrificial material layer 132 is, for example, polysilicon.

[0016] refer to Figure 1B The sacrificial material layer 132 in the peripheral region R2 is removed by photolithography and etching processes, leaving the sacrificial material layer 132 in the memory cell region R1. Then, a dielectric layer 134 is formed all over the substrate 100. The dielectric layer 134 is, for example, silicon oxide.

[0017] refer to Figure 1C A planarization process is performed on dielectric layer 134 to remove the liner structure 130, sacrificial material layer 132, and dielectric layer 134 above the top cover layer 115. This forms a sacrificial wall 132a and liner structure 130' in the memory cell region R1, and a dielectric layer 134a in the peripheral region R2. The top surfaces of the sacrificial wall 132a, liner structure 130', and dielectric layer 134a are coplanar. The sacrificial wall 132a extends between the stacked structures 110.

[0018] refer to Figure 1D and Figure 2AA hard mask layer 136 is formed on the substrate 100 of the memory cell region R1 and the peripheral region R2. The hard mask layer 136 is, for example, silicon nitride. Figure 1D for Figure 2B The diagram shows cross-sectional views of lines I-I' and II-II'. The hard mask layer 136 is patterned using photolithography and etching processes to form multiple openings OP1. The openings OP1 expose the sacrificial wall 132a above the isolation structure 104 located between the stacked structures 110 and the drain regions 102D in the memory cell region R1. The hard mask layer 136 continuously extends over the sacrificial wall 132a above the source region 102S, the stacked structure 110, and the drain region 102D. Only the sacrificial wall 132a exposed by the openings OP1 is exposed in the memory cell region R1. Therefore, even if misalignment occurs, the source region 102S, the stacked structure 110, and the substrate structure 130' will still be covered by the sacrificial wall 132a and will not be exposed.

[0019] refer to Figure 1E Using a hard mask layer 136 as a mask, an etching process is performed to remove the sacrificial wall 132a exposed by the opening OP1, forming multiple openings OP2 and multiple sacrificial pillars 132b. The multiple openings OP2 expose the liner structure 130' located between the stacked structures 110 and above the isolation structure 104. The multiple openings OP2 are arranged in a row in the Y direction. The multiple sacrificial pillars 132b are located above the isolation structure and arranged in a row along the Y direction, separated from each other by the multiple openings OP2.

[0020] If misalignment occurs during photolithography, the source region 102S and the top of the stacked structure 110 will still be covered by the sacrificial wall 132a and will not be exposed. Therefore, during the etching process, the stacked structure 110 and the liner structure 130' of its sidewalls can be protected from etching damage. This can prevent leakage current caused by the liner structure 130' being damaged, which would result in the distance between the self-aligned contact windows 142a, 142b and the conductor layer (control gate) 114 of the stacked structure 110 being too small.

[0021] refer to Figure 1F A stop layer 138 and a dielectric layer 140 are sequentially formed over the entire substrate 100. The stop layer 138 covers the hard mask layer 136 and fills the opening OP2, but does not completely fill the opening OP2. The dielectric layer 140 covers the stop layer 138 and fills the remaining space of the opening OP2. The stop layer 138 is, for example, silicon nitride; the dielectric layer 140 is, for example, silicon oxide.

[0022] refer to Figure 1GA planarization process, such as chemical mechanical polishing, is performed to remove the dielectric layer 140 on the stop layer 138, forming dielectric pillars 140b in the opening OP2, leaving the dielectric layer 140 in the peripheral region (not shown). The top surface of the dielectric pillars 140b is coplanar with the top surface of the stop layer 138.

[0023] refer to Figure 1H The stop layer 138 and hard mask layer 136 are removed. Next, a wet etching process is performed to remove the sacrificial wall 132a and sacrificial pillar 132b, forming openings 116a and 116b. Openings 116b and dielectric pillars 140b alternate in the Y direction.

[0024] refer to Figure 1I The liner structure 130' and tunneling dielectric layer 111 at the bottom of openings 116a and 116b are removed to form openings 116a' and 116b'. The self-aligned contact window opening 116a' exposes the source region 102S; the self-aligned contact window opening 116b' exposes the drain region 102D. The self-aligned contact window opening 116b' and dielectric pillar 140b alternate with each other in the Y direction. The liner structure 130' is separated into liner structures 130A' and 130B' by the stacked structure 110. Since the liner structures 130A' and 130B' are only exposed at this stage, the liner structures 130A' and 130B' extending downward from the sidewall of the top cover layer 115 of the stacked structure 110 to the sidewall of the floating gate 112 have approximately the same thickness, without the problem of the liner structures 130A' and 130B' being thinner in certain areas (e.g., the sidewall of the top cover layer 115).

[0025] refer to Figure 1J A conductive layer (e.g., tungsten) is formed over the substrate 100 and filled into the self-aligned contact window openings 116a' and 116b'. The conductive layer is then planarized, for example, by chemical mechanical polishing, to form the self-aligned contact windows 142a and 142b. The top surfaces of the self-aligned contact windows 142a and 142b are connected to the top surface of the substrate structure 130', the top surface of the capping layer 115, and the dielectric layer 134a (shown in...). Figure 1C and Figure 1N The top surfaces of the self-aligned contact windows 142a are coplanar. Each self-aligned contact window 142a is, for example, a long strip extending continuously in the Y direction and electrically connected to the source region 102S. A plurality of self-aligned contact windows 142b are, for example, cylindrical and arranged in a row alternately with a plurality of dielectric pillars 140b in the Y direction, and electrically connected to a plurality of drain regions 102D.

[0026] Self-aligning contact windows 142a and 142b each include an upper portion 142U and a lower portion 142L. The upper portion 142U is located between the top surface of the control gate 114 and the top surface of the top cover layer 115, and has a first height H1. The lower portion 142L connects to the upper portion 142U, is located between the top surface of the control gate 114 and the top surface of the substrate 100, and has a second height H2. The first height H1 is smaller than the second height H2.

[0027] refer to Figure 1K and 1N A stop layer 144 is formed on the substrate 100. Next, a dielectric layer 146 is formed on the stop layer 144. Figure 1K Stop layer 144 covers stacked structure 110, liner structure 130', self-aligned contact windows 142a and 142b and dielectric layer 134a (shown in...). Figure 1C and Figure 1N The material of the stop layer 144 includes silicon nitride; the material of the dielectric layer 146 includes silicon oxide.

[0028] refer to Figure 1L and Figure 1M The photolithography and etching processes are performed, using stop layer 144 as the etching stop layer. Openings 148a and 148b are formed in dielectric layer 146, and then the stop layer 144 at the bottom of openings 148a and 148b is etched to form contact window openings 148a' and 148b'. Contact window openings 148a' and 148b' expose the top surfaces of self-aligned contact windows 142a and 142b and the top surfaces of substrate structures 130A' and 130B'. The etching depth can be controlled by time mode during the etching of stop layer 144. Therefore, even if substrate structures 130A' and 130B' are etched, the degree of etching can be controlled within a suitable range, so that substrate structures 130A' and 130B' still have sufficient height to allow for the subsequent formation of contact windows 150a and 150b. Figure 1N There is sufficient distance between the gate and the control gate 114.

[0029] refer to Figure 1N A conductive layer (e.g., tungsten) is formed over the substrate 100, filling the contact window openings 148a' and 148b'. The conductive layer is then planarized, for example, by chemical mechanical polishing, to form multiple contact windows 150a and 150b. The top surfaces of the multiple contact windows 150a and 150b are coplanar with the top surface of the dielectric layer 146. The contact windows 150a / 150b are electrically connected to the source / drain regions (102S / 102D) via self-aligned contact windows 142a / 142b. The multiple contact windows 150a and 150b can be arranged to appear in the same cross-section or different cross-sections. Figure 1N Show Figure 2CCross-sectional view of storage cell area R1 and surrounding area R2 of lines I-I' and II-II'.

[0030] Contact windows 150a and 150b can contact self-aligning contact windows 142a and 142b, and can also contact liner structures 130A' and 130B'. Therefore, the bottom width W of contact window 150a in the X direction... 1a The top width W of the self-aligned contact window 142a in the X direction is greater than the width of the self-aligned contact window 142a. 2a The bottom width W of contact window 150b in the X direction 1b The top width W of the self-aligned contact window 142b in the X direction is greater than the width of the top width W. 2b .

[0031] Furthermore, the liner structures 130A' and 130B' do not extend upward to the sidewalls of the contact windows 150a and 150b. Therefore, the contact windows 150a and 150b are located in the dielectric layer 146 and the stop layer 144, and are in direct contact with the sidewalls of the dielectric layer 146 and the stop layer 144. There are no liner structures 130A' and 130B' between them.

[0032] The hard mask layer of this invention covers the stacked structure and substrate structure of the source and drain regions. The opening of the mask layer only exposes the sacrificial material layer above the isolation structure between the drain regions. Therefore, it can avoid the substrate structure on the sidewalls of the stacked structure from being etched and thinned, thereby avoiding leakage current caused by the insufficient distance between the self-aligned contact window and the control gate of the stacked structure. Therefore, the method of this invention can have a large process window when forming the self-aligned contact window and can improve the reliability of the device.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage device, characterized in that: Substrate, the substrate having multiple isolation structures; A first source / drain region and a plurality of second source / drain regions are located in the substrate; A stacked structure is located on the substrate between the first source / drain region and the plurality of second source / drain regions; A first dielectric layer is located on the substrate, wherein the first dielectric layer includes a plurality of dielectric pillars separated from each other, wherein the plurality of dielectric pillars are located on the plurality of isolation structures; A first self-aligned contact window is located on the substrate and is connected to the first source / drain region; Multiple second self-aligned contact windows are located between the multiple dielectric pillars on the substrate and connect the multiple second source / drain regions; A first liner structure is located between the first self-aligning contact window and the first sidewall of the stacked structure; and The second liner structure is located between the plurality of second self-aligning contact windows and the second sidewall of the stacked structure. The first liner structure is not connected to the second liner structure and does not cover the stacked structure. The first and second liner structures are dielectric materials. The top surfaces of the first liner structure and the second liner structure are coplanar with the top surfaces of the first self-aligning contact window and the plurality of second self-aligning contact windows.

2. The storage device according to claim 1, wherein the stacking structure comprises: A floating gate is located above the substrate; A tunneling dielectric layer is located between the floating gate and the substrate; Control gate; Located above the floating gate; An inter-gate dielectric layer is located between the floating gate and the control gate; and The top cover layer is located on the control gate.

3. The storage device according to claim 2, wherein the top surface of the first liner structure and the second liner structure are coplanar with the top surface of the top cover layer of the stacked structure.

4. The storage device according to claim 2, wherein the first liner structure and the second liner structure are multi-layered structures, wherein, The multi-layer structure extends continuously from the side wall of the floating gate to the side wall of the top cover layer.

5. The storage device according to claim 2, wherein the first self-aligning contact window and the second self-aligning contact window each comprise: The upper part is located between the top surface of the control gate and the top surface of the top cover layer; and The lower part connects to the upper part and is located between the top surface of the control gate and the top surface of the substrate.

6. The storage device according to claim 1, further comprising: A second dielectric layer covers the first dielectric layer and the stacked structure; A first contact window is located in the second dielectric layer and is connected to the first self-aligned contact window, wherein the bottom width of the first contact window is greater than the top width of the first self-aligned contact window; and A plurality of second contact windows are located in the second dielectric layer and are respectively located on the plurality of second self-aligned contact windows, wherein the bottom width of the plurality of second contact windows is greater than the top width of the plurality of second self-aligned contact windows.

7. The storage device of claim 6, wherein the bottom surface of the first contact window contacts the top surface of the first liner structure; and the bottom surfaces of the plurality of second contact windows contact the top surface of the second liner structure.

8. The storage device of claim 7, wherein the first liner structure does not extend between the second dielectric layer and the first contact window, and the second liner structure does not extend between the second dielectric layer and the plurality of second contact windows.

9. The storage device according to claim 7, further comprising: A stop layer is located between the second dielectric layer and the first dielectric layer, and between the second dielectric layer and the stacked structure.

10. The storage device of claim 9, wherein the first contact window and the plurality of second contact windows are respectively in contact with the sidewalls of the second dielectric layer and the stop layer.

11. A method for manufacturing a storage device, characterized in that: Multiple stacked structures are formed on the substrate; A plurality of first source / drain regions and a plurality of second source / drain regions are formed in the substrate, wherein each first source / drain region extends along a first direction, and the plurality of second source / drain regions are arranged along the first direction; A liner structure is formed on the top surface and sidewalls of the plurality of stacked structures and on the surface of the substrate between the plurality of stacked structures; Multiple sacrificial walls are formed on the liner structure between the multiple stacked structures; The patterned portion of the plurality of sacrificial walls forms a plurality of alternating first openings and a plurality of sacrificial pillars, the plurality of sacrificial pillars corresponding to the plurality of second source / drain regions, and the plurality of first openings corresponding to a plurality of isolation structures between the plurality of second source / drain regions, wherein the method for patterning the plurality of sacrificial walls includes: A hard mask layer is formed on the substrate, the hard mask layer covering the plurality of sacrificial walls, the stacked structure and the liner structure above the first source / drain regions, and having a plurality of second openings to expose the plurality of sacrificial walls above the plurality of second source / drain regions; A first dielectric layer is formed on the substrate and filled into the plurality of first openings to form a plurality of dielectric pillars; Remove the plurality of sacrificial walls and sacrificial pillars located above and the liner structure below them to form a plurality of first self-aligned contact window openings exposing the plurality of first source / drain regions and a plurality of second self-aligned contact window openings exposing the plurality of second source / drain regions; and A plurality of first self-aligned contact windows and a plurality of second self-aligned contact windows are formed in the plurality of first self-aligned contact window openings and the plurality of second self-aligned contact window openings, respectively.

12. The method of manufacturing a storage device according to claim 11, further comprising: A stop layer is formed over the substrate to cover the first dielectric layer and the stacked structure; A second dielectric layer is formed on the stop layer; A first contact window is formed in the second dielectric layer and the stop layer to connect the first self-aligned contact window, wherein the bottom width of the first contact window is greater than the top width of the first self-aligned contact window; and A second contact window is formed in the second dielectric layer and the stop layer to connect the second self-aligned contact window, wherein the bottom width of the second contact window is greater than the top width of the second self-aligned contact window.

13. The method of manufacturing a storage device according to claim 12, wherein the first dielectric layer, the stop layer and the second dielectric layer further extend to cover a peripheral region of the substrate.

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