Display panel and display device comprising the same

Abstract

A display panel and a display device including the same. Disclosed is a display panel including: a substrate divided into a first region and a second region located outside the first region; a buffer layer provided in the first region and the second region and on the substrate; a first thin film transistor including a polycrystalline semiconductor layer provided in the first region and on the buffer layer, and a first gate provided on the polycrystalline semiconductor layer; a second thin film transistor including an oxide semiconductor layer provided in the first region and on the buffer layer, and a second gate provided on the oxide semiconductor layer; a first intermediate insulating layer provided between the first region and the second region and interposed between the first thin film transistor and the second thin film transistor; a first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and a second contact hole passing through the first intermediate insulating layer in the second region.

Description

Technical Field

[0001] This disclosure relates to a thin-film transistor substrate and a display device using the thin-film transistor substrate. Background Technology

[0002] With the development of the information society, the demand for display devices used to display images in various forms is also increasing. The display device field has rapidly transformed into thin, lightweight, and large-area flat panel display devices (FPDs) that replace bulky cathode ray tubes (CRTs). Flat panel display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode (OLED) displays, and electrophoretic display devices (EDs).

[0003] Active liquid crystal display (LCD), organic light-emitting diode (OLED) display, and electrophoretic display include a thin-film transistor (TFT) substrate, wherein TFTs are distributed in pixel regions arranged in a matrix. LCD displays images by adjusting the transmittance of liquid crystals using an electric field. OLED displays display images by forming organic light-emitting devices within the pixels themselves arranged in a matrix.

[0004] Organic light-emitting diode (OLED) display devices are self-emissive elements that emit light themselves, exhibiting fast response times and significant advantages in luminous efficiency, brightness, and viewing angle. In particular, OLED display devices utilizing the excellent energy efficiency of organic light-emitting diodes are broadly classified into passive matrix OLED displays (PMOLED) and active matrix OLED displays (AMOLED).

[0005] With the rapid development of personal electronic devices, display devices have also been developed as products with excellent portability and / or wearability. Therefore, in order to apply display devices to portable or wearable devices, low-power display devices are required. Currently developed display device-related technologies have limitations in achieving low power consumption. Summary of the Invention

[0006] In order to overcome the problems of the prior art, the purpose of this disclosure is to provide a thin film transistor substrate that includes two or more types of thin film transistors on the same substrate, and to provide a display device using the thin film transistor substrate.

[0007] The purpose of this disclosure is to make the characteristics of the second thin-film transistor device consistent, regardless of where the pixels are arranged.

[0008] As a means to achieve the above objectives, this disclosure has the following implementation features.

[0009] One embodiment is a display panel comprising: a substrate divided into a first region and a second region located outside the first region; a buffer layer disposed in the first region and the second region and disposed on the substrate; a first thin-film transistor comprising a polycrystalline semiconductor layer disposed in the first region and disposed on the buffer layer, and a first gate disposed on the polycrystalline semiconductor layer; a second thin-film transistor comprising an oxide semiconductor layer disposed in the first region and disposed on the buffer layer, and a second gate disposed on the oxide semiconductor layer; a first intermediate insulating layer disposed between the first region and the second region and interposed between the first thin-film transistor and the second thin-film transistor; a first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and a second contact hole passing through the first intermediate insulating layer in the second region.

[0010] The first thin-film transistor also includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate.

[0011] The first contact hole and the second contact hole pass through the first gate insulating layer.

[0012] The display panel also includes a passivation layer disposed in the first region and the second region and on the second thin-film transistor. The passivation layer is connected to the buffer layer through a second contact hole.

[0013] The second thin-film transistor also includes a second gate insulating layer interposed between the oxide semiconductor layer and the second gate.

[0014] The first and second contact holes pass through the second gate insulating layer.

[0015] The display panel also includes a passivation layer disposed in the first region and the second region and on the second thin-film transistor. The passivation layer fills the second contact hole.

[0016] The polycrystalline semiconductor layer is further disposed in the second region.

[0017] The display panel also includes a passivation layer disposed in the first region and the second region and on the second thin-film transistor. The passivation layer is connected to the polycrystalline semiconductor layer disposed in the second region through a second contact hole.

[0018] The first thin-film transistor also includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first intermediate insulating layer.

[0019] The first contact hole and the second contact hole pass through the first gate insulating layer.

[0020] The first area is the display area with multiple pixels, and the second area is the non-display area.

[0021] The plurality of pixels includes a plurality of edge pixels arranged at the boundary between the first region and the second region. The second contact hole is configured to surround the plurality of edge pixels.

[0022] Each pixel has a first length in a first direction and a second length in a second direction perpendicular to the first direction. The first length is shorter than the second length. A second contact hole is disposed in the second region at a distance shorter than the first length from the boundary between the first and second regions.

[0023] One embodiment is a display panel, the display panel comprising: a display area having a plurality of pixels; and a non-display area located outside the display area, wherein each of the plurality of pixels includes: a first thin-film transistor and a second thin-film transistor having a different nature from the first thin-film transistor; an intermediate insulating layer disposed in the display area and the non-display area and interposed between the first thin-film transistor and the second thin-film transistor; and a first contact hole passing through the intermediate insulating layer, wherein the second thin-film transistor in an edge pixel located at the boundary between the display area and the non-display area is adjacent to the non-display area, and wherein a second contact hole is disposed in the non-display area adjacent to the second thin-film transistor in the edge pixel, and the second contact hole passes through the intermediate insulating layer.

[0024] The first thin-film transistor includes a polycrystalline semiconductor layer, a first gate, and a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate, and the second thin-film transistor includes an oxide semiconductor layer.

[0025] The intermediate insulating layer includes a nitride layer disposed near the polycrystalline semiconductor layer and an oxide layer disposed near the oxide semiconductor layer.

[0026] A display device is disclosed, comprising the aforementioned display panel; a driving circuit; and a cover glass covering the display panel.

[0027] The display panel according to embodiments of the present disclosure includes two or more types of thin-film transistors on a substrate. Furthermore, the second thin-film transistor device can have consistent characteristics, regardless of the pixel arrangement position.

[0028] Appendix 1. A display panel, the display panel comprising:

[0029] A substrate, the substrate being divided into a first region and a second region located outside the first region;

[0030] A buffer layer is disposed in the first region and the second region and on the substrate;

[0031] A first thin-film transistor, the first thin-film transistor including a polycrystalline semiconductor layer and a first gate, the polycrystalline semiconductor layer being disposed in the first region and disposed on the buffer layer, and the first gate being disposed on the polycrystalline semiconductor layer;

[0032] A second thin-film transistor, comprising an oxide semiconductor layer and a second gate, wherein the oxide semiconductor layer is disposed in the first region and on the buffer layer, and the second gate is disposed on the oxide semiconductor layer;

[0033] A first intermediate insulating layer is disposed in the first region and the second region, and is inserted between the first thin-film transistor and the second thin-film transistor;

[0034] A first contact hole, the first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and

[0035] The second contact hole passes through the first intermediate insulating layer in the second region.

[0036] Note 2. The display panel according to Note 1, wherein the first thin-film transistor further includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate.

[0037] Note 3. The display panel according to Note 2, wherein the first contact hole and the second contact hole pass through the first gate insulating layer.

[0038] Note 4. According to the display panel described in Note 3, the display panel further includes a passivation layer disposed in the first region and the second region and disposed on the second thin-film transistor, wherein the passivation layer is connected to the buffer layer through the second contact hole.

[0039] Note 5. The display panel according to Note 1, wherein the second thin-film transistor further includes a second gate insulating layer interposed between the oxide semiconductor layer and the second gate.

[0040] Note 6. The display panel according to Note 5, wherein the first contact hole and the second contact hole pass through the second gate insulating layer.

[0041] Note 7. The display panel according to Note 1 further includes a passivation layer disposed in the first region and the second region and disposed on the second thin-film transistor, wherein the passivation layer fills the second contact hole.

[0042] Note 8. The display panel according to Note 1, wherein the polycrystalline semiconductor layer is further disposed in the second region.

[0043] Note 9. The display panel according to Note 8 further includes a passivation layer disposed in the first region and the second region and disposed on the second thin-film transistor, wherein the passivation layer is connected to the polycrystalline semiconductor layer disposed in the second region through the second contact hole.

[0044] Note 10. The display panel according to Note 8, wherein the first thin-film transistor further includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first intermediate insulating layer.

[0045] Note 11. The display panel according to Note 10, wherein the first contact hole and the second contact hole pass through the first gate insulating layer.

[0046] Note 12. The display panel according to Note 1,

[0047] The first region is a display area with multiple pixels arranged thereon, and

[0048] The second area is a non-display area.

[0049] Note 13. The display panel according to Note 12,

[0050] The plurality of pixels includes a plurality of edge pixels arranged at the boundary between the first region and the second region, and

[0051] The second contact hole is configured to surround the plurality of edge pixels.

[0052] Note 14. The display panel according to Note 12,

[0053] Each pixel has a first length in a first direction and a second length in a second direction perpendicular to the first direction.

[0054] Wherein, the first length is shorter than the second length, and

[0055] The second contact hole is disposed in the second region at a distance shorter than the first length from the boundary between the first region and the second region.

[0056] Appendix 15. A display panel, the display panel comprising:

[0057] A display area with multiple pixels; and

[0058] The non-display area located outside the display area,

[0059] Each of the plurality of pixels includes:

[0060] A first thin-film transistor and a second thin-film transistor with different properties from the first thin-film transistor;

[0061] An intermediate insulating layer is disposed in the display area and the non-display area, and is interposed between the first thin-film transistor and the second thin-film transistor; and

[0062] The first contact hole passes through the intermediate insulating layer.

[0063] Wherein, the second thin-film transistor in the edge pixel located at the boundary between the display area and the non-display area is adjacent to the non-display area, and

[0064] In the non-display area, a second contact hole is provided adjacent to the second thin-film transistor in the edge pixel, and the second contact hole passes through the intermediate insulating layer.

[0065] Note 16. The display panel according to Note 15, wherein the first thin-film transistor includes a polycrystalline semiconductor layer, a first gate and a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate, and the second thin-film transistor includes an oxide semiconductor layer.

[0066] Note 17. The display panel according to Note 16, wherein the intermediate insulating layer comprises a nitride layer disposed near the polycrystalline semiconductor layer and an oxide layer disposed near the oxide semiconductor layer.

[0067] Appendix 18. A display device, the display device comprising:

[0068] The display panel described in any of the appendices 1 to 17;

[0069] Drive circuit; and

[0070] Cover glass covering the display panel. Attached Figure Description

[0071] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure;

[0072] Figure 2 yes Figure 1 An enlarged view of the "AA" part;

[0073] Figure 3 It is along Figure 2 The cross-sectional view taken by the cutting line I-I';

[0074] Figures 4 to 7 It is according to the embodiments of this disclosure. Figure 2 A cross-sectional view taken from line I-I'; and

[0075] Figure 8 This is a view used to describe the arrangement of the second contact hole according to an embodiment of the present disclosure. Detailed Implementation

[0076] Since the shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments of this disclosure are illustrative, this disclosure is not limited to the details shown. Throughout the disclosure, the same reference numerals correspond to the same elements. Furthermore, throughout the description of this disclosure, detailed descriptions of known technologies incorporated herein will be omitted where such descriptions might obscure the subject matter of this disclosure. Terms such as "comprising," "having," and "constituting" are used as mentioned in this disclosure, and other terms may be added unless the term "only" is used. Components expressed in the singular include their plural forms unless otherwise expressly stated.

[0077] When interpreting a component, it is interpreted as including the error range, even if there is no separate explicit description.

[0078] When describing positional relationships, such as "above", "over", "below", "adjacent", etc., one or more other components may be located between the two components, as long as the terms "directly" or "immediately" are not used.

[0079] While various components may be described using terms such as first and second, these components are not limited to the terms described above. These terms are used only to distinguish one component from others. Therefore, within the spirit of this disclosure, the first component described below may be the second component.

[0080] Throughout the disclosure, the same reference numerals correspond to the same elements.

[0081] In the following description, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings. The component names used in the following description are chosen to facilitate the writing of the specification and may differ from the component names of the actual product.

[0082] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure.

[0083] The display device 100 may include a display panel 110, a cover glass 120, and a driving circuit 160.

[0084] The display panel 110 can be divided into a display area DA and a non-display area NDA, where the non-display area NDA is the border area surrounding the edge of the display area DA.

[0085] The non-display area NDA may include pad portions defined outside the display area DA. Multiple subpixels may be disposed within the display area DA. Subpixels may be arranged within the display area DA in a red (R), green (G), blue (B) configuration or in a R, G, B, and white (W) configuration to produce full color. Subpixels may be divided by intersecting gating lines and data lines.

[0086] The cover glass 120 is used to cover the front side of the display panel 110 and to protect the display panel 110.

[0087] The driving circuit 160 may be disposed on the rear side of the display panel 110. The driving circuit 160 may include bumps (or terminals). The bumps of the driving circuit 160 may be bonded to the pads of the pad portion via anisotropic conductive films. The driving circuit 160 may be a chip-on-film (COF), wherein the driving IC is mounted on a flexible film.

[0088] Furthermore, the driving circuit 160 can be implemented as a chip-on-glass (COG) type, in which the driving IC is directly bonded to pads on the substrate via COG technology. Additionally, the driving circuit 160 can be a flexible circuit, such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

[0089] In the display device 100, in addition to the display area DA in which the input image is formed, sufficient space must be available for placing pads and the like. This space corresponds to the bezel area, which can be recognized by a user located in front of the display device 100. This can be a factor that reduces aesthetics.

[0090] Figure 2 yes Figure 1 An enlarged view of the "AA" section.

[0091] refer to Figure 1 and Figure 2 The “AA” part is the lower right edge of the display panel 110 and corresponds to the boundary between the display area DA and the non-display area NDA.

[0092] The first pixel P1 and the second pixel P2 are arranged in the display area DA.

[0093] The pixels are arranged in the left and right regions of the first pixel P1. That is, adjacent pixels are located on the left and right sides of the first pixel P1.

[0094] The second pixel P2 (i.e., the edge pixel) is located at the boundary between the display area DA and the non-display area NDA. When a pixel is placed in the area to the left of the second pixel P2, no pixel is placed in the area to the right of the second pixel P2. That is, although adjacent pixels are placed to the left of the second pixel P2, adjacent pixels are not placed to the right of the second pixel P2.

[0095] <Comparative Example>

[0096] Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0097] The display panel 110 according to an embodiment of the present disclosure is characterized in that two types of thin-film transistors are disposed on a substrate.

[0098] The display panel according to this embodiment includes a first thin-film transistor T1 and a second thin-film transistor T2 disposed on a substrate SUB. The first thin-film transistor T1 and the second thin-film transistor T2 may be arranged apart from each other or adjacent to each other. Alternatively, the two thin-film transistors may be arranged in a stacked configuration.

[0099] The substrate SUB is divided into a first region and a second region located outside the first region. The first region may be a display region DA in which multiple pixels are arranged, and the second region may be a non-display region NDA.

[0100] A buffer layer BUF is stacked over the entire surface of the substrate SUB. In some cases, the buffer layer BUF can be omitted. Alternatively, the buffer layer BUF can have a structure in which multiple thin film layers are stacked. Here, for convenience, the buffer layer BUF is described as having a single-layer structure. Furthermore, a light-blocking layer can optionally be further provided only in the necessary portion between the buffer layer BUF and the substrate SUB. The light-blocking layer can be formed to prevent external light from entering the semiconductor layer of the thin-film transistor disposed on the light-blocking layer.

[0101] A first semiconductor layer A1 is disposed on the buffer layer BUF. The first semiconductor layer A1 includes the channel region of the first thin-film transistor T1. The channel region is defined as the area where the first gate G1 and the first semiconductor layer A1 overlap. Since the first gate G1 overlaps with the central portion of the first thin-film transistor T1, the central portion of the first thin-film transistor T1 becomes the channel region. Both sides of the channel region are doped with impurities and are defined as the source region and the drain region.

[0102] When the first thin-film transistor T1 is a thin-film transistor used as a driving element, preferably, the first thin-film transistor T1 can have characteristics suitable for performing high-speed driving processing. For example, a P-MOS or N-MOS type thin-film transistor can be used, or a C-MOS type thin-film transistor including both can be provided. In one embodiment, the P-MOS, N-MOS, and / or C-MOS type thin-film transistor can include a polycrystalline semiconductor material, such as polycrystalline silicon. Furthermore, in one embodiment, the first thin-film transistor T1 can have a top-gate structure.

[0103] A gate insulating layer GI is stacked over the entire surface of a substrate SUB on which a first semiconductor layer A1 is disposed. The gate insulating layer GI can be made of silicon nitride (SiNx) or silicon oxide (SiOx). When the gate insulating layer GI is made of silicon nitride (SiNx), a large amount of hydrogen may be contained within the gate insulating layer GI due to the manufacturing process. Since this hydrogen can diffuse out of the gate insulating layer GI in subsequent processes, it is preferable that the gate insulating layer GI be made of silicon oxide material.

[0104] In the first semiconductor layer A1, which includes polycrystalline silicon, hydrogen diffusion can have a positive effect. However, hydrogen diffusion may negatively affect the second thin-film transistor T2, which has properties different from those of the first thin-film transistor T1. Therefore, as in this disclosure, when thin-film transistors made of different materials are formed on the same substrate, it is more preferable to use silicon oxide (SiOx), which does not particularly affect the device. In this case, when the gate insulating layer GI is made of silicon nitride (SiNx), the degree of hydrogen diffusion may increase. Therefore, considering various factors, it is recommended that the first gate insulating layer GI1 be made of silicon oxide (SiOx). X Made from ).

[0105] A first gate G1 is disposed on a first gate insulating layer GI1. The first gate G1 is configured to overlap with the central portion of the first semiconductor layer A1.

[0106] A first intermediate insulating layer ILD1 is disposed on the first gate G1. The first intermediate insulating layer ILD1 is stacked to cover the first gate G1. Preferably, the first intermediate insulating layer ILD1 may have a multilayer structure, wherein a nitride layer SIN comprising silicon nitride (SiNx) and an oxide layer SiO comprising silicon oxide (SiOx) are alternately stacked. Here, a two-layer structure as a minimum component will be described for convenience, wherein the oxide layer SiO is stacked on the nitride layer SIN.

[0107] The nitride layer SIN is used to diffuse the hydrogen contained therein through a subsequent thermal processing process and to perform hydrogenation on the first semiconductor layer comprising polycrystalline silicon. On the other hand, the oxide layer SIO is used to prevent excessive diffusion of hydrogen from the nitride layer SIN through the subsequent thermal processing into the semiconductor material of the second thin-film transistor T2.

[0108] For example, it is desirable that hydrogen diffuses from the nitride layer SIN into the first semiconductor layer A1 disposed below the nitride layer, wherein the first gate insulating layer GI1 is disposed between the first semiconductor layer A1 and the first intermediate insulating layer ILD1. Therefore, it is preferable to stack the nitride layer SIN on the first gate insulating layer GI1 in a manner close to the first semiconductor layer A1.

[0109] A second semiconductor layer A2, overlapping with the second gate G2, is disposed on the first intermediate insulating layer ILD1. The second semiconductor layer A2 includes the channel region of the second thin-film transistor T2. When the second thin-film transistor T2 is a thin-film transistor for a display element, preferably, the second thin-film transistor T2 can have characteristics suitable for performing display function processing. For example, it is recommended that the second thin-film transistor T2 include oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium zinc oxide (IZO). Oxide semiconductor materials have low cutoff current characteristics, thus the voltage duration of the pixel becomes longer, making oxide semiconductor materials suitable for display devices requiring low-speed driving and low power consumption.

[0110] The second gate G2 is disposed on the second semiconductor layer A2. The second gate G2 constituting the second thin-film transistor T2 may be made of the same material as the first gate G1 constituting the first thin-film transistor T1. The second gate G2 is disposed on a portion of the second thin-film transistor T2.

[0111] A second intermediate insulating layer ILD2 is disposed on the second gate G2. The second intermediate insulating layer ILD2 is stacked to cover the second gate G2. Unlike the first intermediate insulating layer ILD1, the second intermediate insulating layer ILD2 can be formed as a monolayer of an oxide layer SiO including silicon oxide (SiOx).

[0112] Contact holes 50 are formed on the second intermediate insulating layer ILD2, exposing one side and the other side of the first semiconductor layer A1, respectively. The contact holes 50 pass through the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the first intermediate insulating layer ILD1 and the first gate insulating layer GI1, and expose one side and the other side of the first semiconductor layer A1, respectively.

[0113] As described above, the display panel according to the embodiments of the present disclosure is characterized in that two types of thin-film transistors are disposed on a substrate.

[0114] The inventors of this disclosure have discovered that, based on pixels in Figure 3 The placement of the transistor in the structure causes a deviation in the device characteristics of the second thin-film transistor T2.

[0115] As described above, hydrogen diffusion can have a positive effect in the first semiconductor layer A1, which comprises polycrystalline silicon material. However, hydrogen diffusion can have a negative effect on the second thin-film transistor T2, which has properties different from those of the first thin-film transistor T1.

[0116] During the hydrogenation process, a significant amount of hydrogen is present in the stacked nitride layers themselves because the materials used in the fabrication of the nitride layer SIN, which constitutes the first intermediate insulating layer ILD1, contain a large amount of hydrogen. Through a thermal processing step, the hydrogen diffuses into the polycrystalline semiconductor material.

[0117] In subsequent processes, hydrogen generated from the nitride layer SIN escapes through the contact holes 50. The density of the contact holes 50 adjacent to the second thin-film transistor T2 disposed in the first pixel P1 is different from the density of the contact holes 50 adjacent to the second thin-film transistor T2 disposed in the second pixel P2.

[0118] Specifically, the contact hole 50 formed in the first thin-film transistor T1 in the first pixel P1 is located to the left of the second thin-film transistor T2 in the first pixel P1. Furthermore, the contact hole 50 formed in the first thin-film transistor T1 in the second pixel P2 is located to the right of the second thin-film transistor T2 in the first pixel P1. That is, the contact hole 50 is located to the left and right of the second thin-film transistor T2 in the first pixel P1, respectively.

[0119] On the other hand, the contact hole 50 formed in the first thin-film transistor T1 in the second pixel P2 is only located on the left side of the second thin-film transistor T2 in the second pixel P2, and the right side of the second thin-film transistor T2 in the second pixel P2 is adjacent to the non-display area NDA. That is, the contact hole 50 is only located on the left side of the second thin-film transistor T2 in the second pixel P2, and no contact hole 50 is located on the right side because the right side is adjacent to the non-display area NDA.

[0120] In subsequent processes, hydrogen generated from the nitride layer SIN escapes through contact holes 50. There is a difference in the density of contact holes 50 surrounding the second thin-film transistor T2 disposed in the first pixel P1 and the second thin-film transistor T2 disposed in the second pixel P2. As a result, a difference in hydrogen concentration occurs, which affects the second semiconductor layer A2 constituting the second thin-film transistor T2 disposed in the first pixel P1 and the second thin-film transistor T2 disposed in the second pixel P2. Therefore, this difference in hydrogen concentration causes the device characteristics of the second thin-film transistor T2 to vary depending on the pixel location. Figure 3 The position of the arrangement in the structure may be deviated.

[0121] <Implementation Method>

[0122] Figures 4 to 7 It is according to the embodiments of this disclosure. Figure 2 The cross-sectional view taken from line I-I'.

[0123] As described above, in the display panel 110 according to the comparative example, the following problem has been described: due to the difference between the density of the contact holes 50 surrounding the second thin film transistor T2 provided in the first pixel P1 and the density of the contact holes 50 surrounding the second thin film transistor T2 provided in the second pixel P2, a deviation is caused in the device characteristics of the second thin film transistor T2 depending on the position of the pixel.

[0124] In the embodiment described below, by providing additional contact holes in the second region, the difference between the density of contact holes surrounding the second thin-film transistor T2 disposed in the first pixel P1 and the density of contact holes surrounding the second thin-film transistor T2 disposed in the second pixel P2 is eliminated. As a result, the problem of deviation in the device characteristics of the second thin-film transistor T2 caused by the arrangement position of the pixels can be solved.

[0125] first, Figure 4 Implementation methods and Figure 3 The difference in the implementation method is that the second contact hole is located in the second region.

[0126] A first contact hole 150 is formed in the first thin-film transistor T1 to expose one side and the other side of the first semiconductor layer A1, respectively. The first contact hole 150 passes through the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the first intermediate insulating layer ILD1 and the first gate insulating layer GI1, and then exposes one side and the other side of the first semiconductor layer A1, respectively.

[0127] The second contact hole 250 is disposed in the second region. The second contact hole 250 passes through the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the first intermediate insulating layer ILD1, and the first gate insulating layer GI1.

[0128] exist Figure 4 In this embodiment, a contact hole passing through the first intermediate insulating layer ILD1 is also formed in the second region. Therefore, with Figure 3 Unlike the comparison example, the density deviation of the second thin-film transistor T2 surrounding the second pixel P2 arranged in the boundary and the contact hole of the first pixel P1 arranged in the display area DA is eliminated. Therefore, the deviation in device characteristics of the second thin-film transistor of the second pixel P2 disposed in the boundary and the second thin-film transistor of the first pixel P1 disposed in the display area DA can be eliminated.

[0129] Figure 5 yes Figure 4 A cross-sectional view of a display panel on which a passivation layer has already been deposited.

[0130] Reference Figure 4 and Figure 5 The source S1 and drain D1 are formed in the first contact hole 150.

[0131] The source S1 and drain D1 are connected to the first semiconductor layer A1 through the first contact hole 150.

[0132] A passivation layer PAS is disposed on the second intermediate insulating layer ILD2 and is configured to cover the source S1 and drain D1. The passivation layer PAS can fill the second contact hole 250. The passivation layer PAS can be connected to the buffer layer through the second contact hole 250 in the second region NDA.

[0133] Figure 6 It shows a difference Figure 4 The implementation method. Figure 6 Implementation methods and Figure 4 The difference in the implementation is that the aperture barrier layer 200 is disposed in the second region NDA. In the same process, the aperture barrier layer 200 can be made of the same material as the first semiconductor layer A1.

[0134] The second contact hole 250 is located in the second region NDA. The second contact hole 250 passes through the second intermediate insulating layer ILD2, the second gate insulating layer GI2, the first intermediate insulating layer ILD1, and the first gate insulating layer GI1.

[0135] To prevent the second contact hole 250 from damaging the buffer layer BUF, the hole barrier layer 200 can be used as a barrier layer. The buffer layer BUF is used to protect the first thin-film transistor T1 and the second thin-film transistor from the outside. If the second contact hole 250 even penetrates the buffer layer BUF, the first thin-film transistor T1 and the second thin-film transistor T2 may be damaged from the outside.

[0136] Figure 7 It has already been completed. Figure 6 Cross-sectional view of a display panel with PAS passivation layer deposited in the middle.

[0137] Reference Figure 6 and Figure 7 The source electrode S1 and the drain electrode D1 are formed in the first contact hole 150.

[0138] The source S1 and drain D1 are connected to the first semiconductor layer A1 through the first contact hole 150.

[0139] A passivation layer PAS is disposed on the second intermediate insulating layer ILD2 and is configured to cover the source S1 and drain D1. The passivation layer PAS can fill the second contact hole 250. The passivation layer PAS can be connected to the hole barrier layer 200 through the second contact hole 250 in the second region NDA.

[0140] Figure 8 This is a view used to describe the arrangement of the second contact hole 250 according to an embodiment of the present disclosure.

[0141] Figure 8 The pixel P2 shown is located at the boundary between the display area DA and the non-display area NDA.

[0142] Each pixel P2 has a first length X in a first direction DR1 and a second length Y in a second direction DR2 perpendicular to the first direction DR1. The first length X is shorter than the second length Y. Considering the average distance between the second thin-film transistor and the first contact hole 250 within the display area DA, preferably, the second contact hole 250 can be arranged in the second area NDA within a distance shorter than the first length X relative to the boundary between the display area DA and the non-display area NDA.

[0143] As described above, the display panel according to this embodiment includes two or more types of thin-film transistors on the same substrate. Furthermore, the second thin-film transistor device can have consistent characteristics, regardless of the pixel arrangement position.

[0144] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and various changes can be made without departing from the spirit of the present disclosure. Therefore, the embodiments of the present disclosure are not intended to limit the spirit of the present disclosure, but rather to describe it, and the scope of the spirit of the present disclosure is not limited by these embodiments. Thus, the foregoing embodiments are merely exemplary and should not be construed as limiting the present disclosure. The scope of the present disclosure should be interpreted by the claims, and all technical spirit within the scope of the claims should be interpreted as included within the proper scope of the present disclosure.

[0145] Figure Labels

[0146] 100: Display device

[0147] 110: Display panel

[0148] 120: Cover the glass

[0149] Cross-reference to related applications

[0150] This application claims priority to Korean Patent Application No. 10-2021-0190655, filed on December 29, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A display panel, the display panel comprising: A substrate, the substrate being divided into a first region and a second region located outside the first region; A buffer layer is disposed in the first region and the second region and on the substrate; A first thin-film transistor, the first thin-film transistor including a polycrystalline semiconductor layer and a first gate, the polycrystalline semiconductor layer being disposed in the first region and disposed on the buffer layer, and the first gate being disposed on the polycrystalline semiconductor layer; A second thin-film transistor, comprising an oxide semiconductor layer and a second gate, wherein the oxide semiconductor layer is disposed in the first region and on the buffer layer, and the second gate is disposed on the oxide semiconductor layer; A first intermediate insulating layer is disposed in the first region and the second region, and is inserted between the first thin-film transistor and the second thin-film transistor; A first contact hole, the first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; The second contact hole passes through the first intermediate insulating layer in the second region; as well as A passivation layer is disposed in the first region and the second region, and is disposed on the second thin-film transistor, wherein the passivation layer is connected to the buffer layer through the second contact hole.

2. The display panel according to claim 1, wherein, The first thin-film transistor further includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate.

3. The display panel according to claim 2, wherein, The first contact hole and the second contact hole pass through the first gate insulating layer.

4. The display panel according to claim 1, wherein, The second thin-film transistor further includes a second gate insulating layer interposed between the oxide semiconductor layer and the second gate.

5. The display panel according to claim 4, wherein, The first contact hole and the second contact hole pass through the second gate insulating layer.

6. The display panel according to claim 1, further comprising a passivation layer disposed in the first region and the second region and disposed on the second thin-film transistor, wherein, The passivation layer fills the second contact hole.

7. The display panel according to claim 1, wherein, The polycrystalline semiconductor layer is further disposed in the second region.

8. The display panel according to claim 7, further comprising a passivation layer disposed in the first region and the second region and disposed on the second thin-film transistor, wherein, The passivation layer is connected to the polycrystalline semiconductor layer disposed in the second region through the second contact hole.

9. The display panel according to claim 7, wherein, The first thin-film transistor further includes a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first intermediate insulating layer.

10. The display panel according to claim 9, wherein, The first contact hole and the second contact hole pass through the first gate insulating layer.

11. The display panel according to claim 1, in, The first area is a display area with multiple pixels arranged thereon, and The second area is a non-display area.

12. The display panel according to claim 11, in, The plurality of pixels includes a plurality of edge pixels arranged at the boundary between the first region and the second region, and The second contact hole is configured to surround the plurality of edge pixels.

13. The display panel according to claim 11, in, Each pixel has a first length in a first direction and a second length in a second direction perpendicular to the first direction. Wherein, the first length is shorter than the second length, and The second contact hole is disposed in the second region at a distance shorter than the first length from the boundary between the first region and the second region.

14. A display panel, the display panel comprising: A display area with multiple pixels; The non-display area located outside the display area; as well as A buffer layer is disposed in the display area and the non-display area. Each of the plurality of pixels includes: A first thin-film transistor and a second thin-film transistor with different properties from the first thin-film transistor; An intermediate insulating layer is disposed in the display area and the non-display area, and is interposed between the first thin-film transistor and the second thin-film transistor; and The first contact hole passes through the intermediate insulating layer. In this configuration, the second thin-film transistor in the edge pixel located at the boundary between the display area and the non-display area is adjacent to the non-display area. In the non-display area, a second contact hole is disposed adjacent to the second thin-film transistor in the edge pixel, and the second contact hole passes through the intermediate insulating layer. The display panel further includes a passivation layer disposed in the display area and the non-display area and disposed on the second thin-film transistor, wherein the passivation layer is connected to the buffer layer through the second contact hole.

15. The display panel according to claim 14, wherein, The first thin-film transistor includes a polycrystalline semiconductor layer, a first gate, and a first gate insulating layer interposed between the polycrystalline semiconductor layer and the first gate, and the second thin-film transistor includes an oxide semiconductor layer.

16. The display panel according to claim 15, wherein, The intermediate insulating layer includes a nitride layer disposed near the polycrystalline semiconductor layer and an oxide layer disposed near the oxide semiconductor layer.

17. A display device, the display device comprising: The display panel according to any one of claims 1 to 16; Drive circuit; as well as The cover glass that covers the display panel.

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