Interleaved analog-to-digital converter gain calibration

Abstract

An integrated circuit can include a full-scale reference generation circuit that corrects for variations in gain or full-scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit can provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a pre-defined or fixed component and a variable component that can specify a given full-scale correction for the given full-scale. For example, the full-scale reference generation circuit can include a full-scale reference generator replica circuit that outputs a fixed current that corresponds to the fixed component. Further, the full-scale reference generation circuit can include a full-scale reference generator circuit that outputs a first voltage that corresponds to the given full-scale setting based at least in part on the fixed current and a variable current that specifies at least in part the given full-scale correction.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit or system that provides gain or full-scale calibration for at least an analog-to-digital converter (ADC). Notably, this disclosure relates to an integrated circuit or system that determines the setting of the full-scale range for a given set of interleaved ADCs. Background Technology

[0002] An ADC is a widely used circuit component that converts analog signals into a quantized or digital representation. Typically, an integrated circuit can include multiple ADCs.

[0003] One method for achieving analog-to-digital conversion is a time-interleaved ADC. In this type of ADC, multiple ADCs (such as N ADCs, where N is an integer) operate in parallel, with a given ADC sampling the analog signal every Nth cycle of the sampling clock. Therefore, the effective sampling rate can be increased by a factor of N relative to the sampling rate of each individual ADC.

[0004] However, in practice, achieving full resolution at an efficient sampling rate can be challenging with time-interleaved ADCs. It is worth noting that ADCs are often sensitive to mismatches, process variations, voltage and / or temperature variations. For example, these effects may modify or change the gain or full-scale range of a given ADC and / or cause DC offset. Furthermore, different gains or full-scale ranges and / or DC offsets result in differences between the individual ADCs out of N ADCs, which can degrade the overall performance and dynamic range of the time-interleaved ADC.

[0005] Some ADCs attempt to address mismatch errors using digital post-processing. It's worth noting that averaging can be used to sense the mismatch error, and digital multiplication with adjustable coefficients can be used to adjust the ADC's full-scale range. However, this approach may amplify noise.

[0006] Another technique for addressing mismatch errors is to use a shared (or common) full-scale reference for multiple ADCs. However, this approach may not be able to address reference-independent mismatches, such as those in the front-end tracking and holding circuitry of the ADC. Furthermore, using a shared full-scale reference allows noise to couple within or between ADCs in an array. Therefore, it is still necessary to correct for mismatch errors in time-interleaved ADCs. Summary of the Invention

[0007] An embodiment of an integrated circuit is described. This integrated circuit includes: a collection of interleaved ADCs; and a full-scale reference generation circuit including analog circuitry, wherein the analog circuitry generates a full-scale reference voltage for each ADC in the collection of interleaved ADCs.

[0008] Furthermore, the analog circuit may include a full-scale reference generator circuit that generates a full-scale reference voltage for a corresponding ADC in the set of interleaved ADCs, wherein the full-scale reference generator circuit includes an open-loop buffer.

[0009] Furthermore, the full-scale reference generation circuit may include a digital-to-analog converter (DAC) that provides a variable current that at least partially specifies the full-scale reference voltage. Note that the variable current may correspond to full-scale correction of a set of interleaved ADCs.

[0010] In addition, the integrated circuit may include calibration circuitry. Calibration circuitry can determine full-scale correction and can provide feedback to the ensemble of interleaved ADCs via full-scale reference generation circuitry.

[0011] In some embodiments, the full-scale reference voltage corresponds to a variable current and a fixed current. Furthermore, the integrated circuit may include a full-scale reference generator replication circuit that provides a fixed current. Note that the full-scale reference generator replication circuit may be shared or shared by the full-scale reference generator circuit. Alternatively or additionally, the full-scale reference generator replication circuit may include a second open-loop buffer that matches the open-loop buffer in the full-scale reference generator circuit.

[0012] Furthermore, the given full-scale reference voltage of a given interleaved ADC can correspond to the sum of a given variable current and a fixed current.

[0013] Furthermore, the full-scale reference voltage can be bipolar. For example, a given full-scale reference voltage may include a first voltage and a second voltage that jointly specify the given full-scale reference voltage. Note that the first voltage may correspond to a given full-scale correction of a given full-scale range of a given interleaved ADC. In some embodiments, the second voltage is the supply voltage of the integrated circuit.

[0014] Furthermore, the full-scale reference voltage can be generated independently or separately by the full-scale reference generation circuit.

[0015] Another embodiment provides a full-scale reference generation circuit.

[0016] Another embodiment provides a calibration engine used in conjunction with a full-scale reference generation circuit.

[0017] Another embodiment provides an electronic device including an integrated circuit.

[0018] Another embodiment provides a system that includes an array of ADCs and a full-scale reference generation circuit.

[0019] Another embodiment provides a method for generating a full-scale reference voltage. This method includes at least some of the operations performed by an integrated circuit.

[0020] The present invention is provided to illustrate some exemplary embodiments in order to provide a basic understanding of some aspects of the subject matter described herein. Therefore, it will be appreciated that the above features are exemplary and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating an example of a digital calibration engine according to some embodiments of the present disclosure.

[0022] Figure 2 This is a block diagram illustrating an example of a full-scale reference generation circuit according to some embodiments of the present disclosure.

[0023] Figure 3 This is a block diagram illustrating an example of a full-scale reference generator circuit according to some embodiments of the present disclosure.

[0024] Figure 4 This is a block diagram illustrating an example of a full-scale reference generator replication circuit according to some embodiments of the present disclosure.

[0025] Figure 5 This is a flowchart illustrating an example of a method for generating a full-scale reference voltage according to some embodiments of the present disclosure.

[0026] Note that the same reference numerals are used throughout all figures to refer to the corresponding parts. Furthermore, multiple instances of the same part are specified by a common prefix separated from the instance number by a dash. Detailed Implementation

[0027] An integrated circuit is described. This integrated circuit may include a full-scale reference generation circuit that corrects for variations in gain or full-scale range of an array of interleaved ADCs. Notably, the full-scale reference generation circuit can provide a given full-scale or reference setting for a given interleaved ADC, wherein the given full-scale setting corresponds to a predefined or fixed component and a variable component (which at least partially specifies a given full-scale correction for a given full-scale range of the given interleaved ADC). For example, the full-scale reference generation circuit may include a full-scale reference generator replication circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least partially on the fixed current and the variable current, wherein the variable current at least partially specifies the given full-scale correction. Note that the full-scale reference generator replication circuit and the full-scale reference generator circuit may include matched (open-loop) buffers. Furthermore, the first voltage can be a first voltage supplied to a given interleaved ADC, and the full-scale reference generator circuit can also supply a second voltage to the given interleaved ADC, which is positive and can be the supply voltage. The first and second voltages can specify a given full-scale setting for the given interleaved ADC. However, in other unipolar embodiments, the first voltage can be a lower voltage and the second voltage can be a higher voltage, such as 0.4V and 0.9V.

[0028] These circuit techniques can reduce the impact of random transistor mismatch and gradient errors (more generally, process, voltage, and / or temperature variations) on the interleaved ADC array by correcting for variations in gain or full-scale range. Notably, the circuit techniques can improve gain or full-scale voltage matching within the interleaved ADC array. Furthermore, the circuit techniques may not amplify noise. Therefore, the circuit techniques can improve the performance of the interleaved ADC array. One or more of these capabilities can allow embodiments of the interleaved ADC array to be used in a wide variety of systems, electronic devices, and applications.

[0029] In this disclosure, it is noted that "full scale" is sometimes referred to as "gain". Full scale can provide or specify the quantized output level based on the analog input level.

[0030] We now describe circuit techniques and embodiments of an array of interleaved ADCs that address these issues. In some embodiments, a calibration engine can determine the full-scale correction and DC offset of an array of interleaved ADCs (such as SAR ADCs). Notably, the calibration engine can select the quantized output or representation of the input signal from a given interleaved ADC. The calibration engine can then determine or sense an average of the quantized output (such as a moving average of the absolute values ​​of the differential quantized output) and can compare this average with a reference (such as the output of one of the interleaved ADCs, which serves as a reference channel or reference signal level) to determine a given full-scale correction and a given DC offset for a given interleaved ADC. For example, a given full-scale correction can be determined using a minimum mean square adjustment.

[0031] The output from a given interleaved ADC can be corrected for a given DC offset (e.g., the given DC offset can be subtracted from the output). Furthermore, full-scale corrections (such as digital correction coefficients) for the set of interleaved ADCs can be provided to a full-scale reference generation circuit for the set of interleaved ADCs.

[0032] A full-scale reference generation circuit can individually or independently adjust the full-scale reference voltage of each ADC in an interleaved ADC set. For example, a full-scale reference generation circuit may include an analog current directed to the DAC that partially adjusts the full-scale reference voltage. (Therefore, at least a portion of the full-scale reference generation circuit can be implemented in the analog domain.) Notably, the full-scale reference generation circuit can convert a given full-scale correction into a corresponding variable current. This variable current can be combined (e.g., summed) with a fixed current provided by a full-scale reference generator replication circuit (sometimes called an "analog replication feedback circuit") within the full-scale reference generation circuit.

[0033] Then, the full-scale reference generator circuit in the full-scale reference generation circuit can convert the combination of variable and fixed currents into a first voltage (e.g., which can at least partially specify the reference voltage) corresponding to a given full-scale reference voltage of a given interleaved ADC. For example, the combination of variable and fixed currents can be applied to a resistor, such as a matched resistor. Note that while the foregoing discussion illustrates a calibration technique using a combination of variable and fixed currents, a combination of variable and fixed voltages can be used in other embodiments.

[0034] In some embodiments, the full-scale reference generator replication circuit is shared by the set of interleaved ADCs within the full-scale reference generation circuit. It is noteworthy that a fixed component of the full-scale reference voltage for the set of interleaved ADCs can be provided by the shared full-scale reference generator replication circuit. Therefore, the full-scale reference generator replication circuit can distribute a fixed current equally among the full-scale reference generator circuits within the full-scale reference generation circuit. However, the variable component of the full-scale reference voltage can be uniquely generated or provided by the full-scale reference generator circuit, at least in part, based on full-scale correction from the calibration engine. Alternatively, in other embodiments, separate full-scale reference generator replication circuits can provide a fixed current (or a fixed component) to their respective full-scale reference generator circuits.

[0035] Furthermore, the full-scale reference generator replication circuit can use feedback (or may be closed-loop) to improve accuracy. However, because this can slow down the circuit response, in other embodiments, the full-scale reference generator replication circuit may be open-loop. It is noteworthy that at least one of the full-scale reference generator circuits and the full-scale reference generator replication circuit may include matched open-loop buffers, such as open-loop source follower circuits. Note that open-loop buffers can have faster responses and can be more power efficient, but at the cost of more errors. These errors (along with other errors in the full-scale reference generation circuit) can be corrected as part of a calibration (such as digital calibration) performed by a calibration circuit that provides the feedback loop. Additionally, note that using separate buffers in the full-scale reference generator replication circuit and the full-scale reference generator circuit can reduce crosstalk.

[0036] Furthermore, as discussed above, the fixed component (such as a fixed current) can be provided by a replica of the open-loop buffer in the full-scale reference generator replication circuit. It is noteworthy that the full-scale reference generator replication circuit may include the same open-loop buffer as at least one of the full-scale reference generator circuits, which can allow tracking of process, voltage, and / or temperature variations.

[0037] Furthermore, in some embodiments, the full-scale reference voltage can be differential. For example, the capacitor in the DAC of a given interleaved ADC can be switched between a first and a second reference voltage. Therefore, in addition to the first voltage, a given full-scale reference generator circuit can also provide a second voltage, which together specify a given full-scale reference voltage or setting for the given interleaved ADC. In some embodiments, the first voltage can be negative and the second voltage can be positive. For example, the positive voltage can be the supply voltage (such as VDD), which can reduce power consumption, reduce impedance, and / or improve settling time. As discussed above, in some embodiments, the negative voltage can be buffered and is adjustable. However, in other unipolar embodiments, the first voltage is a lower voltage and the second voltage is a higher voltage.

[0038] While the preceding discussion has described calibration techniques for an ensemble of interleaved ADCs, in other embodiments, calibration techniques may be used in conjunction with another type of ADC implementation, such as an ensemble of interleaved pipelined ADCs or an ensemble of interleaved successive approximation ADCs.

[0039] Figure 1 A block diagram illustrating an example of a digital calibration engine 100 according to some embodiments of the present disclosure is presented. This digital calibration engine can receive quantized representations of analog input signals from a set of interleaved ADCs or output DIN_0…DIN_n. Furthermore, the digital calibration engine 100 can output corresponding quantized representations DOUT_0…DOUT_n.

[0040] Furthermore, during operation, the digital calibration engine 100 can determine the full-scale correction and DC offset for the set of interleaved ADCs. Notably, the digital calibration engine 100 can select a quantization representation (e.g., DIN_0) from a given interleaved ADC using a multiplexer (MUX) 110. The averaging circuit 112 in the digital calibration engine 100 can then determine an average of the selected quantization representation (e.g., a moving average as a function of time). The average value can be stored in a gain / offset register 114. The average value can then be compared 116 with a reference voltage provided by a gain / offset reference 118 (which may be common to the set of interleaved ADCs or specific to a particular data channel, such as interleaved ADC 0). For example, the reference voltage can be subtracted from the average value. Using this comparison, the full-scale reference generation circuit can determine a given full-scale correction for a given interleaved ADC, and the offset correction circuit 120 can determine a given DC offset for a given interleaved ADC.

[0041] Next, the determined DC offset can be corrected from the quantization representation of the interleaved ADC. For example, the offset correction circuit can subtract the DC offset from the quantization representation. Furthermore, the full-scale correction or code GCAL_0-GCAL_n determined by the gain correction circuit 122 can be provided to the full-scale reference generation circuit. Note that the full-scale correction can match the full-scale ranges of the interleaved ADC set to each other.

[0042] Figure 2 A block diagram illustrating an example of a full-scale reference generation circuit 200 according to some embodiments of the present disclosure is presented. This full-scale reference generation circuit can individually or independently adjust the full-scale reference voltage of each ADC in a set of interleaved ADCs. For simplicity, Figure 2 The illustration shows the generation of a full-scale reference for a given interleaved ADC (such as interleaved ADC 0).

[0043] During operation, the full-scale reference generation circuit 200 can be generated from the digital calibration engine 100 ( Figure 1 The system receives the full-scale correction GCAL_0. Then, the DAC 210 in the full-scale reference generation circuit 200 can convert the full-scale correction into a variable analog current. Furthermore, the full-scale reference generator replication circuit 212 in the full-scale reference generation circuit 200 can generate a fixed current IFS_0...IFS_n based at least partially on the bandgap reference 214, which can be used to provide a full-scale reference voltage for the interleaved ADC array.

[0044] Next, the full-scale reference generation circuit 200 sums the variable current and the fixed current 216. In addition, the full-scale reference generator circuit 218 in the full-scale reference generation circuit 200 can convert the sum of the variable current and the fixed current into a first voltage corresponding to the full-scale reference voltage of the interleaved ADC 0 (e.g., it can at least partially specify the full-scale reference voltage).

[0045] Note that in some embodiments, the full-scale reference generator replication circuit 212 is shared by the set of interleaved ADCs in the full-scale reference generation circuit 200. It is worth noting that the fixed currents IFS_0…IFS_n for the set of interleaved ADCs can be provided by the shared full-scale reference generator replication circuit. Therefore, the full-scale reference generator replication circuit 212 can distribute the fixed current equally among the full-scale reference generator circuits in the full-scale reference generation circuit 200. However, as previously mentioned, the variable current of the full-scale reference voltage can be at least partially based on the current from the digital calibration engine 100 (…). Figure 1 The full-scale correction GCAL_0---GCAL_n is uniquely generated or provided by the full-scale reference generator circuit.

[0046] Figure 3 A block diagram illustrating an example of a full-scale reference generator circuit 300 according to some embodiments of the present disclosure is presented. It is noteworthy that the full-scale reference generation circuit 300 can apply a sum of a variable current and a fixed current to a resistor 310, such as a matched resistor. A matched open-loop buffer 312 (such as an open-loop source follower) can then provide a first voltage VREF_M to an interleaved ADC, such as an interleaved ADC 0 (which may be separate from the full-scale reference generator circuit 300 and therefore not included therein). As discussed earlier, the open-loop buffer 312 can have a faster response and be more energy-efficient, but at the cost of more errors. These errors (and...) Figure 2 Other errors in the full-scale reference generation circuit 200 can be used as feedback loops provided by the digital calibration circuit 100. Figure 1 It is part of the calibration performed to correct the error.

[0047] In some embodiments, the full-scale reference voltage can be differential. For example, the first voltage can be a negative voltage. Furthermore, the full-scale reference generator circuit 200 ( Figure 2 A second voltage, VREF_P, can be provided, which, in conjunction with the first voltage, jointly specifies the full-scale reference voltage of the interleaved ADC 0. This second voltage can be a positive voltage, such as a supply voltage (e.g., VDD), which can reduce power consumption, reduce impedance, and / or improve settling time. Alternatively, in some embodiments, the positive second voltage can be a variable voltage corresponding to full-scale correction, and the first voltage can be ground. In other unipolar embodiments, the first voltage is a lower voltage and the second voltage is a higher voltage.

[0048] Figure 4 A block diagram illustrating an example of a full-scale reference generator replication circuit 400 according to some embodiments of the present disclosure is presented. This full-scale reference generator replication circuit can use a full-scale reference generator circuit 300 ( Figure 3 A replica (e.g., an exact match) of the open-loop buffer in the circuit can provide a fixed current. This allows for the use of a replica circuit 400 and a full-scale reference generator circuit 300 (e.g., an exact match) to provide a fixed current. Figure 3 Track process, voltage and / or temperature changes.

[0049] It is worth noting that during operation, an instance of the full-scale reference generator circuit 410 in the full-scale reference generator replication circuit 400 can provide a full-scale reference voltage VFS, which is compared by the differential amplifier 412 with a voltage provided by resistor 414 and a current IFS_ref from current source 416 (which provides the master reference). The resulting error can be provided to the voltage-to-current (V to I) circuit 418, which uses it to provide a fixed current IFS_0...IFS_n to the set of interleaved ADCs. For example, the error can be applied to the gate of a current mirror that provides an exact copy of the fixed current to the set of interleaved ADCs. Furthermore, the current mirror in the V to I circuit 418 can provide a copy of the fixed current to the instance of the full-scale reference generator circuit 410.

[0050] In this discussion, interleaved analog-to-digital conversion performed by an array of interleaved ADCs can be applied to a variety of input signals. For example, the input signal may include a frame. This frame may include an image, in which different ADCs in the array of interleaved ADCs receive analog inputs corresponding to different spatial locations or regions. Alternatively, in some embodiments, such as in a scanning system, frames may be captured progressively over time intervals (such as milliseconds). Thus, in these embodiments, the array of interleaved ADCs can receive analog inputs corresponding to different spatial locations or regions captured at different times.

[0051] We will now describe an embodiment of the method. Figure 5 The illustrations are presented for use with circuits such as the full-scale reference generation circuit 200 ( Figure 2 The flowchart illustrates an example of a method 500 for generating a full-scale reference voltage using a full-scale reference generation circuit, such as a full-scale reference generation circuit. During operation, the full-scale reference generation circuit receives a variable current from the DAC that at least partially specifies the full-scale reference voltage (operation 510). Furthermore, the analog circuitry in the full-scale reference generation circuit generates a full-scale reference voltage for each of the interleaved analog-to-digital converters (ADCs) in the set based at least partially on the variable current (operation 512), wherein the variable current corresponds to a full-scale correction of the set of interleaved ADCs.

[0052] In some embodiments of method 500, there may be additional or fewer operations. Moreover, the order of operations may be changed, and / or two or more operations may be combined into a single operation.

[0053] The disclosed ADC and circuit technology can be used in any electronic device (or may be included therein). For example, electronic devices may include: cellular phones or smartphones, tablet computers, laptop computers, notebook computers, personal or desktop computers, netbooks, media player devices, e-book devices, etc. Devices, smartwatches, wearable computing devices, portable computing devices, consumer electronic devices, access points, routers, switches, communication equipment, testing equipment, vehicles, ships, aircraft, automobiles, trucks, buses, motorcycles, manufacturing equipment, agricultural implements, construction equipment, or another type of electronic device.

[0054] While specific components are used to describe embodiments of the full-scale reference generation circuit, the integrated circuit including the full-scale reference generation circuit, and the interleaved ADC, in alternative embodiments, different components and / or subsystems may exist within the calibration engine, the full-scale reference generation circuit, the integrated circuit including the full-scale reference generation circuit, and / or the interleaved ADC. Therefore, embodiments of the calibration engine, the full-scale reference generation circuit, the integrated circuit including the full-scale reference generation circuit, and / or the interleaved ADC may include fewer components, additional components, different components, may combine two or more components into a single component, may divide a single component into two or more components, may change one or more positions of one or more components, and / or may have different types of components.

[0055] Furthermore, the circuitry and components in the embodiments of the calibration engine, full-scale reference generation circuitry, integrated circuitry including the full-scale reference generation circuitry, and / or the collection of interleaved ADCs can be implemented using any combination of analog and / or digital circuitry systems, including bipolar, PMOS, and / or NMOS gates or transistors. Additionally, the signals in these embodiments can include digital signals with substantially discrete values ​​and / or analog signals with continuous values. Furthermore, components and circuitry may be single-ended or differential, and power supplies may be unipolar or bipolar. Note that the electrical couplings or connections in the preceding embodiments can be direct or indirect. In the preceding embodiments, a single line corresponding to a route may indicate one or more single lines or routes.

[0056] As mentioned earlier, an integrated circuit can implement some or all of the functions of circuit technology. This integrated circuit may include hardware and / or software mechanisms for implementing the functions associated with the circuit technology.

[0057] In some embodiments, the output of the process for designing an integrated circuit or a portion thereof (including one or more of the circuits described herein) may be a computer-readable medium, such as, for example, magnetic tape, optical disc, or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing the circuit system, which may be physically instantiated as an integrated circuit or a portion thereof. While various formats may be used for such encoding, these data structures are typically written in formats such as Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork Systems Interchange Standard (OASIS). Those skilled in the art of integrated circuit design can develop such data structures from the schematic diagrams and corresponding descriptions of the types detailed above and encode the data structures on a computer-readable medium. Those skilled in the art of integrated circuit design may use such encoded data to fabricate integrated circuits including one or more of the circuits described herein.

[0058] While some of the operations in the preceding embodiments are implemented in hardware or software, the operations in the preceding embodiments can typically be implemented with various configurations and architectures. Therefore, some or all of the operations in the above embodiments can be performed in hardware, software, or both. For example, at least some of the operations in circuit technology can be implemented using program instructions executed by firmware in a processor or integrated circuit.

[0059] Furthermore, while numerical examples have been provided in the foregoing discussion, different numerical values ​​are used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0060] In the foregoing description, we refer to "some embodiments". Note that "some embodiments" describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0061] The foregoing description is intended to enable any person skilled in the art to make and use this disclosure, and is provided in the context of a particular application and its requirements. Moreover, the foregoing description of embodiments of this disclosure is presented for illustrative and descriptive purposes only. It is not exhaustive or intended to limit this disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure, and the general principles defined herein may be applied to other embodiments and applications. Furthermore, the discussion of the foregoing embodiments is not intended to limit this disclosure. Therefore, this disclosure is not limited to the embodiments shown, but should be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. An integrated circuit, comprising: A collection of interleaved analog-to-digital converters (ADCs); A full-scale reference generation circuit includes analog circuitry, wherein the analog circuitry includes a full-scale reference generator circuit configured to generate a full-scale reference voltage for a corresponding ADC in the set of interleaved ADCs. Wherein, the full-scale reference voltage corresponds to the variable current and the fixed current, and wherein, the variable current corresponds to the full-scale correction of the set of full-scale values ​​of the interleaved ADC; and A full-scale reference generator replication circuit is configured to provide the fixed current, wherein the full-scale reference generator replication circuit is shared or co-located with the full-scale reference generator circuit.

2. The integrated circuit according to claim 1, wherein, The full-scale reference generator circuit includes an open-loop buffer.

3. The integrated circuit according to claim 2, wherein, The full-scale reference generation circuit includes a digital-to-analog converter (DAC) configured to provide a variable current that at least partially specifies the full-scale reference voltage. as well as The variable current corresponds to the full-scale correction of the set of interleaved ADCs.

4. The integrated circuit according to claim 3, wherein, The integrated circuit includes a calibration circuit; and The calibration circuit is configured to determine the full-scale correction and to provide feedback to the set of interleaved ADCs via the full-scale reference generation circuit.

5. The integrated circuit according to claim 1, wherein, The full-scale reference generator replication circuit includes a second open-loop buffer that matches the open-loop buffer in the full-scale reference generator circuit.

6. The integrated circuit according to claim 1, wherein, The given full-scale reference voltage of a given interleaved ADC corresponds to the sum of the given variable current and the fixed current.

7. The integrated circuit according to claim 1, wherein, The full-scale reference voltage is bipolar.

8. The integrated circuit according to claim 7, wherein, The given full-scale reference voltage includes a first voltage and a second voltage that jointly specify the given full-scale reference voltage.

9. The integrated circuit according to claim 8, wherein, The first voltage corresponds to the given full-scale correction of the given full-scale range of the given interleaved ADC.

10. The integrated circuit according to claim 8, wherein, The second voltage is the power supply voltage of the integrated circuit.

11. The integrated circuit according to claim 1, wherein, The full-scale reference voltage is generated independently or separately by the full-scale reference generation circuit.

12. A system comprising: A collection of interleaved analog-to-digital converters (ADCs); as well as A full-scale reference generation circuit includes analog circuitry, wherein the analog circuitry includes a full-scale reference generator circuit configured to generate a full-scale reference voltage for a corresponding ADC in the set of interleaved ADCs. Wherein, the full-scale reference voltage corresponds to the variable current and the fixed current, and wherein, the variable current corresponds to the full-scale correction of the set of full-scale values ​​of the interleaved ADC; and A full-scale reference generator replication circuit is configured to provide the fixed current, wherein the full-scale reference generator replication circuit is shared or co-located with the full-scale reference generator circuit.

13. The system according to claim 12, wherein, The full-scale reference generation circuit includes a digital-to-analog converter (DAC) configured to provide the variable current.

14. The system according to claim 13, wherein, The system includes a calibration circuit; and The calibration circuit is configured to determine the full-scale correction and to provide feedback to the set of interleaved ADCs via the full-scale reference generation circuit.

15. The system according to claim 12, wherein, The full-scale reference generator replication circuit includes a second open-loop buffer that matches the open-loop buffer in the full-scale reference generator circuit.

16. The system according to claim 12, wherein, The given full-scale reference voltage of a given interleaved ADC corresponds to the sum of the given variable current and the fixed current.

17. A method for generating a full-scale reference voltage, comprising: The full-scale reference generation circuit includes analog circuitry: Receive a variable current that partially specifies the full-scale reference voltage from the digital-to-analog converter (DAC); The full-scale reference generator replication circuit receives a fixed current that partially specifies the full-scale reference voltage; as well as Using the analog circuitry and based at least in part on the fixed current and the variable current, a full-scale reference voltage for the full scale of each ADC in the set of interleaved analog-to-digital converters (ADCs) is generated, wherein the variable current corresponds to the full-scale correction of the full scale of the set of interleaved ADCs. The analog circuitry includes a full-scale reference generator circuit configured such that a corresponding ADC in the set of interleaved ADCs generates the full-scale reference voltage. The full-scale reference generator replication circuit is shared or used by the full-scale reference generator circuit.

18. The method according to claim 17, wherein, The full-scale reference generator circuit includes an open-loop buffer.

19. The method of claim 17, wherein, The full-scale reference generator replication circuit includes a second open-loop buffer that matches the open-loop buffer in the full-scale reference generator circuit.

20. The method of claim 17, wherein, The given full-scale reference voltage of a given interleaved ADC corresponds to the sum of the given variable current and the fixed current.

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