Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer. The first nitride layer is on the substrate. The polarity inversion layer is on a surface of the first nitride layer to convert a non-metallic polar surface of the first nitride layer to a metallic polar surface of the polarity inversion layer. The second nitride layer is on the polarity inversion layer. The third nitride layer is on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer contain an iron element. The semiconductor structure of the present invention suppresses efficacy with parasitic channel generation.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure containing iron. Background Technology

[0002] Gallium nitride (GaN) devices have the advantages of high frequency and high power.

[0003] In high-frequency power device applications, the silicon substrate used in gallium nitride (GaN on Si) has relatively high resistivity. Therefore, the formation of parasitic channels in the silicon substrate can easily lead to insertion loss in the high-frequency characteristics of the device. To suppress this insertion loss, silicon nitride layers or deep-level dopant are typically used. However, the presence of a silicon nitride layer can prevent the growth of a flat GaN epitaxial layer. Furthermore, excessive deep-level dopant can cause surface roughness in the GaN epitaxial layer, thereby compromising its epitaxial quality. Summary of the Invention

[0004] This invention provides a semiconductor structure that can suppress the generation of parasitic channels.

[0005] This invention provides a semiconductor structure including a substrate, a first nitride layer, a polarity reversal layer, a second nitride layer, and a third nitride layer. The first nitride layer is located on the substrate. The polarity reversal layer is located on the surface of the first nitride layer to convert the non-metallic polar surface of the first nitride layer into the metallic polar surface of the polarity reversal layer. The second nitride layer is located on the polarity reversal layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity reversal layer, and the second nitride layer all contain iron.

[0006] In one embodiment of the present invention, the third nitride layer comprises iron.

[0007] In one embodiment of the present invention, the substrate includes a lower substrate and an upper substrate between the lower substrate and the first nitride layer, wherein the thickness of the upper substrate is 25 micrometers to 200 micrometers.

[0008] In one embodiment of the present invention, the oxygen concentration in the upper substrate is lower than the oxygen concentration in the lower substrate.

[0009] In one embodiment of the present invention, the resistivity of the upper substrate is higher than that of the lower substrate.

[0010] In one embodiment of the present invention, the iron concentration in the upper substrate is higher than the iron concentration in the lower substrate.

[0011] In one embodiment of the present invention, in the aforementioned upper substrate, the aluminum concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is less than 1E17 atoms / cm². 3 .

[0012] In one embodiment of the present invention, in the aforementioned upper substrate, the iron concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is greater than 1E14 atoms / cm². 3 .

[0013] In one embodiment of the present invention, the first nitride layer comprises iron-containing aluminum silicon nitride, and the iron concentration in the first nitride layer is greater than 5E16 atoms / cm³. 3 .

[0014] In one embodiment of the present invention, the polarity reversal layer comprises an iron-containing metal layer, and the iron concentration in the polarity reversal layer is greater than 5E17 atoms / cm³. 3 .

[0015] In one embodiment of the present invention, the second nitride layer comprises aluminum nitride containing iron, and the iron concentration in the second nitride layer is greater than 5E17 atoms / cm³. 3 .

[0016] In one embodiment of the present invention, the second nitride layer comprises a low-temperature aluminum nitride layer and a high-temperature aluminum nitride layer located on the low-temperature aluminum nitride layer, wherein the temperature difference between the growth temperature of the high-temperature aluminum nitride layer and the growth temperature of the low-temperature aluminum nitride layer is greater than 50°C.

[0017] In one embodiment of the present invention, the carrier concentration within the surface of the substrate is 1E15 atoms / cm². 3 the following.

[0018] This invention provides a semiconductor structure including a substrate, a first nitride layer, a metal layer, a second nitride layer, and a third nitride layer. The first nitride layer is located on the substrate. The substrate includes a lower substrate and an upper substrate between the lower substrate and the first nitride layer. In the upper substrate, the aluminum concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is less than 1E17 atoms / cm³. 3 The iron concentration within 2 micrometers below the interface between the upper substrate and the first nitride layer is greater than 1E14 atoms / cm³. 3 A metal layer is located on the surface of the first nitride layer to convert the non-metallic polar surface of the first nitride layer into the metallic polar surface of the metal layer. A second nitride layer is located on the metal layer. A third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the metal layer, and the second nitride layer all contain iron.

[0019] Based on the above, the substrate, the first nitride layer, the polarity reversal layer and the second nitride layer in the semiconductor structure of the present invention contain iron elements. Therefore, iron elements can generate deep energy level doping in the above structure and suppress the generation of parasitic channels. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0021] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0022] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 4 It is a curve showing the carrier concentration and depth of substrates with different structures;

[0024] Figure 5 This is a cross-sectional schematic diagram of a semiconductor structure according to a comparative example of the present invention.

[0025] Explanation of reference numerals in the attached figures

[0026] 100:Substrate;

[0027] 102: First nitride layer;

[0028] 104: Polarity Reversal Layer;

[0029] 106: Second nitride layer;

[0030] 108: Third nitride layer;

[0031] 110: First aluminum nitride layer;

[0032] 112: Second aluminum nitride layer;

[0033] 114: Al gallium nitride layer;

[0034] 116: Gallium nitride layer;

[0035] S1: Lower substrate;

[0036] S2: Upper substrate. Detailed Implementation

[0037] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 1The semiconductor structure of this embodiment includes a substrate 100, a first nitride layer 102, a polarity reversal layer 104, a second nitride layer 106, and a third nitride layer 108.

[0039] The substrate 100 is, for example, a silicon substrate. In this embodiment, the substrate 100 includes a lower substrate S1 and an upper substrate S2 between the lower substrate S1 and the first nitride layer 102. The thickness of the upper substrate S2 is 25 micrometers to 200 micrometers, preferably 25 micrometers to 100 micrometers, and more preferably 45 micrometers to 55 micrometers. In this embodiment, the lower substrate S1 and the upper substrate S2 have different characteristics. For example, the lower substrate S1 has a greater flexural strength than the upper substrate S2, the oxygen concentration in the upper substrate S2 is lower than the oxygen concentration in the lower substrate S1, and the resistivity of the upper substrate S2 is higher than that of the lower substrate S1. In some embodiments, the flexural strength of the lower substrate S1 is 20 Newtons to 200 Newtons, thereby preventing the substrate 100 from deforming during the process. In some embodiments, the oxygen concentration of the upper substrate S2 is less than 5 ppma, and the resistivity of the upper substrate S2 is greater than 1,000 ohm-cm.

[0040] In some embodiments, an upper substrate S2 and a lower substrate S1 are formed using different processes, and then the upper substrate S2 and the lower substrate S1 are bonded or laminated together. In some embodiments, the method for forming the upper substrate S2 includes, for example, magnetic field applied Czochralski (MCZ), floating zone (FZ), or other methods, while the method for forming the lower substrate S1 includes, for example, Czochralski (CZ), or other methods. By combining the lower substrate S1 and the upper substrate S2, which have different properties, the production cost of the semiconductor structure can be reduced while maintaining the strength of the semiconductor structure and the yield of subsequent thin-film processes.

[0041] In other embodiments, a lower substrate S1 is first formed, and then an upper substrate S2 is formed on the lower substrate S1 using a thin film deposition process. For example, the upper substrate S2 is formed on the lower substrate S1 using a chemical vapor deposition process.

[0042] In this embodiment, iron is present in the substrate 100 due to an unintentional method. In some embodiments, iron is present in the upper substrate S2 and selectively present in the lower substrate S1. The iron concentration in the upper substrate S2 is higher than the iron concentration in the lower substrate S1, wherein the lower substrate S1 selectively contains or does not contain iron. In some embodiments, in the upper substrate S2, the iron concentration within 2 micrometers below the interface between the upper substrate S2 and the first nitride layer 102 is greater than 1E14 atoms / cm².3 For example, greater than 1E14 atoms / cm 3 And less than 1E19 atoms / cm 3 Greater than 1E14 atoms / cm 3 And less than 1E18 atoms / cm 3 Or greater than 1E14 atoms / cm 3 And less than 1E17 atoms / cm 3 When the iron concentration within 2 micrometers below the interface between the upper substrate S2 and the first nitride layer 102 is less than 1E14 atoms / cm². 3 When the iron concentration in substrate 100 is greater than 1E19 atoms / cm³, the iron concentration within 2 micrometers below the interface between the upper substrate S2 and the first nitride layer 102 will not be sufficient to suppress parasitic channels. 3 This will result in a rough GaN epitaxial surface and compromise the quality of subsequent epitaxial growth.

[0043] In some embodiments, aluminum is incorporated into the substrate 100 through unintentional means. In some embodiments, the aluminum concentration in the upper substrate S2 is less than 1E17 atoms / cm³ within a depth of 2 micrometers below the interface between the upper substrate S2 and the first nitride layer 102. 3 For example, less than 1E17 atoms / cm 3 And greater than 1E13 atoms / cm 3 Less than 1E16 atoms / cm 3 And greater than 1E13 atoms / cm 3 The aluminum concentration within 2 micrometers below the interface between the upper substrate S2 and the first nitride layer 102 is greater than 1E17 atoms / cm³. 3 When this occurs, parasitic channels will form; therefore, the lower the aluminum concentration in the substrate 100, the better. In some embodiments, the carrier concentration within the surface of the substrate 100 is 1E15 atoms / cm². 3 the following.

[0044] The first nitride layer 102 is located on the substrate 100. For example, the first nitride layer 102 is formed directly on the substrate 100. The thickness of the first nitride layer 102 is between 0.1 nm and 5 nm, preferably between 0.1 nm and 3 nm.

[0045] In this embodiment, the first nitride layer 102 contains iron. For example, the first nitride layer 102 comprises iron-containing aluminum silicon nitride. The iron concentration in the first nitride layer is greater than 5E16 atoms / cm³. 3 For example, greater than 5E16 atoms / cm 3 And less than 1E19 atoms / cm 3 Greater than 5E16 atoms / cm 3And less than 1E18 atoms / cm 3 Or greater than 5E16 atoms / cm 3 And less than 1E17 atoms / cm 3 In some embodiments, the first nitride layer 102 is formed by generating silicon nitride on the substrate 100, and then aluminum and iron elements from the polarity reversal layer 104 and the second nitride layer 106 diffuse into the aforementioned silicon nitride to form aluminum silicon nitride containing iron, i.e., the first nitride layer 102.

[0046] Please continue to refer to Figure 1 The polarity reversal layer 104 is located on the surface of the first nitride layer 102. For example, the polarity reversal layer 104 is formed directly on the surface of the first nitride layer 102, converting the non-metallic polar surface of the first nitride layer 102 into a metallic polar surface of the polarity reversal layer 104. In some embodiments, the thickness of the polarity reversal layer 104 is less than 1 nm, preferably less than 0.8 nm, such as 0.7 nm, 0.6 nm, 0.5 nm, 0.4 nm, etc. In some embodiments, the metal element in the polarity reversal layer 104 diffuses into the first nitride layer 102, converting the non-metallic polar surface of the first nitride layer 102 into a metallic polar surface, thereby improving the surface smoothness of the subsequently grown nitride layer.

[0047] In some embodiments, the polarity reversal layer 104 is a metal layer. For example, a method of forming the polarity reversal layer 104 includes directly depositing a metal material onto the surface of the first nitride layer 102. In some embodiments, the polarity reversal layer 104 comprises an iron-containing metal layer. For example, the polarity reversal layer 104 comprises iron and other metal elements such as aluminum, indium, and gallium. In some embodiments, the iron concentration in the polarity reversal layer 104 is greater than 5E17 atoms / cm³. 3 For example, greater than 5E17 atoms / cm 3 And less than 1E19 atoms / cm 3 In this embodiment, the iron element in the polarity reversal layer 104 will diffuse into other film layers, such as into the substrate 100, during the deposition of the polarity reversal layer 104 or in the subsequent heat treatment process, to generate deep energy level doping and suppress the generation of parasitic channels.

[0048] In some embodiments, iron in the polarity reversal layer 104 diffuses into the first nitride layer 102 and the substrate 100. In other words, before the polarity reversal layer 104 is deposited, the first nitride layer 102 and the substrate 100 do not contain iron; however, this is not a limitation of the invention. In other embodiments, the first nitride layer 102 and the substrate 100 contain iron before the polarity reversal layer 104 is formed. For example, the first nitride layer 102 containing iron is directly deposited on the substrate 100.

[0049] Please continue to refer to Figure 1 The second nitride layer 106 is located on the polarity reversal layer 104, and the third nitride layer 108 is located on the second nitride layer 106. In one embodiment, the second nitride layer 106 may be a single layer or multiple layers of aluminum nitride. In one embodiment, the thickness of the second nitride layer 106 is less than 100 nm, preferably less than 50 nm, for example less than 25 nm.

[0050] In this embodiment, the second nitride layer 106 contains iron. For example, the second nitride layer 106 comprises iron-containing aluminum nitride, and the iron concentration in the second nitride layer 106 is greater than 5E17 atoms / cm³. 3 For example, greater than 5E17 atoms / cm 3 And less than 1E19 atoms / cm 3 Greater than 8E17 atoms / cm 3 And less than 1E19 atoms / cm 3 Or greater than 1E18 atoms / cm 3 And less than 1E19 atoms / cm 3 In some embodiments, the iron in the second nitride layer 106 is derived from the polarity reversal layer 104; however, the invention is not limited thereto. In other embodiments, the second nitride layer 106 containing iron is deposited directly on the polarity reversal layer 104.

[0051] The third nitride layer 108 comprises a multilayer structure, and the thickness of the third nitride layer 108 is, for example, between 0.1 μm and 10 μm, preferably between 1 μm and 8 μm. In this embodiment, the third nitride layer 108 comprises all combinations of aluminum gallium nitride and aluminum nitride and gallium nitride. For example, Figure 1 The third nitride layer 108 is a combination of an aluminum gallium nitride layer 114 and a gallium nitride layer 116, wherein the gallium concentration of the aluminum gallium nitride layer 114 can be increased stepwise or continuously from the second nitride layer 106 to the gallium nitride layer 116. However, the present invention is not limited thereto. In other embodiments, the third nitride layer of the present invention may also include a superlattice structure, a graded layer structure, an intercalation layer structure, or a combination of the foregoing structures.

[0052] In some embodiments, the third nitride layer 108 may selectively contain iron.

[0053] In this embodiment, the substrate 100, the first nitride layer 102, the polarity reversal layer 104, the second nitride layer 106, and the third nitride layer 108 contain continuous or discontinuous iron element distributions. Specifically, "continuous iron element distribution" can mean that the entire film layer is a doped region with the same iron element concentration, or it can mean that the film layer includes doped regions with different iron element concentrations connected together, wherein the aforementioned doped regions with different iron element concentrations can be iron element doped regions with gradually changing or non-gradually changing concentrations. On the other hand, "discontinuous iron element distribution" means that the film layer contains regions without iron and regions with iron.

[0054] Figure 2 This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It should be noted that... Figure 2 The embodiments follow Figure 1 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0055] Figure 2 semiconductor structure and Figure 1 The difference in semiconductor structure lies in: Figure 2 In the semiconductor structure, the second nitride layer 106 is a double-layer structure and includes a first aluminum nitride layer 110 and a second aluminum nitride layer 112.

[0056] Please refer to Figure 2 The first aluminum nitride layer 110 is located on the polarity reversal layer 104, and the second aluminum nitride layer 112 is located between the first aluminum nitride layer 110 and the third nitride layer 108. In this embodiment, from the viewpoint of suppressing insertion loss and interface carrier concentration, the first aluminum nitride layer 110 is preferably a low-temperature aluminum nitride (LT AlN) layer, and the second aluminum nitride layer 112 is preferably a high-temperature aluminum nitride (HT AlN) layer, wherein the temperature difference between the growth temperature of the high-temperature aluminum nitride layer and the growth temperature of the low-temperature aluminum nitride layer is approximately greater than 50°C, and more preferably greater than 100°C. Furthermore, in this embodiment, using a low-temperature aluminum nitride layer can further suppress the formation of parasitic channels.

[0057] In this embodiment, the thickness of the low-temperature aluminum nitride layer is preferably less than that of the high-temperature aluminum nitride layer, wherein the thickness of the low-temperature aluminum nitride layer is, for example, between 1 nm and 50 nm, and more preferably between 5 nm and 25 nm; the thickness of the high-temperature aluminum nitride layer is, for example, between 1 nm and 50 nm, and more preferably between 10 nm and 35 nm.

[0058] In this embodiment, the first aluminum nitride layer 110 and the second aluminum nitride layer 112 contain continuous or discontinuous iron element distributions.

[0059] Figure 3 This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It should be noted that... Figure 3 The embodiments follow Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0060] Figure 3 semiconductor structure and Figure 2 The difference in semiconductor structure lies in: Figure 3 In the semiconductor structure, the second aluminum nitride layer 112 and the third nitride layer 108 do not contain iron.

[0061] Please refer to Figure 3 In some embodiments, the first aluminum nitride layer 110 is a low-temperature aluminum nitride layer, and the second aluminum nitride layer 112 is a high-temperature aluminum nitride layer, wherein the low-temperature aluminum nitride layer contains iron, and the high-temperature aluminum nitride layer does not contain iron, but the present invention is not limited thereto. In other embodiments, the first aluminum nitride layer 110 and the second aluminum nitride layer 112 are formed at the same process temperature (e.g., both are high-temperature aluminum nitride layers), wherein the first aluminum nitride layer 110 contains iron, and the second aluminum nitride layer 112 does not contain iron.

[0062] Figure 4 It is a graph showing the carrier concentration versus depth based on substrate structures of different types. Figure 4 In the diagram, the vertical axis represents the substrate carrier concentration, while the horizontal axis represents the depth.

[0063] Figure 4 The graph shows the carrier concentration versus depth of substrates with three different semiconductor structures. Figure 4 In this document, Structure 1 and Structure 2 are used to compare the effects of embodiments of Structure 3; however, this does not mean that the invention is limited to embodiments of Structure 3.

[0064] Structure 1 as follows Figure 2 As shown, from bottom to top, it includes a substrate 100 (silicon substrate), a first nitride layer 102 (aluminum nitride silicon), a polarity reversal layer 104, a second nitride layer 106 (containing low-temperature aluminum nitride and high-temperature aluminum nitride), and a third nitride layer 108. However, as previously mentioned... Figure 2 The difference in the description is that, in structure 1, the substrate 100, the first nitride layer 102, the polarity reversal layer 104, the second nitride layer 106, and the third nitride layer 108 do not contain iron. Figure 4It can be seen that in structure 1, the carrier concentration at the surface of the substrate (depth 0) is 2.5E14 atoms / cm². 3 .

[0065] Structure 2 as Figure 5 As shown, from bottom to top, the structure includes a substrate 100 (silicon substrate), a second nitride layer 106 (containing low-temperature aluminum nitride and high-temperature aluminum nitride), and a third nitride layer 108. The difference between structure 2 and structure 1 is that structure 2 does not have a first nitride layer 102 and a polarity reversal layer 104, and the silicon substrate and the second nitride layer 106 in structure 2 contain iron. Figure 4 It can be seen that in structure 2, the carrier concentration at the surface of the substrate (depth 0) is 4.4E14 atoms / cm². 3 .

[0066] Structure 3 remains the same Figure 2 As shown, from bottom to top, the structure includes a substrate 100 (silicon substrate), a first nitride layer 102 (aluminum silicon nitride), a polarity reversal layer 104, a second nitride layer 106 (containing low-temperature aluminum nitride and high-temperature aluminum nitride), and a third nitride layer 108. The difference between structure 3 and structure 1 is that the substrate 100, the first nitride layer 102, the polarity reversal layer 104, and the second nitride layer 106 in structure 3 contain iron.

[0067] Depend on Figure 4 It can be seen that in structure 3, in addition to using silicon aluminum nitride to block the diffusion of aluminum to the silicon substrate, deep-level doping by iron can also be used to reduce the carrier concentration. Therefore, the carrier concentration on the surface of the silicon substrate in structure 3 is lower than that in structures 2 and 1, thereby suppressing the generation of parasitic channels. In structure 3, the carrier concentration on the surface of the substrate is 1E15 atoms / cm². 3 Specifically, in structure 3, the carrier concentration at the surface of the substrate (depth 0) is 7.6E13 atoms / cm². 3 The carrier concentration is lower than that of Structure 1 and Structure 2 at the surface of the substrate.

[0068] In summary, in the semiconductor structure of the present invention, the substrate, the first nitride layer, the polarity reversal layer, and the second nitride layer contain continuous or discontinuous iron element distributions. Therefore, the generation of parasitic channels can be suppressed through the iron element. Furthermore, the second nitride layer, composed of a low-temperature aluminum nitride layer and a high-temperature aluminum nitride layer, can suppress the interface carrier concentration and reduce insertion loss. The semiconductor structure of the present invention can be used in the field of semiconductor epitaxy, and the gallium nitride on silicon (GaN on Si) fabricated by the present invention can be applied to radio frequency (RF) devices.

[0069] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor structure, comprising: substrate; A first nitride layer is located on the substrate; A polarity reversal layer is located on the surface of the first nitride layer to convert the non-metallic polar surface of the first nitride layer into the metallic polar surface of the polarity reversal layer. The second nitride layer is located on the polarity reversal layer; as well as A third nitride layer is located on the second nitride layer, wherein the substrate, the first nitride layer, the polarity reversal layer, and the second nitride layer contain iron, wherein the second nitride layer comprises iron-containing aluminum nitride, and the iron concentration in the second nitride layer is greater than 5E17 atoms / cm³. 3 .

2. The semiconductor structure according to claim 1, wherein the third nitride layer comprises iron.

3. The semiconductor structure according to claim 1, wherein the substrate comprises: A lower substrate and an upper substrate between the lower substrate and the first nitride layer, wherein the thickness of the upper substrate is 25 micrometers to 200 micrometers.

4. The semiconductor structure according to claim 3, wherein the oxygen concentration in the upper substrate is lower than the oxygen concentration in the lower substrate.

5. The semiconductor structure according to claim 3, wherein the resistivity of the upper substrate is higher than that of the lower substrate.

6. The semiconductor structure according to claim 3, wherein the iron concentration in the upper substrate is higher than the iron concentration in the lower substrate.

7. The semiconductor structure according to claim 3, wherein in the upper substrate, the aluminum concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is less than 1E17 atoms / cm². 3 .

8. The semiconductor structure according to claim 3, wherein in the upper substrate, the iron concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is greater than 1E14 atoms / cm². 3 .

9. The semiconductor structure according to claim 1, wherein the first nitride layer forms an interface with the substrate, the first nitride layer comprises iron-containing aluminum silicon nitride, and the iron concentration in the first nitride layer is greater than 5E16 atoms / cm³. 3 .

10. The semiconductor structure according to claim 1, wherein the second nitride layer comprises a low-temperature aluminum nitride layer and a high-temperature aluminum nitride layer located on the low-temperature aluminum nitride layer, wherein the temperature difference between the growth temperature of the high-temperature aluminum nitride layer and the growth temperature of the low-temperature aluminum nitride layer is greater than 50°C.

11. The semiconductor structure according to claim 10, wherein the low-temperature aluminum nitride layer contains iron, and the high-temperature aluminum nitride layer does not contain iron.

12. The semiconductor structure according to claim 1, wherein the carrier concentration within the surface of the substrate is 1E15 atoms / cm². 3 the following.

13. A semiconductor structure comprising: substrate; A first nitride layer is located on the substrate, wherein the substrate includes a lower substrate and an upper substrate between the lower substrate and the first nitride layer, wherein in the upper substrate, the aluminum concentration within a depth of 2 micrometers below the interface between the upper substrate and the first nitride layer is less than 1E17 atoms / cm³. 3 The iron concentration within 2 micrometers below the interface between the upper substrate and the first nitride layer is greater than 1E14 atoms / cm³. 3 ; A metal layer is located on the surface of the first nitride layer to convert the non-metallic polar surface of the first nitride layer into the metallic polar surface of the metal layer. A second nitride layer is located on the metal layer; as well as A third nitride layer is located on the second nitride layer, wherein the substrate, the first nitride layer, the metal layer, and the second nitride layer contain iron, wherein the second nitride layer comprises iron-containing aluminum nitride, and the iron concentration in the second nitride layer is greater than 5E17 atoms / cm³. 3 .

14. A semiconductor structure comprising: substrate; A first nitride layer is located on the substrate; A polarity reversal layer is located on the surface of the first nitride layer to convert the non-metallic polar surface of the first nitride layer into the metallic polar surface of the polarity reversal layer. The second nitride layer is located on the polarity reversal layer; as well as A third nitride layer is located on the second nitride layer, wherein the substrate, the first nitride layer, the polarity reversal layer, and the second nitride layer contain iron, wherein the polarity reversal layer comprises an iron-containing metal layer, and the iron concentration in the polarity reversal layer is greater than 5E17 atoms / cm³. 3 .

Images