An advanced process node HEMT device noise parameter prediction method

Abstract

The application discloses a kind of advanced process node HEMT device noise parameter prediction method, by establishing the relationship between 90nm process node and 70nm process node HEMT device noise model parameter;And by measured 90nm process node HEMT device noise parameter, 70nm process node HEMT device noise parameter can be predicted to obtain.The application creatively constructs large size and small size HEMT device model parameter scaling relationship, facilitates the same process condition different physical size device model parameter of technical personnel in the art to be quickly obtained, the noise characteristic of prediction device, shortens modeling time.

Description

Technical Field

[0001] This invention relates to the field of noise prediction technology for HEMT devices, and more specifically to a method for predicting noise parameters of HEMT devices at advanced process nodes. Background Technology

[0002] Compared to GaAs HEMT devices, InP HEMT devices have become one of the main semiconductor devices used in low-noise applications of terahertz monolithic integrated circuits due to their advantages such as high gain, high cutoff frequency, high current density, low optimal noise factor, and low source resistance. Unlike hybrid integrated circuits, monolithic integrated circuits cannot be adjusted once fabricated. Typically, under the same process conditions, the noise characteristics of multiple HEMT devices with different physical sizes still require building noise models for each device and extracting corresponding model parameters, which increases modeling time and prolongs the engineering schedule. Summary of the Invention

[0003] The purpose of this invention is to provide a method for predicting noise parameters of advanced process node HEMT devices in order to address the shortcomings of existing technologies. This method constructs a proportional scaling relationship between the model parameters of large-size and small-size HEMT devices, which can quickly obtain the model parameters of devices with different physical sizes under the same process conditions. This method can effectively predict the noise characteristics of the devices and shorten the modeling time.

[0004] The specific technical solution for achieving the objective of this invention is as follows:

[0005] A method for predicting noise parameters of advanced process node HEMT devices includes the following steps:

[0006] S1. Construct the PRC noise equivalent circuit model of HEMT devices at 90nm and 70nm process nodes, and derive the expressions for the gate-induced noise factor R and the drain-channel noise factor P.

[0007] P = g m [R n -(R g +R s )];

[0008]

[0009] in,

[0010]

[0011] Among them, R n For noise resistance, R g Gate parasitic resistance, R s For source parasitic resistance, g mFor transconductance, C gs For gate-source intrinsic capacitance, C gd Gate-drain intrinsic capacitance, Bo pt For optimal source susceptance, For optimal source conductance, ω is the angular frequency, and h1 and h2 represent simplification factor 1 and simplification factor 2, respectively.

[0012] S2. Establish a proportional scaling relationship between the noise model parameters of HEMT devices at the 90nm process node and the 70nm process node.

[0013]

[0014]

[0015] Among them, P 70 P represents the drain-channel noise factor of a 70nm HEMT device. 90 R represents the drain-channel noise factor of a 90nm process node HEMT device. 70 R represents the gate-induced noise factor of a 70nm process node HEMT device. 90 This refers to the gate-induced noise factor of a 90nm process node HEMT device. This refers to the gate current of a 70nm process node HEMT device. Transconductance for 70nm process node HEMT devices This refers to the gate current of a 90nm process node HEMT device. Transconductance for HEMT devices at the 90nm process node;

[0016] S3. Test the noise parameters of the 90nm process node HEMT device, and predict the noise parameters of the 70nm process node HEMT device based on the relationship between the noise model parameters.

[0017] The PRC noise equivalent circuit model includes a parasitic network and an intrinsic network, wherein the parasitic network includes a gate parasitic resistance R. g Drain parasitic resistance R d and source parasitic resistance R s The intrinsic network includes the gate-source intrinsic capacitance C. gs Gate-drain intrinsic capacitance C gd Drain-source intrinsic capacitance C ds Intrinsic channel resistance R gs transconductance g m Drain output resistance R ds The time delay τ and intrinsic noise sources, including gate-induced noise sources. and drain channel noise source Wherein, the gate parasitic resistance R g Gate-drain intrinsic capacitance C gd and drain parasitic resistance R d It is connected in series between the gate terminal G and the drain terminal D;

[0018] The gate-induced noise source With source parasitic resistance R s The intrinsic capacitance C connected in series between the gate and drain gd and gate parasitic resistance R g Between the node and the grounding terminal;

[0019] The gate-source intrinsic capacitance C gs and intrinsic channel resistance R gs The intrinsic capacitance C connected in series between the gate and drain gd and gate parasitic resistance R g The node and the source parasitic resistance R s and the gate-induced noise source between;

[0020] The transconductance g m Time delay τ, drain output resistance R ds Drain-source intrinsic capacitance C ds and drain channel noise sources The intrinsic gate-drain capacitance C is connected in parallel. gd and drain parasitic resistance R d The node and the source parasitic resistance R s and the gate-induced noise source between.

[0021] The expression for the PRC noise equivalent circuit model is as follows:

[0022]

[0023]

[0024] The gate-induced noise and drain channel noise Correlation noise between Represented as:

[0025]

[0026] Where Δf is the noise bandwidth, k is the Boltzmann constant, which is 1.38×10-23J / K, T is the absolute temperature, which is set to 290K, and C is the relevant noise factor.

[0027] The expressions for the gate-induced noise factor R and the drain-channel noise factor P are derived from the equivalent circuit model two-port noise network matrix. The correlation matrix of the equivalent circuit model two-port noise network is obtained by the following steps:

[0028] S1-1: The correlation matrix C of the two-port admittance noise network is derived from the intrinsic network of the circuit based on the device noise model. Y expression:

[0029]

[0030] j represents the imaginary part;

[0031] S1-2: The admittance noise correlation matrix C Y Convert to ABCD noise correlation matrix C A The transformation relationship between the noise correlation matrices is as follows:

[0032]

[0033]

[0034] C A21 =(C A12 ) *

[0035]

[0036] Where * denotes the conjugate of the matrix;

[0037] S1-3: Consider the gate parasitic resistance R in the parasitic network g Drain parasitic resistance R d and source parasitic resistance R s The influence of this is used to obtain the ABCD noise correlation matrix expression C' for the entire circuit topology. A :

[0038] S1-4: Based on the four noise parameters of HEMT devices: minimum noise figure F min Noise resistance R n Optimal source conductivity G opt Optimal source susceptance B opt expression:

[0039]

[0040]

[0041]

[0042]

[0043] in

[0044] N = g m (R g +R s );

[0045] Here, M represents substitution factor 1, and N represents substitution factor 2;

[0046] The noise correlation matrix expression C' of ABCD A Characterized as a matrix form of four noise parameters for an InP HEMT device:

[0047]

[0048] In the formula Y opt For optimal source admittance, it is related to optimal source conductance G. opt Optimal source susceptance B opt The relationship is as follows:

[0049] Y opt =G opt +jωB opt .

[0050] The test of noise parameters for 90nm process node HEMT devices includes: obtaining the minimum noise figure F. min Noise resistance R n Optimal reflectance coefficient Γo pt Amplitude and optimal reflection coefficient Γo pt Phase.

[0051] Beneficial effects:

[0052] This invention constructs a proportional scaling relationship between the model parameters of large-size and small-size HEMT devices, which can quickly obtain the model parameters of devices with different physical sizes under the same process conditions, and can effectively predict the noise characteristics of the devices, thus shortening the modeling time. Attached Figure Description

[0053] Figure 1 This is a diagram of the PRC noise equivalent circuit model of the present invention;

[0054] Figure 2 The graph shows the changes in gate-induced noise factor P, drain-channel noise factor R, and associated noise factor C of a 90nm process node HEMT device with frequency.

[0055] Figure 3 The graph shows the changes in gate-induced noise factor P, drain-channel noise factor R, and associated noise factor C of a 70nm process node HEMT device with frequency.

[0056] Figure 4 This is a structural diagram of the test chip;

[0057] Figure 5 The noise parameters of HEMT devices at 90nm and 70nm process nodes vary with frequency.

[0058] Figure 6 The minimum noise figure F for HEMT devices at the 90nm process node. min and noise resistance R n Test data graph;

[0059] Figure 7 The optimal reflection coefficient Γ for noise parameters of HEMT devices at the 90nm process node opt Amplitude and optimal reflection coefficient Γ opt Phase, test data graph;

[0060] Figure 8 The minimum noise figure F for HEMT devices at the 70nm process node min and noise resistance R n A comparison chart of the prediction results calculated based on the proportional scaling relationship of the noise model parameters and the test results;

[0061] Figure 9 The optimal reflection coefficient Γ for noise parameters of HEMT devices at the 70nm process node opt Amplitude and optimal reflection coefficient Γ opt A comparison chart of the predicted phase calculated based on the proportional scaling relationship of the noise model parameters and the test results. Detailed Implementation

[0062] The invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0063] The following description includes certain specific details to provide a comprehensive understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can still be achieved without employing one or more of these specific details, but by using other methods, components, materials, etc.

[0064] This invention includes the following specific steps:

[0065] S1. Construct PRC noise equivalent circuit models for HEMT devices at 90nm and 70nm process nodes, such as... Figure 1 As shown, the PRC noise equivalent circuit model includes a parasitic network and an intrinsic network, wherein the parasitic network includes the gate parasitic resistance R. g Drain parasitic resistance R d and source parasitic resistance R s The intrinsic network includes the gate-source intrinsic capacitance C.gs Gate-drain intrinsic capacitance C gd Drain-source intrinsic capacitance C ds Intrinsic channel resistance R gs transconductance g m Drain output resistance R ds The time delay τ and intrinsic noise sources, including gate-induced noise sources. and drain channel noise source in,

[0066] The gate parasitic resistance R g Gate-drain intrinsic capacitance C gd and drain parasitic resistance R d It is connected in series between the gate terminal G and the drain terminal D;

[0067] The gate-induced noise source With source parasitic resistance R s The intrinsic capacitance C connected in series between the gate and drain gd and gate parasitic resistance R g Between the node and the grounding terminal;

[0068] The gate-source intrinsic capacitance C gs and intrinsic channel resistance R gs The intrinsic capacitance C connected in series between the gate and drain gd and gate parasitic resistance R g The node and the source parasitic resistance R s and the gate-induced noise source between;

[0069] The transconductance g m Time delay τ, drain output resistance R ds Drain-source intrinsic capacitance C ds and drain channel noise sources The intrinsic gate-drain capacitance C is connected in parallel. gd and drain parasitic resistance R d The node and the source parasitic resistance R s and the gate-induced noise source between;

[0070] S1-1: The correlation matrix C of the two-port admittance noise network is derived from the intrinsic network of the circuit based on the device noise model. Y expression:

[0071]

[0072] S1-2: The admittance noise correlation matrix C YConvert to ABCD noise correlation matrix C A The transformation relationship between the noise correlation matrices is as follows:

[0073]

[0074]

[0075] C A21 =(C A12 )*

[0076]

[0077] Where * denotes the conjugate of the matrix;

[0078] S1-3: Consider the gate parasitic resistance R in the parasitic network g Drain parasitic resistance R d and source parasitic resistance R s The influence of this is used to obtain the ABCD noise correlation matrix expression C' for the entire circuit topology. A :

[0079] S1-4: Based on the four noise parameters of HEMT devices: minimum noise figure F min Noise resistance R n Optimal source conductivity Go pt Optimal source susceptibility Bo pt expression:

[0080]

[0081]

[0082]

[0083]

[0084] in

[0085] N = g m (R g +R s );

[0086] Here, M represents substitution factor 1, and N represents substitution factor 2;

[0087] The noise correlation matrix expression C' of ABCD A Characterized as a matrix form of four noise parameters for an InP HEMT device:

[0088]

[0089] In the formula Yopt For optimal source admittance, it is related to optimal source conductance G. opt Optimal source susceptance B opt The relationship is as follows:

[0090] Y opt =G opt +jωB opt ;

[0091] S1-5: Based on the above noise model and noise network matrix, the expressions for the gate-induced noise factor R and the drain-channel noise factor P are derived.

[0092] P = g m [R n -(R g +R s )];

[0093]

[0094] in,

[0095]

[0096] Among them, R n For noise resistance, R g Gate parasitic resistance, R s For source parasitic resistance, g m For transconductance, C gs For gate-source intrinsic capacitance, C gd For gate-drain intrinsic capacitance, B opt For optimal source susceptance, G opt For optimal source conductance, ω is the angular frequency, and h1 and h2 represent simplification factor 1 and simplification factor 2, respectively.

[0097] S2: Establish a scaling relationship between the noise model parameters of HEMT devices at the 90nm process node and the 70nm process node;

[0098]

[0099]

[0100] Among them, P 70 P represents the drain-channel noise factor of a 70nm HEMT device. 90 R represents the drain-channel noise factor of a 90nm process node HEMT device. 70 R represents the gate-induced noise factor of a 70nm process node HEMT device. 90 This refers to the gate-induced noise factor of a 90nm process node HEMT device. This refers to the gate current of a 70nm process node HEMT device. Transconductance for 70nm process node HEMT devices This refers to the gate current of a 90nm process node HEMT device. Transconductance for HEMT devices at the 90nm process node;

[0101] S3. Obtain the minimum noise figure F of the 90nm process node HEMT device through testing. min Noise resistance R n Optimal reflectance coefficient Γ opt Amplitude and optimal reflection coefficient Γ opt Phase, based on the scaling relationship between the noise model parameters, predicts the minimum noise figure F of 70nm process node HEMT devices. min Noise resistance R n Optimal reflectance coefficient Γ opt Amplitude and optimal reflection coefficient Γ opt Phase.

[0102] This invention constructs an accurate noise model for InP HEMT devices to accurately predict device and circuit characteristics. It establishes a proportional scaling relationship between the parameters of large-size and small-size HEMT device models, and quickly obtains the noise parameters of devices of different physical sizes under the same process conditions to predict the noise characteristics of the devices. It features high speed and high accuracy.

[0103] To characterize the high accuracy of the claimed technical solution in predicting the noise characteristics of devices, the following verification experiments were conducted to verify the correctness of the noise model and its parameter extraction method, as well as the correctness of the proportional scaling relationship of the noise model parameters:

[0104] 1. Verify the correctness of the noise model and its parameter extraction method.

[0105] (1) Using Agilent's RF circuit design software ADS (Advanced Design System), the doping and structure are shown in Table 1. Figure 4 Model parameters were extracted for the 90nm and 70nm process node InP HEMT devices shown.

[0106] The minimum noise figure F of InP HEMT devices at 90nm and 70nm process nodes was obtained through testing. min Noise resistance R n .

[0107] Table 1

[0108]

[0109] (2) The gate parasitic resistance R of the parasitic network model is extracted using the reverse cutoff method. g Drain parasitic resistance R d and source parasitic resistance R s Based on the direct extraction method of model parameters and the parasitic resistance extraction method, the parameters at the bias V are extracted respectively. ds =1.0V and I ds At a bias voltage of 15.0mA, 70nm InP HEMT devices and 90nm InP HEMT devices are compared under the condition of bias V. ds =1.0V and I ds Small-signal model parameters under the condition of 14.7mA, including the intrinsic network model parameters gate-source intrinsic capacitance C. gs Gate-drain intrinsic capacitance C gd Drain-source intrinsic capacitance C ds Intrinsic channel resistance R gs transconductance g m and drain output resistance R ds Table 2 presents the small-signal model parameter extraction results for 70nm and 90nm InP HEMT devices. It can be seen that for the 70nm device, C... gs C gd , gm and R ds The corresponding values ​​are 47 fF, 5 fF, 95 mS, and 170 Ω, respectively. (C of the 90nm device) gs C gd g m and R ds The corresponding values ​​are 35 fF, 6.5 fF, 28 mS, and 260 Ω, respectively.

[0110] Table 2

[0111]

[0112] (3) After the small signal model parameters are determined, they are substituted into the noise parameter expression derived in the embodiment of the present invention to extract the curves of the gate-induced noise factor, drain-channel noise factor and related noise factor of 70nm and 90nm InP HEMT devices as a function of frequency.

[0113] (4) Based on the relationships between the gate-induced noise factor, drain-channel noise factor, and correlated noise factor in S1 and the minimum noise figure, noise resistance, optimal source conductance, and optimal source susceptance, the variation curves of the gate-induced noise factor P, drain-channel noise factor R, and correlated noise factor C of 70nm and 90nm InP HEMT devices with frequency can be extracted, as follows: Figure 2 and Figure 3 As shown; where Figure 2For a 90nm InP HEMT device with a bias of V ds =1V and I ds Noise factor extraction results under the condition of 14.7mA; Figure 3 For 70nm InP HEMT devices with a bias of V ds =1V and I ds The noise factor extraction results under the condition of 15mA are shown in the figure. The square represents the gate-induced noise factor P, the circle represents the drain-channel noise factor R, and the triangle represents the correlated noise factor C.

[0114] Based on the gate-induced noise factor P, drain-channel noise factor R, and correlated noise factor C in S1, and the minimum noise figure F min Noise resistance R n Optimal source conductivity G opt Optimal source susceptance B opt The relation can be obtained with bias V. ds =1V and I ds The noise parameters of a 90nm process node InP HEMT device at a bias of V = 14.7mA are compared with those at a bias of V. ds =1V and I ds The noise parameters of a 70nm process node InP HEMT device as a function of frequency under a current of 15mA is shown in the figure below. Figure 5 As shown, where Figure 5 (a), (b), (c), and (d) represent the minimum noise figure F, respectively. min Noise resistance R n Optimal reflectance coefficient Γ opt Amplitude and optimal reflectivity Γ opt The phase versus frequency curve; the solid line represents the simulation result of the noise model, and the circles represent the test result. From Figure 5 It can be seen that the deviation between the simulation results and the test results from 8GHz to 45GHz is very small, almost negligible. This proves the correctness and accuracy of the noise model and its parameter extraction method.

[0115] 2. Verify the correctness of the relationship between the noise model parameters.

[0116] Doping and structure are shown in Table 2. Figure 4 The 90nm and 70nm process node InP HEMT devices shown were tested.

[0117] The minimum noise figure F of InP HEMT devices at 30GHz and 90nm process nodes was obtained through testing. min Noise resistance R n Optimal reflection opt Amplitude and optimal reflectivity Γopt Phase.

[0118] like Figure 6 As shown, the test results of 90nm process node InP HEMT at 30GHz are presented, with the horizontal axis I... ds (mA) represents the gate current, and the left vertical axis F min The minimum noise figure, with the right ordinate R. n This is the noise resistor. For example... Figure 7 As shown, the test results of 90nm process node InP HEMT at 30GHz are presented, with the horizontal axis I... ds (mA) represents the gate current, and the left vertical axis Γ opt The amplitude is the optimal reflection coefficient, and the right ordinate is Γ. opt The phase is the optimal reflection coefficient.

[0119] like Figure 8 The figure shown is the minimum noise figure F of a 70nm process node HEMT device at a frequency of 30GHz. min and noise resistance R n A comparison chart of prediction results calculated based on the proportional scaling relationship of noise model parameters and test results; x-axis I ds (mA) represents the gate current, and the left vertical axis F min The minimum noise figure, with the right ordinate R. n For noise resistance, the solid line represents the predicted relationship between noise model parameters, and the circle represents the experimental test results; for example... Figure 9 As shown, the optimal reflection coefficient Γ for noise parameters of a 70nm process node HEMT device at a frequency of 30GHz is... opt Amplitude and optimal reflection coefficient Γ opt A comparison graph of the predicted phase calculated based on the proportional scaling relationship of the noise model parameters and the test results; the horizontal axis I ds (mA) represents the gate current, and the left vertical axis Γ opt The amplitude is the optimal reflection coefficient, and the right ordinate is Γ. opt The phase represents the optimal reflection coefficient, the solid line represents the predicted relationship between the noise model parameters, and the circle represents the experimental test results.

[0120] It can be seen that the results predicted by scaling the model parameters of large-size 90nm process node HEMT devices and small-size 70nm process node HEMT devices are in good agreement with the experimental test results, which shows the correctness and accuracy of scaling the model parameters of large-size and small-size HEMT devices.

[0121] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for predicting noise parameters of advanced process node HEMT devices, characterized in that, The method includes the following steps: S1. Construct the PRC noise equivalent circuit model of HEMT devices at 90nm and 70nm process nodes, and derive the expressions for the gate-induced noise factor R and the drain-channel noise factor P. ； ； in, ; ； in, For noise resistance, For gate parasitic resistance, For source parasitic resistance, For transconductance, Gate-source intrinsic capacitance, Gate-drain intrinsic capacitance, For optimal source susceptance, For optimal source conductivity and Angular frequency, and These represent simplification factor 1 and simplification factor 2, respectively. S2. Establish a proportional scaling relationship between the noise model parameters of HEMT devices at the 90nm process node and the 70nm process node. ； ； in, This refers to the drain-channel noise factor of a 70nm HEMT device. This refers to the drain-channel noise factor of a 90nm process node HEMT device. This refers to the gate-induced noise factor of a 70nm process node HEMT device. This refers to the gate-induced noise factor of a 90nm process node HEMT device. This refers to the gate current of a 70nm process node HEMT device. Transconductance for 70nm process node HEMT devices This refers to the gate current of a 90nm process node HEMT device. Transconductance for HEMT devices at the 90nm process node; S3. Test the noise parameters of the 90nm process node HEMT device, and predict the noise parameters of the 70nm process node HEMT device based on the relationship between the noise model parameters.

2. The method as described in claim 1, characterized in that, The PRC noise equivalent circuit model includes a parasitic network and an intrinsic network, wherein the parasitic network includes the gate parasitic resistance. Drain parasitic resistance and source parasitic resistance The intrinsic network includes gate-source intrinsic capacitance. Gate-drain intrinsic capacitance Drain-source intrinsic capacitance Intrinsic channel resistance transconductor Drain output resistance Time delay And intrinsic noise sources, including gate-induced noise sources. and drain channel noise source ,in, The gate parasitic resistance Gate-drain intrinsic capacitance and drain parasitic resistance It is connected in series between the gate terminal G and the drain terminal D; The gate-induced noise source With source parasitic resistance Connected in series with the intrinsic gate-drain capacitor and gate parasitic resistance Between the node and the grounding terminal; The gate-source intrinsic capacitance and intrinsic channel resistance Connected in series with the intrinsic gate-drain capacitor and gate parasitic resistance The node and the source parasitic resistance and the gate-induced noise source between; The transconduct Time delay Drain output resistance Drain-source intrinsic capacitance and drain channel noise sources Parallel to the gate-drain intrinsic capacitance and drain parasitic resistance The node and the source parasitic resistance and the gate-induced noise source between.

3. The method as described in claim 2, characterized in that, The expression for the PRC noise equivalent circuit model is as follows: ； ； The gate-induced noise and drain channel noise Correlation noise between Represented as: ； in, For noise bandwidth, The Boltzmann constant is 1.38 × 10⁻²³ J / K. For absolute temperature, set to 290K. This represents the relevant noise factor.

4. The method as described in claim 3, characterized in that, The expressions for the gate-induced noise factor R and the drain-channel noise factor P are derived from the equivalent circuit model two-port noise network matrix. The correlation matrix of the equivalent circuit model two-port noise network is obtained by the following steps: S1-1: The correlation matrix of the two-port admittance noise network is derived from the intrinsic network of the circuit based on the device noise model. expression: j represents the imaginary part; S1-2: The admittance noise correlation matrix Convert to ABCD noise correlation matrix The transformation relationship between the noise correlation matrices is as follows: ； ； ； ； Where * denotes the conjugate of the matrix; S1-3: Consider the gate parasitic resistance in the parasitic network Drain parasitic resistance and source parasitic resistance The influence of this is used to obtain the ABCD noise correlation matrix expression for the entire circuit topology. : S1-4: Based on the four noise parameters of HEMT devices: minimum noise figure noise resistance Optimal source conductivity Optimal source susceptibility expression: ； ； ； ； in ; ； here, Indicates substitution factor 1, This indicates a substitution factor of 2; The expression of the noise correlation matrix of ABCD Characterized as a matrix form of four noise parameters for an InP HEMT device: ； In the formula For optimal source admittance, it is related to optimal source conductance. Optimal source susceptibility The relationship is as follows: 。 5. The method as described in claim 1, characterized in that, The test of noise parameters for 90nm process node HEMT devices includes: obtaining the minimum noise figure. noise resistance Optimal reflectance Amplitude and optimal reflectivity Phase.

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