Power supply control device, circuit, and method

Abstract

A power supply control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease in a voltage level of the first voltage signal. Embodiments of the present application also relate to power supply control circuits and methods.

Description

Technical Field

[0001] Embodiments of this application relate to power control devices, circuits, and methods. Background Technology

[0002] Some known memory devices, such as static random access memory (SRAM) devices, include power-switching control designs. A typical SRAM memory device has an array of memory cells. Each memory cell uses a transistor device connected between an upper reference potential and a lower reference potential (typically ground), allowing one of the two storage nodes to be occupied by the information to be stored, while complementary information is stored at the other storage node. Some SRAM devices operate the memory logic in a low-voltage domain and the memory array in a high-voltage domain. Furthermore, various techniques can be employed to reduce power consumption. For example, portions of the memory device can be shut down during sleep or power-off modes. Power switching mechanisms are provided to switch between different voltage domains and to implement different operating modes, such as power-off mode. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a power control device is provided, comprising: a first switch, a first terminal of which is configured to receive a first voltage signal in a first voltage domain; a second switch, a first terminal of which is configured to receive a second voltage signal in a second voltage domain different from the first voltage domain, a second terminal of which is coupled to a second terminal of the first switch; and a control circuit coupled to control terminals of the first switch and the second switch, and configured to turn on the first switch in response to a decrease in the voltage level of the first voltage signal.

[0004] According to another aspect of the embodiments of this application, a power control circuit is provided, comprising: a first voltage domain input terminal; a second voltage domain input terminal; a first transistor having a first source / drain terminal connected to the first voltage domain input terminal and a second source / drain terminal connected to a voltage output terminal; a second transistor having a first source / drain terminal connected to the second voltage domain input terminal and a second source / drain terminal connected to the voltage output terminal; a control circuit having an enable input terminal and an output terminal connected to the gate terminals of the first transistor and the second transistor; and an enable circuit including an inverter having an input terminal connected to the first voltage domain input terminal and an output connected to the enable input terminal.

[0005] According to another aspect of the embodiments of this application, a power control method is provided, comprising: receiving a first voltage signal in a first power domain via a first switch; receiving a second voltage signal in a second power domain via a second switch; receiving a power-off signal having a first logic level indicating a power-off mode; turning off the first switch and the second switch in response to the first logic level of the power-off signal; and then turning on the first switch in response to a decrease in the first voltage signal in the power-off mode. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram illustrating an example of a memory device according to some embodiments.

[0008] Figure 2 This is a block diagram illustrating further aspects of the control circuit and head circuit.

[0009] Figure 3 This is a block diagram illustrating an example of a memory array according to some embodiments.

[0010] Figure 4 The illustrations are based on some embodiments. Figure 3 A schematic diagram of an example of an SRAM memory cell in the memory array shown.

[0011] Figure 5 This is a schematic diagram illustrating an example of a power switch control circuit according to some embodiments.

[0012] Figure 6 This is a schematic diagram illustrating an example of an enable circuit according to some embodiments.

[0013] Figure 7 The illustration corresponds to some embodiments. Figure 5 The diagram shows an example waveform of the power switch control circuit.

[0014] Figure 8 The illustration corresponds to some embodiments. Figure 5 The diagram shows a table of logic values ​​for various signals in the power switch control circuit.

[0015] Figure 9 This is a schematic diagram illustrating another example of a power switch control circuit according to some embodiments.

[0016] Figure 10This is a schematic diagram illustrating another example of an enable circuit according to some embodiments.

[0017] Figure 11 The illustration corresponds to some embodiments. Figure 9 The diagram shows a table of logic values ​​for various signals in the power switch control circuit.

[0018] Figure 12 This is a schematic diagram illustrating another example of a head circuit and control circuit according to some embodiments.

[0019] Figure 13 This is a schematic diagram illustrating another example of a power switch control circuit according to some embodiments.

[0020] Figure 14 The illustration corresponds to some embodiments. Figure 13 The diagram shows a table of logic values ​​for various signals in the power switch control circuit.

[0021] Figure 15 This is a schematic diagram illustrating another example of a head circuit and control circuit according to some embodiments.

[0022] Figure 16 This is a schematic diagram illustrating another example of a power switch control circuit according to some embodiments.

[0023] Figure 17 The illustration corresponds to some embodiments. Figure 16 The diagram shows a table of logic values ​​for various signals in the power switch control circuit.

[0024] Figure 18 This is a flowchart illustrating a method according to some embodiments. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, this document may use spacing relation terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein may be interpreted accordingly.

[0027] Some memory devices, such as static random access memory (SRAM) devices, include power-switching control circuitry. A typical SRAM memory device has an array of memory cells. Example SRAM devices have memory cells, each using six transistors connected between an upper reference potential and a lower reference potential (typically ground), such that one of the two storage nodes can be occupied by the information to be stored, while complementary information is stored at the other storage node. Some SRAM devices operate the memory logic in a low-voltage domain and the memory array in a high-voltage domain. Furthermore, various techniques can be employed to reduce power consumption. For example, portions of the memory device can be shut down during sleep mode or power-off (SD) mode. Problems can arise if the switching procedure is not carefully controlled.

[0028] In some implementations, the power switching circuit is configured to select between power rails for different power domains, such as VDD and VDDM. Therefore, the control circuit can be configured to select either VDD or VDDM in a dual-supply scheme. The control circuit may include power switches, such as CMOS transistors, that respond to corresponding control signals for the VDDM and VDD domains.

[0029] Figure 1 Example electronic devices, such as SRAM memory device 10, are shown according to some embodiments. Figure 1 As shown, the example SRAM device 10 includes an SRAM macro 20, which includes an SRAM core 30 and a power switch control circuit 100.

[0030] SRAM device 10 is configured to operate in two different power domains. The example SRAM device 10 thus includes voltage input terminals corresponding to the two voltage domains: a VDD input terminal configured to receive the VDD input voltage of the VDD power domain, and a VDDM input terminal configured to receive the VDDM input voltage of the VDDM power domain. SRAM macro 20 also includes power switch control circuitry 100, configured to selectively control the output of VDD voltage signals and / or VDDM voltage signals to SRAM core 30.

[0031] Logic circuits 40 and 42, located in the VDDM and VDD voltage domains respectively, provide control signals to the SRAM core 30 and / or power switching circuit 100. For example, one or both of logic circuits 40 and 42 can output sleep and power-off signals to components of the SRAM macro 20. In some embodiments, logic circuits 40 and 42 can output deep sleep (DSLP), light sleep (LSLP), and / or power-off (SD) control signals. In LSLP and DSLP modes, the memory array can continue to receive power when different combinations of peripheral components are powered off, while in power-off mode, power can be removed from both peripheral components and the memory array.

[0032] In the example shown, the power switch control circuit 100 outputs a control signal to the head circuit 102. The power switch control circuit 100 controls power switches 110 and 112 to selectively output the power signal VDD_SRAM to the SRAM core 30. Figure 1 In the example, the power switch is implemented by a p-type metal-oxide-semiconductor (PMOS) transistor. Therefore, in memory operation mode, the control circuit 100 controls the power switches 110, 112 of the header circuit 102 to connect the VDD or VDDM terminals to output the VDD_SRAM signal to the SRAM core 30 in the desired VDD power domain or VDDM power domain. Figure 1 The diagram illustrates control circuitry 100 and header circuitry connected to SRAM core 30, but this disclosure is not limited to SRAM memory. For example, control circuitry 100 can be used with other types of memory or other devices powered by different power domains.

[0033] Figure 2 Further aspects of the control circuit 100 and the head circuit 102 are illustrated. The power switch control circuit 100 is configured to output gate control signals GMB and GDB to the gate terminals of switches 110 and 112, respectively. Switch 110 has one source / drain terminal connected to the VDD input terminal, and its other source / drain terminal connected to the output terminal VDD_SRAM. Therefore, switch 110 is sometimes referred to herein as "VDD control switch 110". Switch 112 has one source / drain terminal connected to the VDDM input terminal, and its other source / drain terminal connected to the output terminal VDD_SRAM. Therefore, the second switch 112 is sometimes referred to herein as "VDDM control switch 112".

[0034] In power-off mode, for example, logic high (i.e., logic 1) gate control signals GMB and GDB are applied to the gate terminals of power switches 110 and 112 to turn off both switches, thereby disconnecting the SRAM core 30 from the VDDM and VDD input terminals. In other embodiments, the power switches may be implemented using n-type metal-oxide-semiconductor (NMOS) transistors, in which case the control signals will be reversed. Furthermore, in other embodiments, other types of control switches may be employed.

[0035] Therefore, in power-off mode, both gate control signals GMB and GDB are forced to predetermined levels (e.g., logic 1 for a PMOS transistor) to turn off both power switches 110 and 112 and reduce leakage. However, in some cases, such as when the VDD voltage signal collapses (i.e., drops to 0) during power-off mode, a leakage path created by gate-induced drain leakage (GIDL) may exist. The collapsed VDD and high GDB gate signals (i.e., the VDD control signals) create a negative bias level on the VDD control switch 110, which in turn causes GIDL leakage. GIDL leakage is proportional to the negative bias level because more valence band electron-hole pairs tunnel into the conduction band are created under a larger electric field.

[0036] According to some embodiments, additional pins are provided to force the appropriate control signals GMB and / or GDB of the PMOS power control switches 110, 112 from 1 to 0 after a collapse of the VDD and / or VDDM input voltages (such as due to being turned off during a power-saving shutdown mode). In other words, the appropriate switches 110, 112 are turned on in response to a collapse of VDD or VDDM. This reduces bulk-to-source leakage (by 12% in some examples) and increases channel leakage. In examples where the control switches are implemented by PMOS transistors, the total leakage savings can be approximately 51% and 38%, respectively. Therefore, as used herein, "X-rail depletion mode" refers to the operation of switches 110 and / or 112 controlled by control circuitry 100 when the VDD and / or VDDM voltages collapse.

[0037] SRAM core 30 includes one or more memory arrays 50, which include a plurality of memory cells 52 or bit cells. Figure 3 An example of one of the memory arrays 50 is illustrated. The SRAM core 30 also includes input / output (I / O) circuitry 54 connected to logic circuitry 42. The memory cells 52 and the I / O circuitry 54 are coupled via complementary bit lines BL and BLB, and data can be read from and written to the memory cells 52 via the complementary bit lines BL and BLB. Figure 3In the example, memory cell 52 is an SRAM cell. However, the present invention is not limited to SRAM memory.

[0038] Figure 4 This is a circuit diagram illustrating an example SRAM memory cell 52 according to some embodiments. Memory cell 52 includes, but is not limited to, a six-transistor (6T) SRAM structure. In some embodiments, memory cell 52 may be implemented using more or fewer than six transistors. For example, in some embodiments, memory cell 52 may use a 4T, 8T, or 10T SRAM structure, and in other embodiments may include memory class bit cells or building blocks. Memory cell 52 includes a first inverter formed by NMOS / PMOS transistor pairs M1 and M2, a second inverter formed by NMOS / PMOS transistor pairs M3 and M4, and access transistors / transmission gates M5 and M6. Transistors M1, M3, M5, and M6 include n-type metal-oxide-semiconductor (NMOS) transistors, and transistors M2 and M4 include p-type metal-oxide-semiconductor (PMOS) transistors.

[0039] The first and second inverters are cross-coupled to form a latch circuit for data storage. The first terminal of each of transistors M2 and M4 is coupled to the power supply VDD, while the first terminal of each of transistors M1 and M3 is coupled to a reference voltage VSS, such as ground. The gate of transmission gate transistor M6 is coupled to the word line WL. The drain of transmission gate transistor M6 is coupled to the bit line BL. Furthermore, the first terminal of transmission gate transistor M6 is coupled to the second terminals of transistors M4 and M3, and also to the gates of M2 and M1 at node Q. Similarly, the gate of transmission gate transistor M5 is coupled to the word line WL. The drain of transmission gate transistor M5 is coupled to the complementary bit line BLB. Furthermore, the first terminal of transmission gate transistor M5 is coupled to the second terminals of transistors M2 and M1, and also to the gates of M2 and M1 at node Q. It is coupled to the gates of transistors M4 and M3.

[0040] Figure 5 This is a schematic diagram of an embodiment 100a of the control circuit 100. The control circuit 100a includes an enable pin or enable terminal for receiving an enable signal 101. As described above, the control circuit 100 outputs gate control signals GDB and GMB to the gate terminals of switches 110 and 112 to selectively turn on one or both of switches 110 and 112 in response to a drop or decrease in the voltage level of the VDDM and / or VDD voltage signals. The enable signal 101 responds to the voltage level of the VDD and / or VDDM signals. Figure 5In the example shown, control circuit 100a is configured to turn on VDD control switch 110 in response to a collapse of the VDD voltage. As discussed in further detail below, when enable signal 101 indicates a collapse of the VDD signal, GDB control signal goes low to turn on VDD control switch 110 and depress the body source of VDD control switch 110.

[0041] Figure 6 An example of an enable circuit 120 is illustrated, configured to output an enable signal 101 received by control circuit 100a. Control circuit 100 is configured to turn on VDD control switch 110 in response to a collapse of the VDD voltage signal. In the illustrated example, switches 110 and 112 are PMOS transistors, which are turned on based on a low active signal at their gate terminals. Therefore, enable circuit 120 includes an inverter 122, whose input terminals are connected to the VDD voltage terminal. When the VDD signal collapses (i.e. becomes 0), inverter 122 outputs a high enable signal 101.

[0042] return Figure 5 The control circuit 100a shown includes a first input terminal 130 configured to receive a power-off signal SD and a second input terminal 132 configured to receive an SRAM select signal AON_SELSRAM_IN. The control circuit 100 includes a first level shifter 134 and a second level shifter 136 that respectively receive the power-off signal SD and the SRAM select signal AON_SELSRAM_IN. The first and second level shifters 134 and 136 shift the voltage levels of the corresponding input signals. For example, the first and second level shifters 134 and 136 can receive the corresponding input signals in the VDD voltage domain and output these signals in the VDDM voltage domain. The output of the first level shifter 134 is connected to an inverter 140, which outputs an inverted power-off signal SD as an inverse power-off signal SDB. The level-shifted SRAM select signal AON_SELSRAM_IN is output to inverters 142 and 144. The output of inverter 144 is received by another inverter 146.

[0043] NAND gates 148 and 150 receive the outputs of inverters 142 and 146, and the inverse power-off signal SDB, respectively. The output of NAND gate 150 is received by inverters 154 and 156, and inverter 156 outputs the control signal GMB received at the gate terminal of VDDM control switch 112. Inverter 152 receives the output of NAND gate 148 and provides an input signal to NOR gate 158. NOR gate 158 also receives enable signal 101 and outputs the control signal GDB to VDD control switch 110. In addition to facilitating appropriate logic outputs, Figure 5The inverter shown provides the required signal timing; therefore, more or fewer inverters can be used to achieve the correct timing of the output signal.

[0044] Figure 7 It is a combination of diagrams Figure 5 The waveforms of the various signals discussed are presented in graphs. Figure 8 This is a table showing the logic values ​​of certain signals in the diagram. In memory mode, SRAM core 30 receives power from header circuitry 102 to operate memory array 50, and the power-off signal is at a low logic level. When the power-off signal SD goes high to indicate power-off mode, inverter 140 outputs a low inverse power-off SDB signal. The low SDB signal causes high outputs from NAND gates 148 and 150. The high output from NAND gate 150 causes a high GMB signal, which, during power-off mode, turns off VDDM control switch 112 and disconnects the VDDM input terminal from SRAM core 30.

[0045] The high output of NAND gate 148 is output to inverter 152, which provides a low input to NOR gate 158. Enable signal 101 remains low until the VDD signal fails. Therefore, before the VDD signal fails, NOR gate 158 outputs a high GDB control signal to VDD control switch 110, turning off VDD control switch 110 to disconnect the VDD input terminal from SRAM core 30 during power-off mode.

[0046] When the VDD signal crashes (i.e., drops to 0 or logic low), the inverter 122 of the enable circuit 120 outputs a high enable signal 101, indicating X-track down mode. The high-level enable signal 101 received by the NOR gate 158 causes the GDB control signal to go low. This turns on the VDD control switch 110, thereby reducing body-to-source leakage.

[0047] Figure 9 This is a schematic diagram of another embodiment 100b of the control circuit 100. Figure 5 The control circuit 100a shown is configured to turn on the VDD control switch 110 after a VDD voltage failure, while Figure 9 The control circuit 100b shown turns on the VDDM control switch 112 in response to a drop in the VDDM voltage during the shutdown mode. Therefore, in Figure 9 In the example shown, enable signal 101 responds to a collapse of the VDDM voltage. Therefore, when enable signal 101 indicates a collapse of the VDDM signal, the GMB control signal goes low to turn on the VDDM control switch 112 and reduce the body-to-source leakage of the VDDM control switch 112.

[0048] Figure 10An example of an enable circuit 124 configured to output an enable signal 101 to indicate a collapse of the VDDM signal in control circuit 100b is illustrated. Control circuit 100b is configured to turn on VDDM control switch 110 in response to a collapse of the VDDM voltage signal. Figure 5 The example is the same. Figure 9 Switches 110 and 112 in the circuit are PMOS transistors, which are turned on based on a low active signal at their gate terminals. Therefore, in Figure 10 In the enable circuit 124 shown, the input terminal of the inverter 126 is connected to the VDDM voltage terminal. When the VDDM signal crashes (i.e. drops to 0 or logic low), the inverter 126 outputs a high enable signal 101.

[0049] Similar to Figure 5 The control circuit 100a shown is... Figure 9 The control circuit 100b includes a first input terminal 130 configured to receive a power-off signal SD, and a second input terminal 132 configured to receive an SRAM select signal AON_SELSRAM_IN. The control circuit 100b also includes a first level shifter 134 and a second level shifter 136 that receive the power-off signal SD and the SRAM select signal AON_SELSRAM_IN, respectively. The output of the first level shifter 134 is connected to an inverter 140, which outputs an inverse power-off signal SDB.

[0050] exist Figure 9 In the example, the level-shifted SRAM select signal AON_SELSRAM_IN is output to inverters 162 and 164. The output of inverter 162 is received by another inverter 166. The outputs of inverters 166 and 164, as well as the inverse power-off signal SDB, are received by NAND gates 168 and 170, respectively. The output of NAND gate 170 is received by inverter 174, which is connected to another inverter 176, and then inverter 176 outputs the control signal GDB received at the gate terminal of VDD control switch 110. Inverter 172 receives the output of NAND gate 168 and provides an input signal to NOR gate 178. NOR gate 178 also receives enable signal 101 and outputs the control signal GMB to VDDM control switch 112. Figure 5 The example is the same. Figure 9 The inverters shown provide the required signal timing, and therefore, the correct timing of the signal output can be achieved using more or fewer inverters.

[0051] Figure 11 The diagram corresponds to Figure 9The table shows the logic values ​​of the signals in the circuit. When the power-off signal SD goes high to indicate power-off mode, inverter 140 outputs a low power-off signal SDB. The low SDB signal causes the NAND gates 168 and 170 to go high. The high output of NAND gate 170 causes the GDB signal to go high, which shuts off the VDD control switch 110 and disconnects the VDD input terminal from the SRAM core 30 during power-off mode.

[0052] The high output of NAND gate 168 is output to inverter 172, which provides a low input to NOR gate 178. Enable signal 101 remains low until the VDDM signal fails. Therefore, before the VDDM signal fails, NOR gate 178 outputs a high GMB control signal to VDDM control switch 112, turning off VDDM control switch 112 during power-off mode to disconnect the VDDM input terminal from SRAM core 30.

[0053] When the VDDM signal collapses (i.e. drops to 0), the inverter 126 of the enable circuit 124 outputs a high enable signal 101. The high enable signal 101 received by the NOR gate 178 causes the GMB control signal to go low. This turns on the VDDM control switch 112, thereby reducing body-to-source leakage caused by the VDDM signal collapse.

[0054] Figure 12 and Figure 13 The diagram shows Figure 1 Another example of the control circuit 100 and head circuit 102. More specifically, Figure 12 An embodiment of the head circuit 102a is illustrated, in which a "stack" of VDD control switches is employed. One or more first VDD control switches 110-1 are connected in series with a second VDD control switch 110-2. Figure 12 In the example, the first VDD control switch 110-1 includes one or more PMOS switches P2_1 to P2_n, with the source / drain of the PMOS switches P2_1 to P2_n connected, such that switch 110-1 is connected in series with the second VDD control switch 110-2. The first VDD control switch 110-1 is controlled by the GDB control signal, while the second VDD control switch 110-2 is controlled by the GDB2 control signal output by the control circuit 100c.

[0055] Figure 13 The diagram illustrates aspects of the control circuit 100c. The control circuit 100c receives an enable signal 101, which responds to the collapse of the VDD terminal. Therefore, Figure 6The enable circuit 120 shown can provide an enable signal 101 to the control circuit 100c. The control circuit 100c outputs a GMB gate control signal to the gate terminal of the VDDM control switch 112, and outputs GDB and GDB2 control signals to the first and second VDD control switches 110-1 and 110-2, respectively. The GDB2 control signal is configured to selectively turn on the second VDD control switch 110-2 in response to a drop or decrease in the voltage level of the VDD voltage signal, thereby reducing the body-to-source leakage of the second VDD control switch 110-2.

[0056] Figure 13 Control circuit 100c and Figure 5 The control circuit 100a shown is similar, but further configured to output a GDB2 signal. Therefore, the control circuit 100c includes a first input terminal 130 for receiving a power-off signal SD and a second input terminal 132 for receiving an SRAM select signal AON_SELSRAM_IN. A first level shifter 134 and a second level shifter 136 receive the power-off signal SD and the SRAM select signal AON_SELSRAM_IN, respectively. An inverter 140 outputs an inverted power-off signal SD as an inverted power-off signal SDB. The level-shifted SRAM select signal is output to inverters 142 and 144, and the output of inverter 144 is received by inverter 146.

[0057] NAND gates 148 and 150 receive the outputs of inverters 142 and 146, as well as the reverse power-off signal SDB, respectively. The output of NAND gate 150 is received by inverters 154 and 156 to output the GMB control signal received at the gate terminal of VDDM control switch 112. Inverter 152 receives the output of NAND gate 148 and provides an input signal to NOR gate 158. Additionally, inverter 153 is connected to receive the output of inverter 152. Inverter 153 outputs the GDB control signal to the first VDD control switch 110-1.

[0058] like Figure 14 As shown in the table, the GDB control signal remains high before the VDD signal collapses (i.e., in shutdown mode) and after the VDD signal collapses (i.e., in X-track de-mode). In other words, the control circuit 100c provides the GDB control signal to the first VDD control switches 110-1, causing these switches to remain off during shutdown mode.

[0059] and Figure 5 The control circuit is the same as 100a. Figure 13 The NOR gate 158 in the circuit receives the output of inverter 152 and also the enable signal 101, and outputs the control signal GDB2 to the second VDD control switch 110-2. For example... Figure 14As shown in the table, when the power-off signal SD goes high to indicate power-off mode, inverter 140 outputs a low inverse power-off SDB signal. The low SDB signal causes NAND gates 148 and 150 to output high. The high output of NAND gate 150 causes a high GMB signal, which turns off the VDDM control switch 112 and disconnects the VDDM input terminal from the SRAM core 30 during power-off mode.

[0060] The high output of NAND gate 148 is output to inverter 152, and the output of inverter 152 is received by inverter 153 to output a high GDB signal to the first VDD control switch 110-1. The low output of inverter 152 is further provided to NOR gate 158. Before the VDD signal collapses, enable signal 101 remains low and NOR gate 158 correspondingly outputs a high GDB2 control signal to the second VDD control switch 110-2, disconnecting the VDD input terminal from the SRAM core 30 during power-off mode.

[0061] When the VDD signal collapses (i.e. drops to 0), the inverter 122 of the enable circuit 120 outputs a high enable signal 101, indicating X-track down mode. The high enable signal 101 received by the NOR gate 158 causes the GDB2 control signal to go low. This turns on the second VDD control switch 110-2, reducing body-to-source leakage.

[0062] Figure 15 and Figure 16 It shows Figure 1 Another example of the control circuit 100 and head circuit 102. More specifically, Figure 15 An embodiment of head circuit 102b is shown, in which a stack of VDDM control switches is employed. One or more first VDDM control switches 112-1 are connected with their source / drain terminals connected, such that switch 112-1 is connected in series with a second VDDM control switch 112-2. Figure 15 In this circuit, the first VDDM control switch 112-1 includes one or more PMOS switches P2_1 to P2_n connected in series with the second VDDM control switch 112-2. The first VDDM control switch 112-1 is controlled by a GMB control signal, while the second VDDM control switch 112-2 is controlled by a GMB2 control signal output by the control circuit 100d.

[0063] Figure 16 The diagram illustrates one aspect of the control circuit 100d. The control circuit 100d receives an enable signal 101, which responds to the collapse of the VDDM terminal. Therefore, Figure 10The enable circuit 124 shown can provide an enable signal 101 to the control circuit 100d. The control circuit 100d outputs the GDB gate control signal to the gate terminal of the VDD control switch 110, and outputs the GMB and GMB2 control signals to the first and second VDDM control switches 112-1 and 112-2, respectively. The GMB2 control signal is configured to selectively turn on the second VDDM control switch 112-2 in response to a drop or decrease in the voltage level of the VDDM voltage signal, thereby reducing the body-to-source leakage of the second VDDM control switch 112-2.

[0064] Figure 16 Control circuit 100d and Figure 9 The control circuit 100b shown is similar, but is further configured to output a GMB2 signal in response to a collapse of the VDDM voltage during the shutdown mode to turn on the second VDDM control switch 112-2, thereby reducing body-to-source leakage.

[0065] The control circuit 100d has a first input terminal 130 for receiving a power-off signal SD and a second input terminal 132 for receiving an SRAM select signal AON_SELSRAM_IN. The output of a first level shifter 134 is connected to an inverter 140, which outputs a reverse power-off signal SDB. The level-shifted SRAM select signal AON_SELSRAM_IN is output to inverters 162 and 164, and the output of inverter 162 is received by inverter 166. The outputs of inverters 166 and 164, along with the reverse power-off signal SDB, are received by NAND gates 168 and 170, respectively. The output of NAND gate 170 is received by inverter 174, and inverter 176 outputs a control signal GDB received at the gate terminal of the VDD control switch 110.

[0066] Inverter 172 receives the output of NAND gate 168 and provides an input signal to NOR gate 178. Additionally, inverter 173 is connected to receive the output of inverter 172. Inverter 173 outputs a GMB control signal to the first VDDM control switch 112-1.

[0067] like Figure 17 As shown in the table, the GMB control signal remains high before the VDDM signal collapses (i.e., in power-off mode) and after the VDDM signal collapses (i.e., in X-track de-leveling mode). In other words, the control circuit 100d provides the GMB control signal to the first VDDM control switches 112-1, causing these switches to remain off during power-off mode and disconnect the SRAM core 30 from the VDDM terminals.

[0068] and Figure 9 The control circuit is the same as 100b. Figure 16The NOR gate 178 in the circuit receives the output of inverter 172 and also the enable signal 101, and outputs the control signal GMB2 to the second VDDM control switch 112-2. For example... Figure 17 As shown in the table, when the power-off signal SD goes high to indicate power-off mode, inverter 140 outputs a low power-off signal SDB. The low SDB signal causes NAND gates 168 and 170 to output high. The high output of NAND gate 170 causes a high GDB signal, which turns off VDD control switch 110 and disconnects the VDD input terminal from SRAM core 30 during power-off mode.

[0069] The high output of NAND gate 168 is output to inverter 172, and the output of inverter 172 is received by inverter 173 to output a high GMB signal to the first VDDM control switch 112-1. The low output of inverter 172 is further provided to NOR gate 178. Before the VDDM signal collapses, enable signal 101 remains low and NOR gate 178 correspondingly outputs a high GMB2 control signal to the second VDDM control switch 112-2, disconnecting the VDDM input terminal from the SRAM core 30 in power-off mode.

[0070] When the VDDM signal collapses (i.e. decreases to 0), the inverter 126 of the enable circuit 124 outputs a high enable signal 101, indicating the X-track reduction mode. The high enable signal 101 received by the NOR gate 178 causes the GMB2 control signal to go low. This turns on the second VDDM control switch 112-2, thereby reducing body-to-source leakage.

[0071] Figure 18 This is a flowchart illustrating an example of a method 200 for controlling a head circuit such as the head circuit 102 discussed above. The method can be implemented by embodiments of the control circuit 100 disclosed herein, and in some embodiments, the control circuit 100 operates to reduce GIDL leakage of the control switches that may occur after a collapse of the input voltage signal (such as VDD and / or VDDM input voltage). Together with Figure 2 Let's refer to each other. Figure 18At operation 210, the method includes receiving a first voltage signal VDD in a first power domain via a first switch 110. At operation 212, a second voltage signal VDDM in a second power domain is received via a second switch 112. In some examples, the first switch 110 or the second switch 112 is turned on based on an AON_SEL_IN signal to provide a voltage level of the desired voltage domain to the SRAM core 30. For example, when the AON_SEL_IN signal is high, the SRAM core 30 is powered by switch 112 (i.e., VDDM), and the control circuit 100 outputs a high GDB control signal and a low GMB signal to the gate terminals of switches 110 and 112, respectively.

[0072] At operation 214, a power-off signal is received, such as... Figures 5-17 The power-off signal SD is shown. The SD signal has a first logic level indicating a power-off mode and a second logic level indicating a memory mode. In memory mode (e.g., the second logic level of the SD signal), control circuitry 100 controls header circuitry 102 to selectively output first and / or second voltage signals VDD, VDDM to the SRAM core 30 to apply the required supply voltage in the VDD or VDDM voltage domain. At operation 216, the first and second switches are turned off in response to the first logic level of the power-off signal SD. In other words, in power-off mode, control header circuitry 102 removes power from the SRAM core 30. Subsequently, at operation 218, in power-off mode, the first switch is turned on in response to a decrease in the first voltage signal. This reduces GIDL leakage of the first switch due to a drop in the first voltage signal.

[0073] Therefore, this disclosure provides a power switching circuit configured to select between power rails in different power domains, such as VDD and VDDM. The control circuitry includes power transistors responsive to corresponding control signals in the VDDM and VDD domains, enabling devices (such as SRAM memories) to operate in two different power domains.

[0074] Therefore, the power switch control circuit outputs a control signal to the head circuit, which controls the power switch to selectively output a power signal. In power-off mode (i.e., to reduce power consumption), the control circuit outputs a gate control signal to turn off the power switch, thereby disconnecting the device from the VDDM and VDD input terminals. To reduce GIDL leakage in power-off mode due to VDD and / or VDDM signal failure, the corresponding switch is turned on in response to VDD or VDDM failure. This reduces body-to-source leakage.

[0075] More specifically, according to some disclosed embodiments, a power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to a control terminal of the first and second switches. The control circuit is configured to turn on the first switch in response to a decrease in the voltage level of the first voltage signal.

[0076] In the power control device described above, the first voltage domain is the VDD domain.

[0077] In the power control device described above, the first voltage domain is the VDDM domain.

[0078] In the aforementioned power control device, the control circuit includes an enable input terminal configured to receive an enable signal, wherein the enable signal is based on the voltage level of a first voltage signal.

[0079] The power control device described above also includes an enable circuit, which has an input terminal and an output terminal configured to receive a first voltage signal in a first voltage domain, wherein the output terminal is connected to output the enable signal to the enable input terminal.

[0080] In the aforementioned power control device, the enabling circuit includes an inverter.

[0081] In the aforementioned power control device, the first switch and the second switch each include a PMOS transistor.

[0082] The power control device described above also includes a plurality of first switches, wherein the plurality of first switches are connected in series, and wherein the control circuit is configured to turn on at least one of the first switches in response to a decrease in the voltage level of the first voltage signal.

[0083] According to a further aspect, a power supply control circuit includes a first voltage domain input terminal and a second voltage domain input terminal. A first transistor has a first source / drain terminal connected to the first voltage domain input terminal and a second source / drain terminal connected to a voltage output terminal. A second transistor has a first source / drain terminal connected to a second voltage domain input terminal and a second source / drain terminal connected to a voltage output terminal. A control circuit has an enable input terminal and an output terminal connected to the gate terminals of the first and second transistors. The enable circuit includes an inverter having an input terminal connected to the first voltage domain input terminal and an output terminal connected to the enable input terminal.

[0084] In the power control circuit described above, the control circuit is configured to turn on the first transistor in response to a decrease in the voltage signal received at the input terminal of the first voltage domain indicated by the enable signal.

[0085] In the power control circuit described above, the control circuit includes a power-off terminal configured to receive a power-off signal, and wherein the control circuit is further configured to turn off the first transistor and the second transistor based on the power-off signal.

[0086] In the power control circuit described above, the voltage level of the first voltage domain is lower than the voltage level of the second voltage domain.

[0087] In the power control circuit described above, the first transistor and the second transistor each include a PMOS transistor.

[0088] The power control circuit described above also includes a third transistor, which has a first source / drain terminal connected to the second source / drain terminal of the first transistor and a second source / drain terminal connected to the voltage output terminal. The control circuit has an output terminal connected to the gate terminal of the third transistor.

[0089] In the power control circuit described above, the control circuit is configured to output a first control signal and a second control signal to the gate terminal of the first transistor and the gate terminal of the second transistor respectively in response to a power-off signal, and to output a third control signal to the gate terminal of the third transistor in response to the power-off signal and an enable signal output by the enable circuit.

[0090] In the power control circuit described above, the voltage output terminal is connected to the SRAM memory array.

[0091] According to another aspect, a power control method includes receiving a first voltage signal in a first power domain via a first switch, and receiving a second voltage signal in a second power domain via a second switch. A power-off signal having a first logic level indicating a power-off mode is received. In response to the first logic level of the power-off signal, the first and second switches are turned off, and then, in the power-off mode, the first switch is turned on in response to a decrease in the first voltage signal.

[0092] In the above power control method, the first power domain is either the VDD power domain or the VDDM power domain.

[0093] In the above power control method, the power-off signal has a second logic level indicating a memory mode, and the method further includes: in response to the second logic level of the power-off signal, turning on one of a first power switch or a second power switch to output a desired first voltage signal or a second voltage signal.

[0094] The power control method described above further includes: generating an enable signal based on the decrease of a first voltage signal in the power-off mode; and turning on a first switch in response to the enable signal.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A power supply control device, comprising: A first switch, wherein a first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain; A second switch, wherein the first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain that is different from the first voltage domain, and the second terminal of the second switch is coupled to the second terminal of the first switch; as well as A control circuit, coupled to the control terminals of the first switch and the second switch, and configured to turn on the first switch in response to a decrease in the voltage level of the first voltage signal, wherein the control circuit includes an enable input terminal configured to receive an enable signal, wherein the enable signal is based on the voltage level of the first voltage signal; An enabling circuit having an input terminal and an output terminal configured to receive a first voltage signal in the first voltage domain, the output terminal being connected to output the enabling signal to the enabling input terminal.

2. The power control device according to claim 1, wherein, The first voltage domain is the VDD domain.

3. The power control device according to claim 1, wherein, The first voltage domain is the VDDM domain.

4. The power control device according to claim 1, wherein, The second terminal of the second switch and the second terminal of the first switch are coupled to the voltage output terminal.

5. The power control device according to claim 4, wherein, The voltage output terminal is coupled to the SRAM memory array.

6. The power control device according to claim 1, wherein, The enabling circuit includes an inverter.

7. The power control device according to claim 1, wherein, The first switch and the second switch each include a PMOS transistor.

8. The power control device according to claim 1, further comprising a plurality of first switches including the first switch, wherein, The plurality of first switches are connected in series, and the control circuit is configured to turn on at least one of the first switches in response to a decrease in the voltage level of the first voltage signal.

9. A power supply control circuit, comprising: First voltage domain input terminal; Second voltage domain input terminal; The first transistor has a first source / drain terminal connected to the input terminal of the first voltage domain and a second source / drain terminal connected to the voltage output terminal; The second transistor has a first source / drain terminal connected to the input terminal of the second voltage domain and a second source / drain terminal connected to the voltage output terminal; The control circuit has an enable input terminal and an output terminal connected to the gate terminal of the first transistor and the gate terminal of the second transistor. as well as An enabling circuit includes an inverter having an input terminal connected to the first voltage domain input terminal and an output terminal connected to the enable input terminal.

10. The power control circuit according to claim 9, wherein, The control circuit is configured to turn on the first transistor in response to a decrease in the voltage signal received at the first voltage domain input terminal indicated by the enable signal.

11. The power control circuit according to claim 9, wherein, The control circuit includes a power-off terminal configured to receive a power-off signal, and wherein the control circuit is further configured to turn off the first transistor and the second transistor based on the power-off signal.

12. The power control circuit according to claim 9, wherein, The voltage level in the first voltage domain is lower than the voltage level in the second voltage domain.

13. The power control circuit according to claim 9, wherein, The first transistor and the second transistor each include a PMOS transistor.

14. The power control circuit of claim 9, further comprising a third transistor having a first source / drain terminal connected to the second source / drain terminal of the first transistor and a second source / drain terminal connected to the voltage output terminal, wherein, The control circuit has an output terminal connected to the gate terminal of the third transistor.

15. The power control circuit according to claim 14, wherein, The control circuit is configured to output a first control signal and a second control signal to the gate terminal of the first transistor and the gate terminal of the second transistor respectively in response to a power-off signal, and to output a third control signal to the gate terminal of the third transistor in response to the power-off signal and an enable signal output by the enable circuit.

16. The power control circuit according to claim 9, wherein, The voltage output terminal is connected to the static random access memory array.

17. A power supply control method, comprising: The first voltage signal in the first power domain is received by the first switch; The second voltage signal in the second power domain is received by the second switch; Receive a power-off signal, the power-off signal having a first logic level indicating a power-off mode; In response to the first logic level of the power-off signal, the first switch and the second switch are turned off; And afterwards In the power-off mode, the first switch is turned on in response to a decrease in the first voltage signal.

18. The power control method according to claim 17, wherein, The first power domain is either a VDD power domain or a VDDM power domain.

19. The power control method according to claim 17, wherein, The power-off signal has a second logic level indicating a memory mode, and the method further includes: turning on one of the first power switch or the second power switch in response to the second logic level of the power-off signal to output the desired first voltage signal or the second voltage signal.

20. The power control method according to claim 17, further comprising: In the power-off mode, an enable signal is generated based on the decrease of the first voltage signal; as well as The first switch is turned on in response to the enable signal.

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