SGT MOS Device and Its Fabrication Method

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an SGT MOS device and a manufacturing method thereof. First-conductivity-type impurities are implanted by plasma to form a first-conductivity-type doped channel region on an upper layer of an epitaxial layer on both sides of a deep trench; second-conductivity-type impurities are implanted by plasma to form a second-conductivity-type doped source region on a surface layer of the epitaxial layer on the first-conductivity-type doped channel region; a contact hole is formed so that the contact hole extends to the first-conductivity-type doped channel region in sequence through the second-conductivity-type doped source region; amorphous element ions are implanted to form an amorphous doped region in the first-conductivity-type doped channel region at the outer periphery of the bottom end of the contact hole; and the first-conductivity-type impurities are implanted into the bottom end of the contact hole to form a first-conductivity-type doped contact region in the amorphous doped region at the outer periphery of the bottom end of the contact hole; wherein the first-conductivity-type doped contact region and the first-conductivity-type doped channel region are separated by the amorphous doped region.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an SGT MOS device and its fabrication method. Background Technology

[0002] With the rise of fast charging for mobile phones and brushless motors, the demand for medium-voltage MOSFETs is increasing, and medium-voltage power devices are booming. SGT (Shiled Gate Trench) MOSFETs, as a representative of medium-voltage MOSFETs, are widely used as switching devices in power management systems and are core power control components.

[0003] An SGT MOEFET includes a gate structure formed in an epitaxial layer and active regions located on both sides of the gate structure. The gate structure includes a shielded polysilicon structure and a polysilicon gate structure located in a deep trench, wherein the shielded polysilicon structure is located at the lower part of the deep trench, and the polysilicon gate structure is located at the upper part of the deep trench. The shielded polysilicon structure, the polysilicon gate structure, and the deep trench are isolated from each other. A channel region is formed on the top layer of the active region, and a source region is formed on the surface layer of the epitaxial layer located on the channel region. The source region is brought out through contact holes, typically with a heavily doped contact region formed around the bottom end of the contact holes used to bring out the source region, which contacts the channel region.

[0004] The channel region determines the threshold voltage of the device. In related technologies, the heavily doped contact region and the channel region are usually of the same type, and the doping concentration of the heavily doped contact region is two orders of magnitude higher than that of the channel region. During the subsequent annealing process, the heavily doped contact region will undergo lateral diffusion, which will affect the doping concentration of the channel region, thereby increasing and dispersing the threshold voltage parameter. For small-sized semiconductor devices, the influence of the contact region formed by contact hole injection will be significantly increased, which will be detrimental to the development of small-sized MOS devices. Summary of the Invention

[0005] This application provides an SGT MOS device and its fabrication method, which can solve the problem in related technologies that lateral diffusion occurs in the heavily doped contact region, thereby affecting the doping concentration in the channel region and causing the threshold voltage parameter to increase and become discrete.

[0006] To address the technical problems described in the background art, a first aspect of this application provides a method for manufacturing an SGT MOS device, the method comprising the following steps:

[0007] A semiconductor substrate is provided, the semiconductor substrate including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, a deep trench extending downward from the upper surface of the epitaxial layer, a gate polysilicon structure located above the deep trench, and the gate polysilicon structure and the deep trench being isolated from each other;

[0008] By injecting impurities of the first conductivity type with plasma, a first conductivity type doped channel region is formed on the epitaxial layer on both sides of the deep trench;

[0009] By injecting a second type of conductivity impurity with plasma, a second type of conductivity doped source region is formed on the surface of the epitaxial layer on the first type of conductivity doped channel region.

[0010] A contact hole is formed, which extends sequentially through the second conductivity type doped source region to the first conductivity type doped channel region;

[0011] Amorphous element ion implantation is performed to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom end of the contact hole;

[0012] A first type of conductivity impurity is injected into the bottom end of the contact hole, thereby forming a first type of conductivity doped contact region in the amorphous doped region on the outer periphery of the bottom end of the contact hole; wherein the amorphous doped region is spaced between the first type of conductivity doped contact region and the first type of conductivity doped channel region.

[0013] Optionally, the step of performing amorphous element ion implantation to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom end of the contact hole includes:

[0014] With an injection energy of 40 KeV, at 1x10 15 atoms / cm 2 At a certain implantation dose, amorphous element ions are vertically implanted, thereby forming an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole.

[0015] Optionally, the amorphous element ion implantation is performed such that the amorphous doped region is formed in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole, and the amorphous element ion is carbon ion.

[0016] Optionally, the step of injecting a first conductivity type impurity into the bottom end of the contact hole to form a first conductivity type doped contact region in the amorphous doped region on the outer periphery of the bottom end of the contact hole includes:

[0017] First, with an injection energy of 25 KeV, at 1x10 15 atoms / cm 2 At the injection dose, boron fluoride ions were vertically injected;

[0018] Then, with an injection energy of 30 KeV, at 8.7 x 10 13 atoms / cm 2At a specific implantation dose, boron ions are vertically implanted to form a first conductivity type doped contact region in the amorphous doped region on the outer periphery of the bottom of the contact hole.

[0019] To address the technical problems described in the background art, a second aspect of this application provides an SGT MOS device structure, the SGT structure comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, and further comprising:

[0020] Deep trenches extending downward from the upper surface of the epitaxial layer;

[0021] A gate polysilicon structure is located above the deep trench, and the gate polysilicon structure and the deep trench are isolated from each other;

[0022] A first conductivity type doped channel region is formed on the upper layer of the epitaxial layer on both sides of the deep trench;

[0023] The second conductivity type doped source region is formed on the epitaxial layer surface on the first conductivity type doped channel region.

[0024] A contact hole that extends through the second conductivity type doped source region into the first conductivity type doped channel region;

[0025] A first conductivity type doped contact region is formed in a first conductivity type doped channel region around the bottom end of the contact hole;

[0026] An amorphous doped region is formed in the first conductivity type doped channel region surrounding the first conductivity type doped contact region.

[0027] Optionally, the impurities in the amorphous doped region are carbon ions.

[0028] Optionally, the amorphous doped region is obtained by implantation at an energy of 40 KeV and at a density of 1 x 10⁻⁶ kJ / m². 15 atoms / cm 2 Amorphous element ion doping is performed at specific dosages to form the amorphous material.

[0029] The technical solution of this application has at least the following advantages: The SGT MOS device manufacturing method and SGT MOS device provided in this embodiment can form an amorphous doped region between the outer periphery of the first conductivity type doped contact region and the first conductivity type doped channel region. The amorphous doped region isolates the first conductivity type doped contact region from the first conductivity type doped channel region, avoiding the diffusion of impurities in the first conductivity type doped contact region from affecting the concentration of the first conductivity type doped channel region, thereby avoiding affecting the threshold voltage of the device. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 A flowchart of the SGT MOS device manufacturing method in one embodiment of this application is shown;

[0032] Figure 2 A schematic diagram of the semiconductor structure in step S1 is shown;

[0033] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S4 is shown;

[0034] Figure 4 A cross-sectional view of an SGT MOS device structure provided in an embodiment of this application is shown. Detailed Implementation

[0035] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0038] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0039] Reference Figure 1 It shows a flowchart of the SGT MOS device manufacturing method in one embodiment of this application, from Figure 1 As can be seen from this, the manufacturing method of this SGT MOS device includes the following steps:

[0040] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, a deep trench extending downward from the upper surface of the epitaxial layer, a shielding polysilicon structure located at the lower part of the deep trench, a gate polysilicon structure located at the upper part of the deep trench, and the shielding polysilicon structure, the gate polysilicon structure and the deep trench being isolated from each other.

[0041] Reference Figure 2 It shows a schematic diagram of the semiconductor structure in step S1, from Figure 2 As can be seen, the semiconductor substrate includes a semiconductor substrate 100 and an epitaxial layer 200 formed on the semiconductor substrate 100. A deep trench 300 extends downward from the upper surface of the epitaxial layer 200. A gate polysilicon structure 320 is located above the deep trench 300, and the gate polysilicon structure 320 and the deep trench 300 are isolated from each other by an oxide layer 330. A shielding gate polysilicon 310, which is isolated from both the deep trench 300 and the gate polysilicon structure 320, can also be formed at the lower part of the deep trench 300.

[0042] Step S2: By plasma injection of impurities of the first conductivity type, a first conductivity type doped channel region is formed on the epitaxial layer on both sides of the deep trench.

[0043] Optionally, the first conductivity type impurity can be a P-type impurity.

[0044] Step S3: By plasma injection of a second type of impurity, a second type of doped source region is formed on the surface of the epitaxial layer on the first type of doped channel region.

[0045] Optionally, the second conductivity type impurity can be an N-type impurity.

[0046] Step S4: Create a contact hole, such that the contact hole extends sequentially through the second conductivity type doped source region to the first conductivity type doped channel region.

[0047] Reference Figure 3 It shows a cross-sectional view of the device after step S4. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type. From Figure 3 As can be seen, a P-type doped channel region 410 is formed on the epitaxial layer 200 on both sides of the deep trench 300, and an N-type doped source region 420 is formed on the surface of the epitaxial layer 200 on the P-type doped channel region 410. The formed contact hole 340 extends through the N-type doped source region 420 into the P-type doped channel region 410.

[0048] Step S5: Perform amorphous element ion implantation to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom end of the contact hole.

[0049] Specifically, during amorphous element ion implantation, carbon ions can be used to implant carbon ions, forming a carbon-doped region in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole. This first conductivity type can be P-type.

[0050] For example, during step S5, an injection energy of 40 KeV can be used at 1x10 15 atoms / cm 2 At a certain implantation dose, carbon ions are vertically implanted, resulting in the formation of an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole.

[0051] Step S6: Inject a first type of conductivity impurity into the bottom of the contact hole, thereby forming a first type of conductivity doped contact region in the amorphous doped region on the outer periphery of the bottom of the contact hole; wherein the amorphous doped region separates the first type of conductivity doped contact region from the first type of conductivity doped channel region.

[0052] For example, when performing step S6, an injection energy of 25 KeV can be used first at 1x10 15 atoms / cm 2 At the specified injection dose, boron fluoride ions were vertically implanted; then, with an injection energy of 30 keV, at 8.7 x 10⁻⁶ kilometres per cubic centimeter (kcal / kg), the ion was injected vertically. 13 atoms / cm 2 At a specific implantation dose, boron ions are vertically implanted to form a first conductivity type doped contact region in the amorphous doped region on the outer periphery of the bottom of the contact hole.

[0053] Reference Figure 4 It shows a schematic diagram of the cross-sectional structure of the device after step S6. In this embodiment, the first conductivity type can be P-type, the second conductivity type can be N-type, and the amorphous element ion can be carbon element ion.

[0054] from Figure 4 As can be seen from this, after step S6 is completed, in Figure 3 Based on this, a carbon-doped region 350 is formed in the P-type doped channel region 410 on the outer periphery of the bottom end of the contact hole 340, and a P-type doped contact region 430 is formed in the carbon-doped region 350 on the outer periphery of the bottom end of the contact hole 340; wherein the carbon-doped region 350 is spaced between the P-type doped contact region 430 and the P-type doped channel region 410.

[0055] This application also provides an SGT MOS device structure, which is composed of... Figure 1 The SGT MOS device is manufactured using the method shown.

[0056] Reference Figure 4 It also shows a cross-sectional view of an SGT MOS device structure provided in one embodiment of this application. In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type.

[0057] from Figure 4 As can be seen from the diagram, the SGT MOS device structure includes a semiconductor substrate 100 and an epitaxial layer 200 formed on the semiconductor substrate 100, and further includes:

[0058] A deep trench 300 extends downward from the upper surface of the epitaxial layer 200.

[0059] A gate polysilicon structure 320 is located above the deep trench 300, and the gate polysilicon structure 320 and the deep trench 300 are isolated from each other.

[0060] P-type doped channel region 410 is formed on the upper layer of epitaxial layer 200 on both sides of deep trench 300.

[0061] N-type doped source region 420 is formed on the surface of epitaxial layer 200 on the P-type doped channel region 410.

[0062] Contact hole 340 extends through the N-type doped source region 420 into the P-type doped channel region.

[0063] A P-type doped contact region 430 is formed in the P-type doped channel region 410 surrounding the bottom end of the contact hole 340.

[0064] A carbon-doped region 350 is formed in the P-type doped channel region 410 surrounding the P-type doped contact region 430.

[0065] The SGT MOS device manufacturing method and SGT MOS device provided in this embodiment can form an amorphous doped region between the outer periphery of the first conductivity type doped contact region and the first conductivity type doped channel region. The amorphous doped region isolates the first conductivity type doped contact region from the first conductivity type doped channel region, avoiding the diffusion of impurities in the first conductivity type doped contact region from affecting the concentration of the first conductivity type doped channel region, thereby avoiding affecting the threshold voltage of the device.

[0066] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing an SGT MOS device, characterized in that, The SGT MOS device manufacturing method includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, a deep trench extending downward from the upper surface of the epitaxial layer, a gate polysilicon structure located above the deep trench, and the gate polysilicon structure and the deep trench being isolated from each other; By injecting impurities of the first conductivity type with plasma, a first conductivity type doped channel region is formed on the epitaxial layer on both sides of the deep trench; By injecting a second type of conductivity impurity with plasma, a second type of conductivity doped source region is formed on the surface of the epitaxial layer on the first type of conductivity doped channel region. A contact hole is formed, which extends sequentially through the second conductivity type doped source region to the first conductivity type doped channel region; Amorphous element ion implantation is performed to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom end of the contact hole; A first type of conductivity impurity is injected into the bottom end of the contact hole, thereby forming a first type of conductivity doped contact region in the amorphous doped region on the outer periphery of the bottom end of the contact hole; wherein the amorphous doped region is spaced between the first type of conductivity doped contact region and the first type of conductivity doped channel region.

2. The method for manufacturing an SGT MOS device as described in claim 1, characterized in that, The step of performing amorphous element ion implantation to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom end of the contact hole includes: With an injection energy of 40 KeV, at 1x10 15 atoms / cm 2 At a certain implantation dose, amorphous element ions are vertically implanted, thereby forming an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole.

3. The method for manufacturing an SGT MOS device as described in claim 2, characterized in that, The amorphous element ion implantation is performed to form an amorphous doped region in the first conductivity type doped channel region on the outer periphery of the bottom of the contact hole, wherein the amorphous element ion is a carbon element ion.

4. The method for manufacturing an SGT MOS device as described in claim 1 or 2, characterized in that, The step of injecting a first conductivity type impurity into the bottom end of the contact hole to form a first conductivity type doped contact region in the amorphous doped region on the outer periphery of the bottom end of the contact hole includes: First, with an injection energy of 25 KeV, at 1x10 15 atoms / cm 2 At the injection dose, boron fluoride ions were vertically injected; Then, with an injection energy of 30 KeV, at 8.7 x 10 13 atoms / cm 2 At a specific implantation dose, boron ions are vertically implanted to form a first conductivity type doped contact region in the amorphous doped region on the outer periphery of the bottom of the contact hole.

5. An SGT MOS device structure, characterized in that, The SGT structure includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, and further includes: Deep trenches extending downward from the upper surface of the epitaxial layer; A gate polysilicon structure is located above the deep trench, and the gate polysilicon structure and the deep trench are isolated from each other; A first conductivity type doped channel region is formed on the upper layer of the epitaxial layer on both sides of the deep trench; The second conductivity type doped source region is formed on the epitaxial layer surface on the first conductivity type doped channel region. A contact hole that extends through the second conductivity type doped source region into the first conductivity type doped channel region; A first conductivity type doped contact region is formed in a first conductivity type doped channel region around the bottom end of the contact hole; An amorphous doped region is formed in the first conductivity type doped channel region surrounding the first conductivity type doped contact region.

6. The SGT MOS device as described in claim 1, characterized in that, The impurities in the amorphous doped region are carbon ions.

7. The SGT MOS device as described in claim 6, characterized in that, The amorphous doped region was created by injecting an energy of 40 KeV at a density of 1 x 10⁻⁶ kJ / L. 15 atoms / cm 2 Amorphous element ion doping is performed at specific dosages to form the amorphous material.

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