Semiconductor substrate, transistor and method of manufacturing the same

Abstract

The application discloses a kind of semiconductor substrate, transistor and preparation method thereof, belong to semiconductor device technical field, including the following steps: respectively preparing strain SOI substrate and strain GOI substrate;The strain SOI substrate and the strain GOI substrate are bonded connection;Remove substrate and buried oxygen layer in the strain SOI substrate or remove substrate and buried oxygen layer in the strain GOI substrate, obtain semiconductor substrate.Formation method of the application, avoid the dislocation defect generated between Ge and Si interface in growth process, good interface state between Si channel and Ge channel, avoid producing interface trap in device conduction, avoid being limited to the pinning effect of interface state on Fermi level.Good surface roughness and uniformity may improve carrier transport efficiency, improve mobility.And the preparation of double substrate can be realized simultaneously, save cost, simple operation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a semiconductor substrate, a transistor, and a method for fabricating the same. Background Technology

[0002] Silicon germanium on insulator (SGOI) is not only a good substrate for strained silicon, a novel high-mobility channel material, but it is also a highly promising high-mobility substrate material. SGOI combines silicon on insulator (SOI) structure to fabricate fully depleted, low-power, small-size metal-oxide-semiconductor field-effect transistor devices. Due to its high Ge content, SiGe itself has the advantage of high carrier mobility, and the material itself has considerable development prospects.

[0003] The difficulty in traditional SGOI substrate fabrication lies in the defects at the Ge-Si interface. Since Ge's lattice constant is 4.2% larger than Si's, this mismatch in lattice constants leads to a large number of dislocation defects at the Si-Ge interface. This results in poor device characterization performance and, in severe cases, can even affect the performance of the final transistor device. Therefore, how to eliminate or avoid a large number of dislocation defects at the Si-Ge interface and obtain a well-strained SGOI substrate has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a semiconductor substrate, a transistor and a method for fabricating the same, thereby avoiding misalignment defects between the Ge and Si interfaces during the growth process and obtaining a semiconductor substrate with a good Si-Ge interface.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a semiconductor substrate, comprising the following steps: An SOI substrate is provided, the SOI substrate including a substrate, a buried oxide layer and a top silicon layer, a first buffer layer is deposited on the top silicon layer, a silicon nitride layer is deposited on the first buffer layer, a first heat treatment is performed, and then the first buffer layer and the silicon nitride layer are removed to obtain a strained SOI substrate. A GOI substrate is provided, the GOI substrate including a substrate, a buried oxide layer and a top germanium layer, a second buffer layer is deposited on the top germanium layer, a silicon nitride layer is deposited on the second buffer layer, a second heat treatment is performed, and then the second buffer layer and the silicon nitride layer are removed to obtain a strained GOI substrate. The strained SOI substrate and the strained GOI substrate are bonded together; The substrate and buried oxide layer in the strained SOI substrate or the substrate and buried oxide layer in the strained GOI substrate are removed to obtain a semiconductor substrate.

[0006] In a preferred embodiment of the present invention, the substrate is a silicon substrate.

[0007] In a preferred embodiment of the present invention, the first buffer layer includes a SiGe layer and a PEOX layer; and / or The second buffer layer includes a SiGe layer and a PEOX layer.

[0008] In a preferred embodiment of the present invention, the thickness of the SiGe layer is 50~200nm, the thickness of the PEOX layer is 10~50nm, and the thickness of the silicon nitride layer is 100~500nm.

[0009] As a preferred embodiment of the present invention, the temperature of the first heat treatment is 900~950℃; and / or The temperature of the second heat treatment is 900~950℃.

[0010] In a preferred embodiment of the present invention, the bonding connection is a pressure bonding connection, and the bonding process conditions are: bonding force of 10~60KN, bonding temperature of 200~500℃, and bonding time of 0.5~8 hours.

[0011] As a preferred embodiment of the present invention, the strained SOI substrate includes a substrate, a buried oxide layer, and a strained silicon layer; and / or The GOI substrate includes a substrate, a buried oxide layer, and a strained germanium layer.

[0012] In a second aspect of the present invention, the present invention provides a semiconductor substrate prepared by the method described above, comprising a substrate, a buried oxide layer, a strained silicon layer and a strained germanium layer; The buried oxide layer is located above the substrate, the strained silicon layer and the strained germanium layer are located above the buried oxide layer, and the strained silicon layer is located above or below the strained germanium layer.

[0013] In a third aspect, the present invention provides a transistor comprising: Strained silicon layer; A strained germanium layer; the strained silicon layer is located above or below the strained germanium layer; A buried oxide layer is located below the strained silicon layer or the strained germanium layer; Substrate, located below the buried oxide layer; The source / drain is located above the buried oxide layer and on both sides of the strained silicon layer and the strained germanium layer.

[0014] As a preferred embodiment of the present invention, a back gate is also included, which is located below the substrate.

[0015] The beneficial effects of the present invention are as follows: (1) In this application, a first buffer layer and a silicon nitride layer are first deposited on an SOI substrate, and then heat-treated at a high temperature of 900~950°C. The polycrystalline silicon on the silicon nitride layer will have the memory stress conducted downward along the vertical direction until it is conducted to the top silicon layer, making it a strained silicon layer 300; a second buffer layer and a silicon nitride layer are first deposited on a GOI substrate, and then heat-treated at a high temperature of 900~950°C. The polycrystalline silicon on the silicon nitride layer will have the memory stress conducted downward along the vertical direction until it is conducted to the top germanium layer, making it a strained germanium layer; (2) The strained SOI substrate and the strained GOI substrate are bonded together, and the connection When the strained germanium layer and the strained silicon layer are in contact, the strained germanium layer and the strained silicon layer are bonded together to avoid the misalignment defects generated between the Ge and Si interfaces during the growth process; (3) The two semiconductor substrates formed in this application are s-Si-sGOI substrate and SGOI substrate, wherein the strained germanium layer of the s-Si-sGOI substrate is below the strained silicon layer, and the strained germanium layer of the SGOI substrate is above the strained silicon layer. When the strained silicon layer is below, the strained germanium layer acts as the main channel, and the device has a high carrier mobility. When the strained germanium layer is below, the strained silicon layer acts as the main channel, and the device can obtain a high switching ratio current and an ideal subthreshold swing. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the SOI substrate structure of the present invention.

[0017] Figure 2 This is a schematic diagram of the structure after the first buffer layer and silicon nitride layer are deposited on the SOI substrate according to the present invention.

[0018] Figure 3 This is a schematic diagram of the strained SOI substrate structure of the present invention.

[0019] Figure 4 This is a schematic diagram of the GOI substrate structure of the present invention.

[0020] Figure 5 This is a schematic diagram of the structure after depositing a second buffer layer and a silicon nitride layer on a GOI substrate according to the present invention.

[0021] Figure 6 This is a schematic diagram of the strained GOI substrate structure of the present invention.

[0022] Figure 7 This is a schematic diagram of the bonding connection between the strained SOI substrate and the strained GOI substrate of the present invention.

[0023] Figure 8This is a schematic diagram of the s-Si-sGOI substrate structure of the present invention.

[0024] Figure 9 This is a schematic diagram of the SGOI substrate structure.

[0025] Figure 10 This is a schematic diagram of a transistor structure containing an s-Si-sGOI substrate provided in one embodiment.

[0026] Figure 11 This is a schematic diagram of another transistor structure containing an s-Si-sGOI substrate.

[0027] Figure 12 This is a schematic diagram of a transistor containing an SGOI substrate.

[0028] Figure 13 This is a schematic diagram of another transistor structure containing an SGOI substrate.

[0029] The markings in the figure are as follows: 10, silicon substrate; 20, buried oxide layer; 30, top silicon layer; 300, strained silicon layer; 40a, first buffer layer; 40b, second buffer layer; 410, SiGe layer; 420, PEOX layer; 50, silicon nitride layer; 60, top germanium layer; 600, strained germanium layer; 70, source; 80, drain; 90, back gate. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In this application, the technical features described in an open-ended manner include both closed technical solutions consisting of the listed features and open technical solutions that include the listed features.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0033] In this application, numerical ranges are referred to as continuous unless otherwise specified, and include the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.

[0034] This application provides a method for preparing a semiconductor substrate, comprising the following steps: (1) Provide an SOI substrate, see reference Figure 1 As shown. In this embodiment of the application, the SOI substrate includes, from bottom to top, a silicon substrate 10, a buried oxide layer 20, and a top silicon layer 30.

[0035] like Figure 2 As shown, a first buffer layer 40a is deposited on the top silicon 30, and a silicon nitride layer 50 is deposited on the first buffer layer 40a. The substrate is then heat-treated at 900~950℃, and then the first buffer layer 40a and the silicon nitride layer 50 are removed to obtain a strained SOI substrate. like Figure 3 As shown, the obtained strained SOI substrate includes a silicon substrate 10, a buried oxide layer 20, and a strained silicon layer 300 from bottom to top.

[0036] First, a first buffer layer 40a and a silicon nitride layer 50 are deposited on an SOI substrate. Then, the substrate is heat-treated at a high temperature of 900~950℃. The polycrystalline silicon on the silicon nitride layer 50 will have the memory stress conducted downward along the vertical direction until it is conducted to the top silicon layer 30, making it a strained silicon layer 300.

[0037] (2) Provide a GOI substrate, please refer to Figure 4 In this embodiment of the application, the GOI substrate includes a silicon substrate 10, a buried oxide layer 20 and a top germanium layer 60 from bottom to top.

[0038] like Figure 5 As shown, a second buffer layer 40b is deposited on the top germanium 60, and a silicon nitride layer 50 is deposited on the second buffer layer 40b. The substrate is then heat-treated at 900~950℃, and then the second buffer layer 40b and the silicon nitride layer 50 are removed to obtain a strained GOI substrate. like Figure 6 As shown, the obtained strained GOI substrate includes a silicon substrate 10, a buried oxide layer 20, and a strained germanium layer 600 from bottom to top.

[0039] First, a second buffer layer 40b and a silicon nitride layer 50 are deposited on the GOI substrate. Then, the substrate is heat-treated at a high temperature of 900~950℃. The polycrystalline silicon on the silicon nitride layer 50 will have the memory stress conducted downward along the vertical direction until it is conducted to the top germanium layer 30, making it a strained germanium layer 600.

[0040] (3) Bond the strained SOI substrate and the strained GOI substrate together, making the strained germanium layer 600 and the strained silicon layer 300 in contact during bonding, such as... Figure 7 As shown; in this way, bonding the strained germanium layer 600 and the strained silicon layer 300 together avoids the misalignment defects generated between the Ge and Si interfaces during the growth process; (4) Remove the substrate 10 and buried oxide layer 20 from the SOI substrate (i.e., remove) Figure 7 The substrate 10 and buried oxide layer 20 below the medium-strained silicon layer 300 are used to obtain a semiconductor substrate (hereinafter referred to as s-Si-sGOI substrate), such as Figure 8 As shown, the s-Si-sGOI substrate includes, from bottom to top, a silicon substrate 10, a buried oxide layer 20, a strained germanium layer 600, and a strained silicon layer 300.

[0041] As one possible implementation of forming a semiconductor substrate, step (4) can be replaced by: removing the substrate 10 and the buried oxide layer 20 from the GOI substrate (i.e., removing...). Figure 7 A semiconductor substrate (hereinafter referred to as SGOI substrate) is obtained by placing a substrate 10 and a buried oxide layer 20 above a medium-strained germanium layer 300, as shown in the figure. Figure 9As shown, the s-Si-sGOI substrate includes, from bottom to top, a silicon substrate 10, a buried oxide layer 20, a strained silicon layer 300, and a variable germanium layer 600.

[0042] In this embodiment, the two semiconductor substrates formed are an s-Si-sGOI substrate and an SGOI substrate. In the s-Si-sGOI substrate, the strained germanium layer 600 is below the strained silicon layer 300, and in the SGOI substrate, the strained germanium layer 600 is above the strained silicon layer 300. When the strained silicon layer 300 is below, the strained germanium layer 600 acts as the main channel, characterized by high carrier mobility. When the strained germanium layer 600 is below, the strained silicon layer 300 acts as the main channel, characterized by high on / off ratio current and ideal subthreshold swing.

[0043] The above-described formation method avoids dislocation defects at the Ge-Si interface during growth. The favorable interface states between the Si and Ge channels prevent interface traps during device conduction, avoiding the pinning effect on the Fermi level. Excellent surface roughness and uniformity may improve carrier transport efficiency and mobility. Furthermore, it allows for simultaneous fabrication of dual substrates, saving costs and simplifying the operation.

[0044] The buried oxide layer 20 is commonly referred to as the BOX (Buried Oxide) layer. The buried oxide layer 20 separates the silicon substrate 10 from the top silicon 30 and the top germanium 60, respectively, so as to provide dielectric isolation.

[0045] In some alternative implementations, in Figure 1 In the SOI substrate, there are no particular limitations on the thickness of the silicon substrate 10, the buried oxide layer 20 and the top germanium layer 60. Those skilled in the art know how to set their thickness. For example, the thickness of the silicon substrate 10 can be 5~100nm, the thickness of the buried oxide layer 20 can be 5~100nm, and the thickness of the top germanium layer 60 can be 5~50nm.

[0046] In some specific implementations, in step (1), the temperature of the first heat treatment is 900°C and the time is 1 min.

[0047] In some specific embodiments, in step (1), the method of removing the first buffer layer 40a and the silicon nitride layer 50 can be by grinding or dry etching or wet etching.

[0048] In some specific embodiments, in step (1), the deposition of the first buffer layer 40a and the deposition of the silicon nitride layer 50 can be carried out by chemical vapor deposition, molecular beam epitaxy, etc.; wherein the setting of the first buffer layer 40a prevents the top silicon 30 from directly contacting the surface of the silicon nitride film 50, and conducts stress through indirect stress conduction, so that the interface of the surface of the top silicon 30 will not produce misalignment defects, and retains an excellent interface characterization structure.

[0049] In some specific implementations, in step (2), the temperature of the second heat treatment is 900°C and the time is 1 min.

[0050] In some specific embodiments, in step (2), the method for removing the second buffer layer 40b and the silicon nitride layer 50 can be by grinding or dry etching or wet etching.

[0051] In some specific embodiments, in step (2), the deposition of the second buffer layer 40b and the deposition of the silicon nitride layer 50 can be carried out by chemical vapor deposition, molecular beam epitaxy, etc.; wherein the setting of the second buffer layer 40b prevents the top germanium 60 from directly contacting the surface of the silicon nitride film 50, and conducts stress through indirect stress conduction, so that the interface of the surface of the top germanium 60 will not produce misalignment defects, and retains an excellent interface characterization structure.

[0052] In the embodiments of this application, such as Figure 2 As shown, the first buffer layer 40a includes a SiGe layer 410 and a PEOX layer 420. The SiGe layer 410 is in contact with the top silicon layer 30, and the PEOX layer 420 is in contact with the silicon nitride layer 50. In this way, the interface of the surface of the top silicon layer 30 will not produce dislocation defects, and the excellent interface characterization structure is preserved. The SiGe layer 410, as a relaxation buffer layer, can effectively protect the underlying top silicon layer 300 from damage and allow stress to be transmitted to the top silicon layer 300. It is precisely because of the doping of Ge element that strain can be generated on the Si layer. The PEOX layer 420, as a buffer layer, can also protect the underlying SiGe layer 410. The SiGe layer 410 is in direct contact with the silicon nitride layer 500. When the silicon nitride layer 500 releases stress, it will cause serious damage to the crystal of the SiGe layer 410, causing it to lose its buffering effect. Therefore, the PEOX layer 420 is needed for buffering.

[0053] In the embodiments of this application, such as Figure 5 As shown, the second buffer layer 40b includes a SiGe layer 410 and a PEOX layer 420, wherein the SiGe layer 410 is in contact with the top germanium layer 30 and the PEOX layer 420 is in contact with the silicon nitride layer 50. In this way, the interface of the surface of the top germanium layer 30 will not produce misalignment defects, and the excellent interface characterization structure is preserved.

[0054] In some specific embodiments, both the SiGe layer 410 and the PEOX layer 420 are deposited sequentially on the top silicon layer 30. The deposition methods can include chemical vapor deposition, molecular beam epitaxy, etc.

[0055] In some specific embodiments, the thickness of the SiGe layer 410 is 50~200nm, the thickness of the PEOX layer 420 is 10~50nm, and the thickness of the silicon nitride layer 50 is 100~500nm. Within this thickness range, the stress conduction effect is good, and the interface between the top silicon 30 and the top germanium 60 will not produce misalignment defects, thus retaining an excellent interface characterization structure.

[0056] In some specific embodiments, the thickness of the preferred SiGe layer 410 is 50~150nm, the thickness of the PEOX layer 420 is 10~40nm, and the thickness of the silicon nitride layer 50 is 100~400nm.

[0057] In some specific embodiments, the thickness of the SiGe layer 410 is preferably 120 nm, the thickness of the PEOX layer 420 is 20 nm, and the thickness of the silicon nitride layer 50 is 200 nm.

[0058] In some specific embodiments, the composition of Si and Ge in the SiGe layer is adjustable, wherein the Ge composition is preferably 20-40%. In this embodiment, Si is used as the base material. 0.7 Ge 0.3 For example.

[0059] In some specific implementations, the bonding method between strained SOI substrates and strained GOI substrates is pressure bonding, which can be performed directly using a pressure bonding machine. During the bonding process, bonding process conditions such as bonding force, bonding temperature, and bonding time can be set according to actual needs. For example, the bonding process conditions can be set as follows: bonding force of 10~60KN, bonding temperature of 200~500℃, and bonding time of 0.5~8 hours. Pressure bonding avoids misalignment defects that occur at the Ge-Si interface during growth.

[0060] In some specific embodiments, the methods for removing the substrate 10 and buried oxide layer 20 in the SOI substrate and the methods for removing the substrate 10 and buried oxide layer 20 in the GOI substrate can be by grinding or dry etching or wet etching (TMAH).

[0061] In some specific embodiments, wet etching is preferred. The etching solution used in wet etching can be tetramethylammonium hydroxide (TMAH). During etching, the tetramethylammonium hydroxide can be diluted with deionized water at a ratio of 2.35%. The etching temperature can be 45~90℃; the etching time can be 0.5 hours~6 hours.

[0062] In one embodiment, the present invention provides a transistor, the structural diagram of which is shown below. Figure 10 As shown, it is fabricated using an s-Si-sGOI substrate and includes: a strained silicon layer 300, a strained germanium layer 600, a buried oxide layer 20, a buried oxide layer 10, a source electrode 70, and a drain electrode 80. The strained silicon layer 300 is located above the strained germanium layer 600, the buried oxide layer 20 is located below the strained germanium layer 300, and the silicon substrate 20 is located below the buried oxide layer. The source / drain is located above the buried oxide layer 20 and on both sides of the strained silicon layer 300 and the strained germanium layer 600.

[0063] The source / drain is formed by etching both sides of the strained silicon layer 600 and the strained germanium layer 300.

[0064] Among them, the strained silicon layer 300 and the strained germanium layer 600 serve as gates.

[0065] In some alternative implementations, a back gate is also included, such as Figure 11 As shown, it is located below the silicon substrate.

[0066] In another embodiment, the present invention provides a transistor, the structural diagram of which is shown below. Figure 12 As shown, it is fabricated using an SGOI substrate and includes: a strained silicon layer 300, a strained germanium layer 600, a buried oxide layer 20, a buried oxide layer 10, a source electrode 70, and a drain electrode 80. The strained silicon layer 300 is located below the strained germanium layer 600, the buried oxide layer 20 is located below the strained silicon layer 600, and the silicon substrate 20 is located below the buried oxide layer. The source / drain is located above the buried oxide layer 20 and on both sides of the strained silicon layer 300 and the strained germanium layer 600.

[0067] The source / drain is formed by etching both sides of the strained silicon layer 600 and the strained germanium layer 300.

[0068] In some alternative implementations, a back gate is also included, such as Figure 13 As shown, it is located below the silicon substrate.

[0069] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so they are described more simply; relevant parts can be referred to the descriptions in the method embodiments.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a semiconductor substrate, characterized in that, Includes the following steps: An SOI substrate is provided, the SOI substrate including a substrate, a buried oxide layer and a top silicon layer, a first buffer layer is deposited on the top silicon layer, a silicon nitride layer is deposited on the first buffer layer, a first heat treatment is performed, and then the first buffer layer and the silicon nitride layer are removed to obtain a strained SOI substrate. A GOI substrate is provided, the GOI substrate including a substrate, a buried oxide layer and a top germanium layer, a second buffer layer is deposited on the top germanium layer, a silicon nitride layer is deposited on the second buffer layer, a second heat treatment is performed, and then the second buffer layer and the silicon nitride layer are removed to obtain a strained GOI substrate. The strained SOI substrate and the strained GOI substrate are bonded together; The substrate and buried oxide layer in the strained SOI substrate or the substrate and buried oxide layer in the strained GOI substrate are removed to obtain a semiconductor substrate.

2. The method for preparing a semiconductor substrate according to claim 1, characterized in that, The substrate is a silicon substrate.

3. The method for preparing a semiconductor substrate according to claim 1, characterized in that, The first buffer layer includes a SiGe layer and a PEOX layer; and / or The second buffer layer includes a SiGe layer and a PEOX layer.

4. The method for preparing a semiconductor substrate according to claim 3, characterized in that, The thickness of the SiGe layer is 50~200nm, the thickness of the PEOX layer is 10~50nm, and the thickness of the silicon nitride layer is 100~500nm.

5. The method for preparing a semiconductor substrate according to claim 1, characterized in that, The temperature of the first heat treatment is 900~950℃; and / or The temperature of the second heat treatment is 900~950℃.

6. The method for preparing a semiconductor substrate according to claim 1, characterized in that, The bonding connection is a pressure bonding connection, and the bonding process conditions are: bonding force of 10~60KN, bonding temperature of 200~500℃, and bonding time of 0.5~8 hours.

7. The method for preparing a semiconductor substrate according to claim 1, characterized in that, The strained SOI substrate includes a substrate, a buried oxide layer, and a strained silicon layer; and / or The GOI substrate includes a substrate, a buried oxide layer, and a strained germanium layer.

8. A semiconductor substrate, characterized in that, It is prepared by the method according to any one of claims 1 to 7, and includes a substrate, a buried oxide layer, a strained silicon layer and a strained germanium layer; The buried oxide layer is located above the substrate, the strained silicon layer and the strained germanium layer are located above the buried oxide layer, and the strained silicon layer is located above or below the strained germanium layer.

9. A transistor, characterized in that, include: Strained silicon layer; Strained germanium layer; The strained silicon layer is located above or below the strained germanium layer; A buried oxide layer is located below the strained silicon layer or the strained germanium layer; The substrate is located below the buried oxide layer; The source / drain is located above the buried oxide layer and on both sides of the strained silicon layer and the strained germanium layer.

10. The transistor according to claim 9, characterized in that, It also includes a back gate located beneath the substrate.

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