A dual-gate GaN HEMT device and its fabrication method and chip
By introducing an isolation layer and an intermediate metal layer structure into GaN HEMT devices, the piezoelectric polarization effect between the barrier layer and the drift layer is weakened, the threshold voltage and switching speed are improved, the problem of low threshold voltage in GaN HEMT devices is solved, and its application in the electronic field is expanded.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIRIUS CORE SEMICON (CHENGDU) CO LTD
- Filing Date
- 2023-03-15
- Publication Date
- 2026-07-31
AI Technical Summary
GaN HEMT devices have a low threshold voltage, which can lead to false turn-on and limit their application in the electronics field.
A first isolation layer is added between the buffer layer and the drift layer, and an intermediate metal layer electrically connected to the source metal layer is formed on one side of the first isolation layer to form a depletion region, so as to reduce the piezoelectric polarization effect between the weak barrier layer and the drift layer. The first isolation layer outside the gate region is shielded by the first shielding region and the second shielding region to control the two-dimensional electron gas concentration at the position below the gate.
This improves the threshold voltage of the device, increases the switching speed, reduces source-drain leakage current, and expands the application scenarios of GaN HEMT in the electronic field.
Smart Images
Figure CN116435356B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor device technology, and particularly relates to a dual-gate GaN HEMT device, its fabrication method, and chip. Background Technology
[0002] Gallium nitride high electron mobility transistors (GaNHEMTs) have extremely high electron mobility and very low on-resistance. However, their threshold voltage (Vth) is low, making them prone to false turn-on, which limits the application of GaN HEMT devices in the electronics field. Summary of the Invention
[0003] This application provides a dual-gate GaN HEMT device and its fabrication method and chip, aiming to solve the problem of low threshold voltage in current GaNHMET devices.
[0004] To address the aforementioned technical problems, a first aspect of this application provides a dual-gate GaN HEMT device, comprising:
[0005] Semiconductor substrate;
[0006] A buffer layer and a first isolation layer are sequentially stacked on the semiconductor substrate; wherein the first isolation layer has a W-shaped structure.
[0007] The first shielding area and the second shielding area are respectively formed in two grooves on the first isolation layer, and the first shielding area and the second shielding area do not contact each other;
[0008] A drift layer and a barrier layer are stacked on the first shielding region and the second shielding region, as well as the spacer region between the first shielding region and the second shielding region.
[0009] A second isolation layer and a gate metal layer are stacked and formed on a portion of the barrier layer, with the second isolation layer disposed opposite to the spacer region.
[0010] A source metal layer and a drain metal layer are formed on the barrier layer and located on both sides of the second isolation layer; wherein the source metal layer and the drain metal layer are respectively located within the shielding range of the first shielding region and the second shielding region;
[0011] An intermediate metal layer is formed on one side of the first isolation layer and is electrically connected to the source metal layer.
[0012] In one embodiment, the width of the second isolation layer is equal to the width of the gap between the first shielding area and the second shielding area.
[0013] In one embodiment, the drift layer partially covers the first shielding area and the second shielding area.
[0014] In one embodiment, the area of the drift layer covering the first shielding area is greater than half the area of the first shielding area; the area of the drift layer covering the second shielding area is greater than half the area of the second shielding area.
[0015] In one embodiment, the spacing between the source metal layer and the second isolation layer is smaller than the spacing between the drain metal layer and the second isolation layer.
[0016] In one embodiment, the width of the first shielding area is smaller than the width of the second shielding area.
[0017] In one embodiment, the source metal layer is disposed opposite to the first shielding region; the drain metal layer is disposed opposite to the second shielding region.
[0018] In one embodiment, the drift layer has the same shape as the barrier layer; the second isolation layer has the same shape as the gate metal layer.
[0019] A second aspect of this application also provides a method for fabricating a dual-gate GaN HEMT device, the method comprising:
[0020] A buffer layer and a first isolation layer are sequentially stacked on a semiconductor substrate;
[0021] N-type doped ions are implanted into a first preset region and a second preset region of the first isolation layer to form a first shielding region and a second shielding region; the first shielding region and the second shielding region do not contact each other;
[0022] A drift layer and a barrier layer are stacked on the first shielding area, the second shielding area, and the interval between the first shielding area and the second shielding area.
[0023] A second isolation layer and a gate metal layer are stacked on a portion of the barrier layer, wherein the second isolation layer is disposed opposite to the spacer region.
[0024] A source metal layer and a drain metal layer are formed on the barrier layer; the source metal layer and the drain metal layer are located on both sides of the second isolation layer; wherein the source metal layer and the drain metal layer are respectively located within the shielding range of the first shielding region and the second shielding region;
[0025] Electrode material is deposited on one side of the first isolation layer to form an intermediate metal layer that is electrically connected to the source metal layer.
[0026] A third aspect of this application also provides a chip, including a dual-gate GaN HEMT device as described in any of the above embodiments; or including a dual-gate GaN HEMT device prepared by the preparation method described in the above embodiments.
[0027] The beneficial effects of the embodiments in this application compared with the prior art are:
[0028] By adding a first isolation layer between the buffer layer and the drift layer, and forming an intermediate metal layer electrically connected to the source metal layer on one side of the first isolation layer, a depletion region is formed between the first isolation layer and the drift layer. This reduces the piezoelectric polarization effect between the weak barrier layer and the drift layer, thereby lowering the concentration of two-dimensional electron gas (2DEG) between the barrier layer and the drift layer. Furthermore, by providing a first shielding region and a second shielding region on the first isolation layer to shield the area below the gate region, the concentration of 2DEG below the gate is controlled to remain low, while the concentration of 2DEG at other locations remains unaffected. This results in a higher gate voltage being required during device turn-on to achieve the 2DEG concentration required for turn-on, thus increasing the device threshold voltage. Additionally, by using a first isolation layer and an intermediate metal layer to reduce the concentration of 2DEG between the barrier layer and the drift layer, this application also helps to improve the turn-off speed of GaN HEMT devices and reduce source-drain leakage. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of the structure of the dual-gate GaN HEMT device provided in the embodiments of this application;
[0030] Figure 2 A schematic diagram illustrating the implementation flow of the fabrication method of the dual-gate GaN HEMT device provided in the embodiments of this application is shown;
[0031] Figure 3 A schematic diagram of the formation of a buffer layer 200 and a first isolation layer 300 provided in an embodiment of this application is shown;
[0032] Figure 4 A schematic diagram illustrating the formation of the first shielding region 310 and the second shielding region 320 provided in an embodiment of this application is shown;
[0033] Figure 5 A schematic diagram of the formation of GaN layer 410, AlGaN layer 510, P-type GaN layer 610 and metal layer 710 provided in the embodiments of this application is shown;
[0034] Figure 6 A schematic diagram of the formation of the drift layer 400 and the barrier layer 500 provided in an embodiment of this application is shown;
[0035] Figure 7 A schematic diagram of the formation of the second isolation layer 600 and the gate metal layer 700 provided in an embodiment of this application is shown. Detailed Implementation
[0036] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0037] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0038] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0040] Gallium nitride high electron mobility transistors (GaNHEMTs) have extremely high electron mobility and very low on-resistance; however, their low threshold voltage (Vth) limits their application in the electronics field.
[0041] In related technologies, increasing the gate length is generally used to improve the threshold voltage (Vth) of GaN HEMTs. However, increasing the gate length will reduce the switching speed of the device and increase the switching loss. Therefore, it is necessary to develop new GaN HEMT devices that can improve the threshold voltage in order to expand the application scenarios of GaN HEMTs in the electronic field.
[0042] To address the aforementioned technical problems, this application provides a dual-gate GaN HEMT device, see [link to relevant documentation]. Figure 1 As shown, the dual-gate GaN HEMT device in this embodiment includes: a semiconductor substrate 100, a buffer layer 200, a first isolation layer 300, a first shielding region 310, a second shielding region 320, a drift layer 400, a barrier layer 500, a second isolation layer 600, a gate metal layer 700, a source metal layer 810, a drain metal layer 820, and an intermediate metal layer 830.
[0043] In this configuration, a buffer layer 200 and a first isolation layer 300 are sequentially stacked on a semiconductor substrate 100. The first isolation layer 300 has a W-shaped structure. A first shielding region 310 and a second shielding region 320 are respectively formed in two grooves on the first isolation layer 300, and the first shielding region 310 and the second shielding region 320 do not contact each other. A drift layer 400 and a barrier layer 500 are stacked on the first shielding region 310, the second shielding region 320, and the interval between the first shielding region 310 and the second shielding region 320. A second isolation layer 600 and a gate metal layer 700 are stacked on a portion of the barrier layer 500, and the second isolation layer 600 is disposed opposite to the aforementioned interval.
[0044] The source metal layer 810 and the drain metal layer 820 are formed on the barrier layer 500 and are located on both sides of the second isolation layer 600. The source metal layer 810 and the drain metal layer 820 are located within the shielding range of the first shielding region 310 and the second shielding region 320, respectively. The intermediate metal layer 830 is formed on one side of the first isolation layer 300 and is electrically connected to the source metal layer 810 to form a dual-gate GaNHEMT device.
[0045] In the above structure, by adding a first isolation layer 300 between the buffer layer 200 and the drift layer 400 of a conventional GaN HEMT device, and forming an intermediate metal layer 830 electrically connected to the source metal layer 810 on one side of the first isolation layer 300, a depletion region is formed between the first isolation layer 300 and the drift layer 400. This reduces the piezoelectric polarization effect between the barrier layer 500 and the drift layer 400, thereby reducing the concentration of two-dimensional electron gas (2DEG) between the barrier layer 500 and the drift layer 400. The first isolation layer 300, except for the area below the gate region, is shielded by the first shielding region 310 and the second shielding region 320. This controls the 2DEG concentration below the gate to remain low, while the 2DEG concentration at other locations remains unaffected. As a result, a higher gate voltage is required during device turn-on in order to achieve the turn-on condition for the 2DEG concentration, thereby increasing the device threshold voltage.
[0046] Specifically, this application forms an intermediate metal layer 830 electrically connected to the source metal layer 810 on one side of the first isolation layer 300, so that the first isolation layer is at a low potential relative to the drift layer, thereby forming a depletion region between the first isolation layer 300 and the drift layer 400. This reduces the piezoelectric polarization effect between the weak barrier layer 500 and the drift layer 400, and thus reduces the concentration of two-dimensional electron gas (2DEG) between the barrier layer 500 and the drift layer 400. Furthermore, a portion of the two-dimensional electron gas (2DEG) between the barrier layer 500 and the drift layer 400 is also depleted by the second isolation layer 600. Therefore, during device turn-on, a higher gate voltage is required to achieve the required 2DEG concentration for the device to turn on, thereby increasing the device threshold voltage.
[0047] In addition, by setting the first isolation layer 300 and the intermediate metal layer 830, this application reduces the concentration of two-dimensional electron gas (2DEG) between the barrier layer 500 and the drift layer 400, thereby improving the turn-off speed of the GaN HEMT device and reducing the leakage current of the source and drain.
[0048] In one embodiment, the semiconductor substrate 100 may be a P-type substrate.
[0049] In one embodiment, the first isolation layer 300 can be P-type GaN.
[0050] In one embodiment, when the first isolation layer 300 is P-type GaN, N-type doped ions or N-type impurities can be implanted into two non-contacting first and second preset regions on the first isolation layer 300 by ion implantation, thereby forming the first shielding region 310 and the second shielding region 320 on the first isolation layer 300, and making the first isolation layer 300 have a W-shaped structure, with the first shielding region 310 and the second shielding region 320 located in two grooves of the first isolation layer 300 respectively.
[0051] In one embodiment, the first shielding area 310 and the second shielding area 320 have the same depth, and the depth of the first shielding area 310 and the second shielding area 320 is less than the depth of the first isolation layer 300.
[0052] In one embodiment, the width of the second isolation layer 600 is equal to the width of the gap between the first shielding region 310 and the second shielding region 320, so that the first shielding region 310 and the second shielding region 320 can shield only the first isolation layer outside the gate region, so as to control the 2DEG concentration at the position directly below the gate to remain low, while the 2DEG concentration at other positions is not affected.
[0053] In one embodiment, the width of the second isolation layer 600 may be smaller than the width of the gap between the first shielding region 310 and the second shielding region 320. That is, the threshold voltage of the GaN HEMT device can be set by changing the width of the second isolation layer.
[0054] In one embodiment, the drift layer 400 can partially cover the first shielding region 310 and the second shielding region 320, as long as the source metal layer 810 and the drain metal layer 820 are located within the shielding range of the first shielding region 310 and the second shielding region 320, respectively.
[0055] Specifically, in one embodiment, combined with Figure 1 As shown, the area of the drift layer 400 covering the first shielding area 310 is greater than half the area of the first shielding area 310, and the area of the drift layer 400 covering the second shielding area 320 is greater than half the area of the second shielding area 320.
[0056] In one embodiment, the spacing between the source metal layer 810 and the second isolation layer 600 is smaller than the spacing between the drain metal layer 820 and the second isolation layer 600.
[0057] Therefore, the width of the first shielding region 310 is smaller than the width of the second shielding region 320, so that the source metal layer 810 and the drain metal layer 820 can be located within the shielding ranges of the first shielding region 310 and the second shielding region 320, respectively. That is, the source metal layer 810 is located within the shielding range of the first shielding region 310, and the drain metal layer 820 is located within the shielding range of the second shielding region 320.
[0058] In one embodiment, to ensure that the source metal layer 810 is located within the shielding range of the first shielding region 310, and the drain metal layer 820 is located within the shielding range of the second shielding region 320, such as... Figure 1 As shown, the source metal layer 810 can be arranged opposite to the first shielding region 310; the drain metal layer 820 can be arranged opposite to the second shielding region 320, that is, the lower projection of the source metal layer 810 coincides with the lower projection of the first shielding region 310, and the lower projection of the drain metal layer 820 coincides with the lower projection of the second shielding region 320.
[0059] In one embodiment, the drift layer 400 has the same shape as the barrier layer 500; the second isolation layer 600 has the same shape as the gate metal layer 700.
[0060] In this embodiment of the application, the first isolation layer 300 and the second isolation layer 600 can be P-type GaN, the drift layer 400 can be GaN, and the barrier layer 500 can be AlGaN.
[0061] This application also provides a method for fabricating a dual-gate GaN HEMT device, which is used to fabricate the aforementioned dual-gate GaN HEMT device.
[0062] See Figure 2 As shown, the preparation method in this embodiment includes steps S100 to S600.
[0063] In step S100, a buffer layer and a first isolation layer are sequentially stacked on a semiconductor substrate;
[0064] Combination Figure 3 As shown, in this embodiment, a buffer layer 200 and a first isolation layer 300 can be sequentially stacked on a semiconductor substrate 100 by means of ion implantation, diffusion or epitaxial growth.
[0065] In one embodiment, the semiconductor substrate 100 may be a P-type substrate.
[0066] In one embodiment, the first isolation layer 300 can be P-type GaN.
[0067] In step S200, N-type doped ions are implanted into the first and second preset regions of the first isolation layer to form a first shielding region and a second shielding region, respectively. The first shielding region and the second shielding region are not in contact with each other.
[0068] Combination Figure 4 As shown, after N-type doped ions are injected into the first preset region and the second preset region of the first isolation layer to form the first shielding region 310 and the second shielding region 320, the first isolation layer 300 has a W-shaped structure.
[0069] In one embodiment, the first shielding area 310 and the second shielding area 320 have the same depth, and the depth of the first shielding area 310 and the second shielding area 320 is less than the depth of the first isolation layer 300.
[0070] In one embodiment, when the first isolation layer is P-type GaN, N-type GaN can be implanted into the two grooves on the first isolation layer by ion implantation to form the first shielding region and the second shielding region.
[0071] In step S300, a drift layer and a barrier layer are stacked on the first shielding area, the second shielding area, and the interval area between the first shielding area and the second shielding area.
[0072] In this embodiment of the application, combined with Figure 1 and Figure 7As shown, the drift layer 400 and barrier layer 500 stacked on the first shielding region 310 and the second shielding region 320 and the interval region between the first shielding region 310 and the second shielding region 320 can refer to the drift layer 400 and barrier layer 500 being stacked on a portion of the surface of the first shielding region 310, a portion of the surface of the second shielding region 320, and the entire surface of the interval region between the first shielding region 310 and the second shielding region 320.
[0073] In other words, the drift layer 400 can partially cover the first shielding area 310 and the second shielding area 320.
[0074] Specifically, in one embodiment, the area of the drift layer 400 covering the first shielding area 310 is greater than half the area of the first shielding area 310; the area of the drift layer 400 covering the second shielding area 320 is greater than half the area of the second shielding area 320.
[0075] In step S400, a second isolation layer and a gate metal layer are stacked on a portion of the barrier layer, with the second isolation layer disposed opposite to the spacer region.
[0076] In this embodiment of the application, combined with Figure 1 As shown, the second isolation layer 600 is positioned opposite to the interval region, meaning that the lower projection of the second isolation layer 600 coincides with the lower projection of the interval region between the first shielding region 310 and the second shielding region 320. This allows the depletion region formed between the first isolation layer 300 and the drift layer 400 to reduce the piezoelectric polarization effect between the barrier layer 500 and the drift layer 400, thereby reducing the concentration of two-dimensional electron gas (2DEG) between the barrier layer 500 and the drift layer 400. As a result, a higher gate voltage is required during device turn-on in order to achieve the required 2DEG concentration, thereby increasing the device threshold voltage.
[0077] In one embodiment, the drift layer 400 has the same shape as the barrier layer 500; the second isolation layer 600 has the same shape as the gate metal layer 700.
[0078] In one embodiment, the drift layer 400 can be GaN, the barrier layer 500 can be AlGaN, and the second isolation layer 600 can be P-type GaN.
[0079] Combination Figure 1 , Figure 5 , Figure 6 and Figure 7As shown in the embodiment of this application, during the process of forming the drift layer 400, barrier layer 500, second isolation layer 600 and gate metal layer 700 in the above steps S300 to S400, GaN layer 410, AlGaN layer 510, P-type GaN layer 610 and metal layer 710 can be formed sequentially on the surfaces of the first isolation layer 300, the first shielding region 310 and the second shielding region 320. Then, the GaN layer 410, AlGaN layer 510, P-type GaN layer 610 and metal layer 710 are etched for the first time to form the drift layer 400 and barrier layer 500. Next, the P-type GaN layer 610 and metal layer 710 are etched for the second time to form the second isolation layer 600 and gate metal layer 700.
[0080] In step S500, a source metal layer and a drain metal layer are formed on the barrier layer; the source metal layer and the drain metal layer are located on both sides of the second isolation layer.
[0081] In this embodiment, combined with Figure 1 As shown, the source metal layer 810 and the drain metal layer 820 are located within the shielding ranges of the first shielding region 310 and the second shielding region 320, respectively.
[0082] In step S600, electrode material is deposited on one side of the first isolation layer 300 to form an intermediate metal layer electrically connected to the source metal layer 810.
[0083] In one embodiment, combined Figure 1 As shown, the spacing between the source metal layer 810 and the second isolation layer 600 is smaller than the spacing between the drain metal layer 820 and the second isolation layer 600.
[0084] Therefore, the width of the first shielding region 310 is smaller than the width of the second shielding region 320, so that the source metal layer 810 and the drain metal layer 820 can be located within the shielding ranges of the first shielding region 310 and the second shielding region 320, respectively. That is, the source metal layer 810 is located within the shielding range of the first shielding region 310, and the drain metal layer 820 is located within the shielding range of the second shielding region 320.
[0085] In one embodiment, to ensure that the source metal layer 810 is located within the shielding range of the first shielding region 310, and the drain metal layer 820 is located within the shielding range of the second shielding region 320, such as... Figure 1 As shown, the source metal layer 810 can be arranged opposite to the first shielding region 310; the drain metal layer 820 can be arranged opposite to the second shielding region 320, that is, the lower projection of the source metal layer 810 coincides with the lower projection of the first shielding region 310, and the lower projection of the drain metal layer 820 coincides with the lower projection of the second shielding region 320.
[0086] In one embodiment, the drift layer 400 has the same shape as the barrier layer 500; the second isolation layer 600 has the same shape as the gate metal layer 700.
[0087] This application also provides a chip, including a dual-gate GaN HEMT device as described in any of the above embodiments.
[0088] In one embodiment, the chip in this embodiment includes a dual-gate GaN HEMT device fabricated by the fabrication method of any of the above embodiments.
[0089] In one embodiment, the chip includes a chip substrate on which one or more dual-gate GaN HEMT devices are disposed. The dual-gate GaN HEMT devices can be fabricated by the fabrication method in any of the above embodiments, or the dual-gate GaN HEMT devices in any of the above embodiments can be disposed on the chip substrate.
[0090] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the dual-gate GaN HEMT device.
[0091] In one specific application embodiment, the chip can be a switch chip, a driver chip, or a radio frequency chip.
[0092] The beneficial effects of the embodiments in this application compared with the prior art are:
[0093] By adding a first isolation layer between the buffer layer and the drift layer, and forming an intermediate metal layer electrically connected to the source metal layer on one side of the first isolation layer, a depletion region is formed between the first isolation layer and the drift layer. This reduces the piezoelectric polarization effect between the weak barrier layer and the drift layer, thereby reducing the concentration of two-dimensional electron gas (2DEG) between the barrier layer and the drift layer. The first isolation layer, except for the area below the gate region, is shielded by the first and second shielding regions to control the 2DEG concentration below the gate to remain low, while the 2DEG concentration at other locations remains unaffected. This means that during device turn-on, a higher gate voltage is required to achieve the turn-on condition for the 2DEG concentration, thereby increasing the device threshold voltage.
[0094] In addition, by setting a first isolation layer and an intermediate metal layer, this application reduces the concentration of two-dimensional electron gas (2DEG) between the barrier layer and the drift layer, which is beneficial to improving the turn-off speed of GaN HEMT devices and reducing leakage current between the source and drain.
[0095] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A dual-gate GaN HEMT device, characterized by, The dual-gate GaN HEMT device includes: Semiconductor substrate; A buffer layer and a first isolation layer are sequentially stacked on the semiconductor substrate; wherein the first isolation layer has a W-shaped structure. The first shielding area and the second shielding area are respectively formed in two grooves on the first isolation layer, and the first shielding area and the second shielding area do not contact each other; A drift layer and a barrier layer are stacked on the first shielding region, the second shielding region, and the spacer region between the first shielding region and the second shielding region. A second isolation layer and a gate metal layer are stacked and formed on a portion of the barrier layer, with the second isolation layer disposed opposite to the spacer region. A source metal layer and a drain metal layer are formed on the barrier layer and located on both sides of the second isolation layer; wherein the source metal layer and the drain metal layer are respectively located within the shielding range of the first shielding region and the second shielding region; An intermediate metal layer is formed on one side of the first isolation layer and is electrically connected to the source metal layer.
2. The dual-gate GaN HEMT device of claim 1, wherein, The width of the second isolation layer is equal to the width of the gap between the first shielding area and the second shielding area.
3. The dual-gate GaN HEMT device of claim 1, wherein, The drift layer partially covers the first shielding area and the second shielding area.
4. The dual-gate GaN HEMT device of claim 3, wherein, The drift layer covers an area greater than half the area of the first shielding area; The area covered by the drift layer of the second shielding area is greater than half the area of the second shielding area.
5. The dual-gate GaN HEMT device according to claim 1, characterized in that, The distance between the source metal layer and the second isolation layer is less than the distance between the drain metal layer and the second isolation layer.
6. The dual-gate GaN HEMT device according to claim 5, characterized in that, The width of the first shielding area is smaller than the width of the second shielding area.
7. The dual-gate GaN HEMT device according to any one of claims 1-6, characterized in that, The source metal layer is disposed opposite to the first shielding region; the drain metal layer is disposed opposite to the second shielding region.
8. The dual-gate GaN HEMT device according to any one of claims 1-6, characterized in that, The drift layer has the same shape as the barrier layer; the second isolation layer has the same shape as the gate metal layer.
9. A method for fabricating a dual-gate GaN HEMT device, characterized in that, The preparation method includes: A buffer layer and a first isolation layer are sequentially stacked on a semiconductor substrate; N-type doped ions are implanted into a first preset region and a second preset region of the first isolation layer to form a first shielding region and a second shielding region; the first shielding region and the second shielding region do not contact each other; A drift layer and a barrier layer are stacked on the first shielding area, the second shielding area, and the interval between the first shielding area and the second shielding area; A second isolation layer and a gate metal layer are stacked on a portion of the barrier layer, wherein the second isolation layer is disposed opposite to the spacer region. A source metal layer and a drain metal layer are formed on the barrier layer; the source metal layer and the drain metal layer are located on both sides of the second isolation layer; wherein the source metal layer and the drain metal layer are respectively located within the shielding range of the first shielding region and the second shielding region; Electrode material is deposited on one side of the first isolation layer to form an intermediate metal layer that is electrically connected to the source metal layer.
10. A chip, characterized in that, Includes the dual-gate GaN HEMT device as described in any one of claims 1-8; or includes the dual-gate GaN HEMT device prepared by the preparation method described in claim 9.