Light-load efficiency enhancement circuit for DC-DC converters in FCCM mode and DC-DC converter

Abstract

This disclosure provides a light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode, and a DC-DC converter itself. The light-load efficiency enhancement circuit includes a light-load judgment circuit, a logic control circuit, a freewheeling diode drive circuit, and a power transistor drive circuit. The light-load judgment circuit generates a light-load indication signal based on the freewheeling diode sampling current and the light-load threshold current. The logic control circuit generates a freewheeling diode turn-on signal and a power transistor turn-on signal based on the DC-DC converter's duty cycle modulation signal and a clock signal, and generates a fast-drive indication signal based on the light-load indication signal. The freewheeling diode drive circuit accelerates the turn-off speed of the DC-DC converter's freewheeling diode when the fast-drive indication signal is at an active level and the freewheeling diode turn-on signal is at an inactive level. The power transistor drive circuit accelerates the turn-on speed of the DC-DC converter's power transistor when both the fast-drive indication signal and the power transistor turn-on signal are at active levels.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a light-load efficiency enhancement circuit for a DC-DC converter in forced continuous conduction mode (FCCM mode), and a DC-DC converter in FCCM mode. Background Technology

[0002] DC-DC (Direct-to-Direct-to-Converter) converters are commonly used in various electronic devices to convert DC voltages. DC-DC converters include buck converters and boost converters. Buck converters convert higher DC voltages to lower DC voltages, while boost converters convert lower DC voltages to higher DC voltages. During the operation of a DC-DC converter, the freewheeling transistor and the power transistor alternately turn on and off. At the instant the freewheeling transistor turns off and the power transistor turns on, the drain-source voltage of the power transistor is not zero, but current is already flowing through it, thus incurring switching losses. This significantly reduces the efficiency of the DC-DC converter, especially under light load conditions. Summary of the Invention

[0003] The embodiments described herein provide a light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode, and a DC-DC converter in FCCM mode.

[0004] According to a first aspect of this disclosure, a light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode is provided. The light-load efficiency enhancement circuit includes: a light-load judgment circuit, a logic control circuit, a freewheeling diode drive circuit, and a power transistor drive circuit. The light-load judgment circuit is configured to generate a light-load indication signal based on the freewheeling diode sampling current and a light-load threshold current of the DC-DC converter. An active level of the light-load indication signal indicates that the load of the DC-DC converter is light-loaded. The logic control circuit is configured to generate a freewheeling diode turn-on signal and a power transistor turn-on signal based on a duty cycle modulation signal and a clock signal of the DC-DC converter, and to generate a fast-drive indication signal based on the light-load indication signal. The freewheeling diode drive circuit is configured to accelerate the turn-off speed of the freewheeling diode of the DC-DC converter when the fast-drive indication signal is active and the freewheeling diode turn-on signal is inactive. The power transistor drive circuit is configured to accelerate the turn-on speed of the power transistor of the DC-DC converter when both the fast-drive indication signal and the power transistor turn-on signal are active.

[0005] In some embodiments of this disclosure, the freewheeling drive circuit is further configured to: drive the freewheeling of the DC-DC converter to turn off at a normal speed when both the fast drive indication signal and the freewheeling turn-on signal are at invalid levels, and drive the freewheeling of the DC-DC converter to turn on at a normal speed when the freewheeling turn-on signal is at an active level.

[0006] In some embodiments of this disclosure, the power transistor drive circuit is further configured to: drive the power transistor of the DC-DC converter to turn on at a normal speed when the fast drive indication signal is at an invalid level and the power transistor turn-on signal is at an active level, and drive the power transistor of the DC-DC converter to turn off at a normal speed when the power transistor turn-on signal is at an invalid level.

[0007] In some embodiments of this disclosure, the light load judgment circuit includes: a freewheeling diode current detection circuit, a detection result storage circuit, a reset circuit, and a level conversion circuit. The freewheeling diode current detection circuit is configured to generate a detection signal during the period when the freewheeling diode conduction signal is at an effective level and provide the detection signal to the level conversion circuit and the detection result storage circuit via a first node. The detection signal is at an effective level when the freewheeling diode sampling current is lower than the light load threshold current. The detection result storage circuit is configured to store the voltage of the first node. The reset circuit is configured to reset the voltage of the first node to an ineffective level when the freewheeling diode conduction signal or the clock signal flips to an effective level. The level conversion circuit is configured to convert the effective level of the detection signal to a target level to generate a light load indication signal.

[0008] In some embodiments of this disclosure, the freewheeling diode current detection circuit includes a current comparator and a voltage-controlled switch. A first input terminal of the current comparator is provided with a light-load threshold current. A second input terminal of the current comparator is provided with the freewheeling diode sampling current. The output terminal of the current comparator is coupled to a first terminal of the voltage-controlled switch. A freewheeling diode on signal is provided to the controlled terminal of the voltage-controlled switch. A second terminal of the voltage-controlled switch is coupled to a first node.

[0009] In some embodiments of this disclosure, the detection result storage circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a first node. A second terminal of the first capacitor is coupled to a second voltage terminal.

[0010] In some embodiments of this disclosure, the reset circuit includes a first transistor. The control electrode of the first transistor is provided with one of a clock signal and a freewheeling diode on signal. The first electrode of the first transistor is coupled to a second voltage terminal. The second electrode of the first transistor is coupled to a first node.

[0011] In some embodiments of this disclosure, the freewheeling diode driving circuit includes: a first inverter, a first NAND gate, a freewheeling diode driving signal generation circuit, and a freewheeling diode accelerated turn-off driving circuit. The freewheeling diode driving signal generation circuit is configured to generate a freewheeling diode driving signal based on a freewheeling diode turn-on signal. When the freewheeling diode turn-on signal is at an active level, the freewheeling diode driving signal drives the freewheeling diode to turn on. When the freewheeling diode turn-on signal is at an inactive level, the freewheeling diode driving signal drives the freewheeling diode to turn off. The input terminal of the first inverter is provided with the freewheeling diode turn-on signal. The output terminal of the first inverter is coupled to the first input terminal of the first NAND gate. The second input terminal of the first NAND gate is provided with a fast drive indication signal. The output terminal of the first NAND gate is coupled to the input terminal of the freewheeling diode accelerated turn-off driving circuit. The freewheeling diode accelerated turn-off driving signal is output from the output terminal of the first NAND gate. The freewheeling diode accelerated turn-off driving circuit is configured to increase the toggling speed of the freewheeling diode driving signal to accelerate the turn-off speed of the freewheeling diode when the freewheeling diode accelerated turn-off signal is at an active level.

[0012] In some embodiments of this disclosure, the power transistor driving circuit includes: a first AND gate, a power transistor driving signal generation circuit, and a power transistor acceleration turn-on driving circuit. The power transistor driving signal generation circuit is configured to generate a power transistor driving signal based on a power transistor turn-on signal. When the power transistor turn-on signal is at an active level, the power transistor driving signal drives the power transistor to turn on. When the power transistor turn-on signal is at an inactive level, the power transistor driving signal drives the power transistor to turn off. A first input terminal of the first AND gate is provided with a power transistor turn-on signal. A second input terminal of the first AND gate is provided with a fast drive indication signal. The output terminal of the first AND gate is coupled to the input terminal of the power transistor acceleration turn-on driving circuit. A power transistor acceleration drive signal is output from the output terminal of the first AND gate. The power transistor acceleration turn-on driving circuit is configured to increase the toggling speed of the power transistor driving signal to accelerate the turn-on speed of the power transistor when the power transistor acceleration drive signal is at an active level.

[0013] In some embodiments of this disclosure, the DC-DC converter is a boost converter.

[0014] In some embodiments of this disclosure, the DC-DC converter is a buck converter.

[0015] According to a second aspect of this disclosure, a light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode is provided. The light-load efficiency enhancement circuit includes: a logic control circuit, a current comparator, a voltage-controlled switch, a first capacitor, a first transistor, a buffer, a first inverter, a first NAND gate, a freewheeling diode drive signal generation circuit, a freewheeling diode accelerated turn-off drive circuit, a first AND gate, a power transistor drive signal generation circuit, and a power transistor accelerated turn-on drive circuit. The logic control circuit is configured to generate a freewheeling diode turn-on signal and a power transistor turn-on signal based on a duty cycle modulation signal and a clock signal of the DC-DC converter, and to generate a fast drive indication signal based on a light-load indication signal output from the buffer. A first input terminal of the current comparator is provided with a light-load threshold current. A second input terminal of the current comparator is provided with a freewheeling diode sampling current of the DC-DC converter. The output terminal of the current comparator is coupled to a first terminal of the voltage-controlled switch. A controlled terminal of the voltage-controlled switch is provided with a freewheeling diode turn-on signal. A second terminal of the voltage-controlled switch is coupled to a first terminal of the first capacitor. A second terminal of the first capacitor is coupled to a second voltage terminal. The control electrode of the first transistor is provided with either a clock signal or a freewheeling diode turn-on signal. The first electrode of the first transistor is coupled to a second voltage terminal. The second electrode of the first transistor is coupled to a first terminal of a first capacitor. A buffer is configured to convert a first level at the first terminal of the first capacitor to a target level to generate a light-load indication signal. A freewheeling diode drive signal generation circuit is configured to generate a freewheeling diode drive signal based on the freewheeling diode turn-on signal. When the freewheeling diode turn-on signal is at an active level, the freewheeling diode drive signal drives the freewheeling diode of the DC-DC converter to turn on. When the freewheeling diode turn-on signal is at an inactive level, the freewheeling diode drive signal drives the freewheeling diode to turn off. The input of the first inverter is provided with the freewheeling diode turn-on signal. The output of the first inverter is coupled to the first input of a first NAND gate. The second input of the first NAND gate is provided with a fast drive indication signal. The output of the first NAND gate is coupled to the input of a freewheeling diode accelerated turn-off drive circuit. A freewheeling diode accelerated drive signal is output from the output of the first NAND gate. The freewheeling diode accelerated turn-off drive circuit is configured to increase the toggling speed of the freewheeling diode drive signal to accelerate the turn-off speed of the freewheeling diode when the freewheeling diode accelerated drive signal is at an active level. The power transistor drive signal generation circuit is configured to generate a power transistor drive signal based on the power transistor turn-on signal. Specifically, when the power transistor turn-on signal is at an active level, the power transistor drive signal drives the power transistor to turn on. When the power transistor turn-on signal is at an inactive level, the power transistor drive signal drives the power transistor to turn off. The first input of the first AND gate is provided with the power transistor turn-on signal. The second input of the first AND gate is provided with a fast drive indication signal. The output of the first AND gate is coupled to the input of the power transistor accelerated turn-on drive circuit. The power transistor accelerated drive signal is output from the output of the first AND gate.The power transistor acceleration drive circuit is configured to increase the switching speed of the power transistor drive signal to accelerate the power transistor's turn-on speed when the power transistor acceleration drive signal is at an effective level.

[0016] In some embodiments of this disclosure, the DC-DC converter is a boost converter.

[0017] In some embodiments of this disclosure, the DC-DC converter is a buck converter.

[0018] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes a light-load efficiency enhancement circuit as described in a first or second aspect of this disclosure. The DC-DC converter operates in FCCM mode.

[0019] In some embodiments of this disclosure, the DC-DC converter is a boost converter.

[0020] In some embodiments of this disclosure, the DC-DC converter is a buck converter.

[0021] According to a fourth aspect of this disclosure, a chip is provided. The chip includes the DC-DC converter described in a third aspect of this disclosure.

[0022] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0024] Figure 1 This is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0025] Figure 2 This is a schematic block diagram of a light-load efficiency enhancement circuit according to an embodiment of the present disclosure;

[0026] Figure 3 This is an exemplary circuit diagram of a light-load efficiency enhancement circuit according to embodiments of the present disclosure; and

[0027] Figure 4 This is a timing diagram of some signals used in a light-load efficiency enhancement circuit according to an embodiment of the present disclosure.

[0028] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0031] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0032] As mentioned above, under light load conditions, the efficiency of a DC-DC converter decreases due to switching losses. Increasing the drive speed of the DC-DC converter to a faster speed for turning the power transistors on and off under any load can indeed improve light-load efficiency. However, under heavy load conditions, the faster switching speed can cause large voltage spikes across the drain and source of the power transistors, potentially leading to transistor breakdown.

[0033] For DC-DC converters operating in FCCM mode, to improve light-load efficiency and prevent power transistor breakdown, this disclosure proposes monitoring the valley current of the freewheeling transistor. When the valley current of the freewheeling transistor is higher than a target value, the freewheeling transistor and the power transistor are driven at the normal drive speed. When the valley current of the freewheeling transistor is lower than the target value, the freewheeling transistor and the power transistor are driven at a fast drive speed during the initial turn-off and turn-on of the power transistor, thereby effectively reducing switching losses and improving the light-load efficiency of the DC-DC converter in FCCM mode. Here, normal drive speed refers to a drive speed lower than fast drive speed that will not cause power transistor breakdown.

[0034] Figure 1 A schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure is shown. The DC-DC converter is configured to operate in Forced Continuous On-Mode (FCCM mode). The DC-DC converter includes: an error amplifier EA, a pulse width modulation comparator PWM_COMP, a compensation capacitor Cc, a compensation resistor Rc, a resistor Rs, a current source I1, a freewheeling transistor MH, a power transistor ML, a freewheeling current sampling transconductance amplifier Gcs, an inductor L, a filter capacitor Cout, feedback resistors Rfb1 and Rfb2, and a light-load efficiency enhancement circuit 100. To avoid obscuring the focus of this disclosure with unnecessary details, Figure 1 The complete components of a DC-DC converter are not shown in the diagram.

[0035] exist Figure 1 In the example, the error amplifier EA generates an error signal eaout based on the output voltage Vout of the DC-DC converter and the reference voltage Vref. The error signal eaout is provided to the inverting input of the pulse width modulation comparator PWM_COMP. The non-inverting input of the PWM_COMP is coupled to a current source I1 and a resistor Rs via node sum. The current value of the current source I1 is equal to Idc1 - IL, where Idc1 represents a preset constant current value, and IL represents the inductor current flowing through inductor L. Therefore, the current value of the current source I1 changes with the inductor current, causing the voltage at node sum to change with the inductor current. The PWM_COMP generates a duty cycle modulation signal MTR based on the voltage at node sum and the error signal eaout. The freewheeling diode current sampling transconductance amplifier Gcs samples the current flowing through the freewheeling diode MH. Isns represents the current flowing through the freewheeling diode MH. The light-load efficiency enhancement circuit 100 generates the freewheeling diode drive signal HG and the power transistor drive signal LG based on the duty cycle modulation signal MTR, the clock signal CLK, the freewheeling diode current Isns, and the light-load threshold current Ith. Figure 1In the example, the freewheeling transistor MH is a P-type transistor, and the power transistor ML is an N-type transistor. When the freewheeling transistor drive signal HG is low, the freewheeling transistor MH is turned on. When the freewheeling transistor drive signal HG is high, the freewheeling transistor MH is turned off. When the power transistor drive signal LG is high, the power transistor ML is turned on. When the power transistor drive signal LG is low, the power transistor ML is turned off.

[0036] When the freewheeling transistor MH is on and the power transistor ML is off, the inductor L discharges, and the inductor current flowing through the inductor L gradually decreases. When the freewheeling transistor MH is off and the power transistor ML is on, the inductor L charges, and the inductor current flowing through the inductor L gradually increases.

[0037] The light-load efficiency enhancement circuit 100 is configured to: accelerate the turn-off speed of the freewheeling transistor MH and accelerate the turn-on speed of the power transistor ML under light-load conditions, and drive the freewheeling transistor MH and the power transistor ML at normal drive speed under other conditions.

[0038] In some embodiments of this disclosure, the light-load efficiency enhancement circuit 100 includes: a light-load judgment circuit 110, a logic control circuit 120, a freewheeling diode driving circuit 130, and a power transistor driving circuit 140.

[0039] The light load detection circuit 110 is coupled to the freewheeling diode current sampling transconductance amplifier Gcs, the light load threshold current source Ith, the logic control circuit 120, and the freewheeling diode drive circuit 130. The light load detection circuit 110 is configured to generate a light load indication signal VY based on the freewheeling diode sampling current Isns and the light load threshold current Ith of the DC-DC converter. A valid level of the light load indication signal VY indicates that the load of the DC-DC converter is light-loaded. An invalid level of the light load indication signal VY indicates that the load of the DC-DC converter is not light-loaded.

[0040] Logic control circuit 120 is coupled to the output of pulse width modulation comparator PWM_COMP, clock signal CLK, light load judgment circuit 110, freewheeling diode drive circuit 130, and power transistor drive circuit 140. Logic control circuit 120 is configured to generate freewheeling diode turn-on signal MON and power transistor turn-on signal SON based on the duty cycle modulation signal MTR and clock signal CLK of the DC-DC converter, and to generate fast drive indication signal FT based on the light load indication signal VY. In some embodiments of this disclosure, when the duty cycle modulation signal MTR is at an active level (in... Figure 1 In the example, when the signal is high, the freewheeling diode conduction signal MON flips to an invalid level (in...). Figure 1 In the example, the signal is low; the power transistor on signal SON flips to an active level (in...). Figure 1In the example, it is high level). When the clock signal CLK is at an active level (e.g., high level), the freewheeling diode on signal MON toggles to an active level (in...). Figure 1 In the example, it is high level), and the power transistor on signal SON toggles to an invalid level (in Figure 1 (In the example, it is a low level). In some embodiments of this disclosure, when the light load indicator signal VY is at an active level, the fast drive indicator signal FT is at an active level. When the light load indicator signal VY is at an inactive level, the fast drive indicator signal FT is at an inactive level.

[0041] The freewheeling diode drive circuit 130 is coupled to the logic control circuit 120, the light load judgment circuit 110, the power transistor drive circuit 140, and the freewheeling diode MH. The freewheeling diode drive circuit 130 can be configured to accelerate the turn-off speed of the freewheeling diode MH in the DC-DC converter when the fast drive indicator signal FT is at an active level and the freewheeling diode turn-on signal MON is at an inactive level. The freewheeling diode drive circuit 130 can also be configured to drive the freewheeling diode MH of the DC-DC converter to turn off at a normal speed when both the fast drive indicator signal FT and the freewheeling diode turn-on signal MON are at inactive levels, and to drive the freewheeling diode MH of the DC-DC converter to turn on at a normal speed when the freewheeling diode turn-on signal MON is at an active level.

[0042] The power transistor driver circuit 140 is coupled to the logic control circuit 120, the freewheeling transistor driver circuit 130, and the power transistor ML. The power transistor driver circuit 140 can be configured to accelerate the turn-on speed of the power transistor ML of the DC-DC converter when both the fast drive indicator signal FT and the power transistor turn-on signal SON are at active levels. The power transistor driver circuit 140 can also be configured to drive the power transistor ML of the DC-DC converter to turn on at a normal speed when the fast drive indicator signal FT is at an inactive level and the power transistor turn-on signal SON is at an active level, and to drive the power transistor ML of the DC-DC converter to turn off at a normal speed when the power transistor turn-on signal SON is at an inactive level.

[0043] Here, normal speed is relative to the accelerated turn-off / turn-on speed. Normal speed is slower than accelerated turn-off / turn-on speed and will not cause the power transistor to break down.

[0044] exist Figure 1 The example used is a boost converter. Those skilled in the art will understand that the light-load efficiency enhancement circuit 100 according to embodiments of this disclosure can also be applied to a buck converter.

[0045] The light-load efficiency enhancement circuit 100 for a DC-DC converter in FCCM mode according to embodiments of the present disclosure can accelerate the switching off of the freewheeling transistor MH and the switching on of the power transistor ML when the DC-DC converter is under light load, and drive the power transistor ML and the freewheeling transistor MH at normal speed under other load conditions. Thus, the DC-DC converter in FCCM mode according to embodiments of the present disclosure can effectively reduce switching losses, improve light-load efficiency, and prevent power transistor breakdown, maintaining the stability of the DC-DC converter.

[0046] Figure 2 A schematic block diagram of a light load determination circuit 210 according to an embodiment of the present disclosure is shown. The light load determination circuit 210 includes: a freewheeling diode current detection circuit 212, a detection result storage circuit 214, a reset circuit 213, and a level conversion circuit 211.

[0047] The freewheeling diode current detection circuit 212 is coupled to the detection result storage circuit 214, the reset circuit 213, and the level conversion circuit 211 via a first node N1. The freewheeling diode current detection circuit 212 is also coupled to the logic control circuit 120, the freewheeling diode current sampling transconductance amplifier Gcs, and the light-load threshold current source Ith. The freewheeling diode current detection circuit 212 is configured to generate a detection signal Dec during the period when the freewheeling diode on-signal MON is at an active level and provide the detection signal Dec to the level conversion circuit 211 and the detection result storage circuit 214 via the first node N1. The detection signal Dec is at an active level when the freewheeling diode sampling current Isns is lower than the light-load threshold current Ith. The detection signal Dec is at an inactive level when the freewheeling diode sampling current Isns is higher than the light-load threshold current Ith. In some embodiments of this disclosure, the freewheeling diode current detection circuit 212 does not generate the detection signal Dec during the period when the freewheeling diode on-signal MON is at an inactive level, therefore the voltage of the first node N1 is at a low level.

[0048] The detection result storage circuit 214 is coupled to the freewheeling diode current detection circuit 212, the reset circuit 213, and the level conversion circuit 211 via the first node N1. The detection result storage circuit 214 is configured to: store the voltage of the first node N1; store the detection signal Dec when the freewheeling diode current detection circuit 212 generates a detection signal Dec; and store a low level when the voltage of the first node N1 is low.

[0049] The reset circuit 213 is coupled to the detection result storage circuit 214, the freewheeling diode current detection circuit 212, and the level conversion circuit 211 via the first node N1. The reset circuit 213 is configured to reset the voltage of the first node N1 to an invalid level when the freewheeling diode conduction signal MON or the clock signal CLK flips to an active level. In some embodiments of this disclosure, the invalid level of the first node N1 is a low level.

[0050] The input of the level conversion circuit 211 is coupled to the detection result storage circuit 214, the reset circuit 213, and the freewheeling diode current detection circuit 212 via a first node N1. The output of the level conversion circuit 211 is also coupled to the logic control circuit 120. The level conversion circuit 211 is configured to convert the effective level of the detection signal Dec to a target level to generate a light load indication signal VY. In some embodiments of this disclosure, the effective level of the detection signal Dec is a high level, and the target level is a level that can be recognized as a high level by the logic control circuit 120.

[0051] refer to Figure 4 At time T1, the duty cycle modulation signal MTR flips to a high level, the power transistor ML turns on and the freewheeling transistor MH turns off, and the inductor current IL begins to rise. At time T2, the clock signal CLK flips to a high level, the power transistor ML turns off and the freewheeling transistor MH turns on, and the inductor current IL begins to decrease. At time T3, the inductor current IL decreases to the light load threshold current Ith (e.g., 0A), the light load indicator signal VY flips to a high level, thereby causing the fast drive indicator signal FT to flip to a high level. Thus, at time T4, when the duty cycle modulation signal MTR flips to a high level again, the turn-off speed of the freewheeling transistor MH and the turn-on speed of the power transistor ML are accelerated, thereby reducing switching losses and improving light load efficiency. At time T5, the clock signal CLK flips to a high level, the freewheeling transistor on signal MON flips to an active level, thereby resetting the light load indicator signal VY and the fast drive indicator signal FT to a low level.

[0052] Figure 3 An exemplary circuit diagram of a light-load efficiency enhancement circuit 300 according to an embodiment of the present disclosure is shown. The light-load determination circuit 310 includes: a freewheeling tube current detection circuit 312, a detection result storage circuit 314, a reset circuit 313, and a level conversion circuit 211.

[0053] The freewheeling diode current detection circuit 312 includes a current comparator COMP and a voltage-controlled switch S1. The first input terminal of the current comparator COMP is provided with a light-load threshold current Ith. The second input terminal of the current comparator COMP is provided with the freewheeling diode sampling current Isns. The output terminal of the current comparator COMP is coupled to the first terminal of the voltage-controlled switch S1. The controlled terminal of the voltage-controlled switch S1 is provided with a freewheeling diode on-signal MON. The second terminal of the voltage-controlled switch S1 is coupled to the first node N1. Figure 3 In the example, the first input of the current comparator COMP is the non-inverting input, and the second input of the current comparator COMP is the inverting input.

[0054] In some embodiments of this disclosure, the first input of the current comparator COMP may be coupled to a light-load threshold current source Ith. The supply voltage of the light-load threshold current source Ith is a first voltage V1 from the first voltage terminal V1. Figure 3 In an alternative embodiment, the voltage-controlled switch S1 can also be replaced by a switching transistor.

[0055] The detection result storage circuit 314 includes a first capacitor Ch1. The first terminal of the first capacitor Ch1 is coupled to a first node N1. The second terminal of the first capacitor Ch1 is coupled to a second voltage terminal V2.

[0056] In some embodiments of this disclosure, the reset circuit 313 includes a first transistor M1. The control electrode of the first transistor M1 is provided with one of a clock signal CLK and a freewheeling diode on signal MON. The first electrode of the first transistor M1 is coupled to a second voltage terminal V2. The second electrode of the first transistor M1 is coupled to a first node N1.

[0057] The freewheeling diode drive circuit 330 includes: a first inverter NG1, a first NAND gate NAND1, a freewheeling diode drive signal generation circuit DHS1, and a freewheeling diode accelerated turn-off drive circuit DHS2. The freewheeling diode drive signal generation circuit DHS1 is configured to generate a freewheeling diode drive signal HG based on the freewheeling diode on-signal MON. When the freewheeling diode on-signal MON is at an active level, the freewheeling diode drive signal HG drives the freewheeling diode MH to turn on. When the freewheeling diode on-signal MON is at an inactive level, the freewheeling diode drive signal HG drives the freewheeling diode MH to turn off. The input terminal of the first inverter NG1 is provided with the freewheeling diode on-signal MON. The output terminal of the first inverter NG1 is coupled to the first input terminal of the first NAND gate NAND1. The second input terminal of the first NAND gate NAND1 is provided with a fast drive indication signal FT. The output terminal of the first NAND gate NAND1 is coupled to the input terminal of the freewheeling diode accelerated turn-off drive circuit DHS2. The freewheeling diode accelerated drive signal FDH is output from the output terminal of the first NAND gate NAND1. The freewheeling diode accelerated turn-off drive circuit DHS2 is configured to increase the toggling speed of the freewheeling diode drive signal HG to accelerate the turn-off speed of the freewheeling diode MH when the freewheeling diode accelerated drive signal FDH is at an active level. In some embodiments of this disclosure, the freewheeling diode accelerated turn-off drive circuit DHS2 may include multiple pull-up transistors, thus increasing the rising slope of the freewheeling diode drive signal HG when a pull-up operation is required on the control electrode of the freewheeling diode, thereby accelerating the turn-off speed of the freewheeling diode MH.

[0058] The power transistor drive circuit 340 includes: a first AND gate AND1, a power transistor drive signal generation circuit DLS1, and a power transistor acceleration turn-on drive circuit DLS2. The power transistor drive signal generation circuit DLS1 is configured to generate a power transistor drive signal LG based on the power transistor turn-on signal SON. When the power transistor turn-on signal SON is at an active level, the power transistor drive signal LG drives the power transistor ML to turn on. When the power transistor turn-on signal SON is at an inactive level, the power transistor drive signal LG drives the power transistor ML to turn off. The first input terminal of the first AND gate AND1 is provided with the power transistor turn-on signal SON. The second input terminal of the first AND gate AND1 is provided with a fast drive indication signal FT. The output terminal of the first AND gate AND1 is coupled to the input terminal of the power transistor acceleration turn-on drive circuit DLS2. The power transistor acceleration drive signal FDL is output from the output terminal of the first AND gate AND1. The power transistor acceleration turn-on drive circuit DLS2 is configured to increase the toggling speed of the power transistor drive signal LG to accelerate the turn-on speed of the power transistor ML when the power transistor acceleration drive signal FDL is at an active level. In some embodiments of this disclosure, the power transistor acceleration drive circuit DLS2 may include multiple pull-up transistors, thereby increasing the rising slope of the power transistor drive signal LG when a pull-up operation is required on the control electrode of the power transistor ML, thereby accelerating the turn-on speed of the power transistor ML.

[0059] exist Figure 3 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 is an NMOS transistor. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0060] refer to Figure 4 At time T1, the duty cycle modulation signal MTR flips to a high level, and the power transistor on signal SON flips to an active level (at...). Figure 3 In the example, it is high level), and the freewheeling diode conduction signal MON toggles to an invalid level (in Figure 3 In the example, the level is low. The active power transistor turn-on signal SON causes the power transistor drive signal generation circuit DLS1 to output a high level, thus turning on the power transistor ML. Since the fast drive indicator signal FT is inactive at this time (in...), the power transistor ML is turned on. Figure 3 In the example, it is low level), therefore the power transistor acceleration drive signal FDL is at an invalid level (in the example, it is low level), so the power transistor acceleration drive signal FDL is at an invalid level (in Figure 3In the example, the signal is low (in this case, the power transistor acceleration drive circuit DLS2 is not working, and it will not accelerate the turn-on speed of the power transistor ML). The freewheeling transistor turn-on signal MON, which is at an invalid level, causes the freewheeling transistor drive signal generation circuit DHS1 to output a high level, thereby turning off the freewheeling transistor MH. Since the fast drive indicator signal FT is at an invalid level at this time (in this case, the fast drive indicator signal FT is at an invalid level), the power transistor ML will not turn on. Figure 3 In the example, it is low level), therefore the freewheeling diode acceleration drive signal FDH is at an invalid level (in Figure 3 In the example, the level is high. The freewheeling diode accelerated turn-off drive circuit DHS2 does not work and will not speed up the turn-off speed of the freewheeling diode MH.

[0061] At time T2, the clock signal CLK toggles to a high level, and the power transistor on signal SON toggles to an inactive level (at...). Figure 3 In the example, it is low level), and the freewheeling diode conduction signal MON toggles to an active level (in Figure 3 (High level in the example). The power transistor turn-on signal SON, which is at an invalid level, causes the power transistor drive signal generation circuit DLS1 to output a low level, thus turning off the power transistor ML. Since the fast drive indicator signal FT and the power transistor turn-on signal SON are at invalid levels at this time, the power transistor acceleration drive signal FDL is also at an invalid level, and the power transistor acceleration turn-on drive circuit DLS2 does not work, thus not affecting the turn-off speed of the power transistor. The freewheeling transistor turn-on signal MON, which is at an active level, causes the freewheeling transistor drive signal generation circuit DHS1 to output a low level, thus turning on the freewheeling transistor MH. Since the inverted signal MONB of the freewheeling transistor turn-on signal MON and the fast drive indicator signal FT are both at invalid levels at this time, the freewheeling transistor acceleration drive signal FDH is also at an invalid level, and the freewheeling transistor acceleration turn-off drive circuit DHS2 does not work, thus not affecting the turn-on speed of the freewheeling transistor.

[0062] Between time T2 and time T4, the freewheeling diode conduction signal MON remains at a high level, so the voltage-controlled switch S1 remains closed.

[0063] At time T3, the inductor current IL drops to the light load threshold current Ith (e.g., 0A), the current comparator COMP outputs a high level, so the light load indication signal VY flips to a high level, thereby causing the fast drive indication signal FT to flip to a high level.

[0064] At time T4, when the duty cycle modulation signal MTR flips to high level again, the power transistor on signal SON flips to an active level (at...). Figure 3 In the example, it is high level), and the freewheeling diode conduction signal MON toggles to an invalid level (in Figure 3In the example, the level is low. The active power transistor turn-on signal SON causes the power transistor drive signal generation circuit DLS1 to output a high level, thus turning on the power transistor ML. Since the fast drive indicator signal FT is active at this time (in...),... Figure 3 In the example, it is high level), therefore the power transistor acceleration drive signal FDL is at an active level (in Figure 3 In the example, the signal is high (high level). The power transistor acceleration drive circuit DLS2 will accelerate the turn-on speed of the power transistor ML. The freewheeling transistor turn-on signal MON, which is at an invalid level, causes the freewheeling transistor drive signal generation circuit DHS1 to output a high level, thereby turning off the freewheeling transistor MH. Since at this time both the inverted signal MONB of the freewheeling transistor turn-on signal MON and the fast drive indicator signal FT are at valid levels (in the example, the signal is high level), the power transistor acceleration drive circuit DLS2 will accelerate the turn-on speed of the power transistor ML. Figure 3 In the example, it is high level), therefore the freewheeling diode acceleration drive signal FDH is at an active level (in Figure 3 (In the example, it is at a low level), the freewheeling diode accelerated turn-off drive circuit DHS2 will accelerate the turn-off speed of the freewheeling diode MH.

[0065] The turn-off speed of the freewheeling diode MH and the turn-on speed of the power diode ML are accelerated, thus reducing switching losses and improving the light-load efficiency of the DC-DC converter in FCCM mode.

[0066] At time T5, the clock signal CLK toggles to a high level, and the freewheeling diode on signal MON toggles to an active level (at...). Figure 3 (In the example, it is high level). The first transistor M1 is turned on, thereby releasing the charge stored at the first terminal of the first capacitor Ch1 to avoid affecting the light load judgment in the next cycle.

[0067] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0068] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0069] In summary, the light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode according to embodiments of this disclosure can accelerate the switching off of the freewheeling transistor and the switching on of the power transistor when the DC-DC converter is under light load, and drive the power transistor and freewheeling transistor at normal speed under other load conditions. Thus, the DC-DC converter in FCCM mode according to embodiments of this disclosure can effectively reduce switching losses, improve light-load efficiency, and prevent power transistor breakdown, maintaining the stability of the DC-DC converter.

[0070] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0071] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0072] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode, comprising: Light load detection circuit, logic control circuit, freewheeling diode drive circuit, and power transistor drive circuit. The light load judgment circuit is configured to generate a light load indication signal based on the freewheeling tube sampling current and the light load threshold current of the DC-DC converter, wherein the effective level of the light load indication signal indicates that the load of the DC-DC converter is light load; The logic control circuit is configured to generate a freewheeling diode turn-on signal and a power diode turn-on signal based on the duty cycle modulation signal and clock signal of the DC-DC converter, and to generate a fast drive indicator signal based on the light load indicator signal. The freewheeling diode drive circuit is configured to accelerate the turn-off speed of the freewheeling diode of the DC-DC converter when the fast drive indication signal is at an active level and the freewheeling diode turn-on signal is at an inactive level. The power transistor drive circuit is configured to accelerate the turn-on speed of the power transistor of the DC-DC converter when both the fast drive indication signal and the power transistor turn-on signal are at valid levels.

2. The light-load efficiency enhancement circuit according to claim 1, wherein, The freewheeling drive circuit is further configured to: drive the freewheeling of the DC-DC converter to turn off at a normal speed when both the fast drive indication signal and the freewheeling turn-on signal are at an invalid level, and drive the freewheeling of the DC-DC converter to turn on at a normal speed when the freewheeling turn-on signal is at an effective level. The power transistor drive circuit is further configured to: drive the power transistor of the DC-DC converter to turn on at a normal speed when the fast drive indication signal is at an invalid level and the power transistor turn-on signal is at an valid level, and drive the power transistor of the DC-DC converter to turn off at a normal speed when the power transistor turn-on signal is at an invalid level.

3. The light-load efficiency enhancement circuit according to claim 1, wherein, The light load judgment circuit includes: a freewheeling diode current detection circuit, a detection result storage circuit, a reset circuit, and a level conversion circuit. The freewheeling diode current detection circuit is configured to generate a detection signal during the period when the freewheeling diode conduction signal is at an effective level and provide the detection signal to the level conversion circuit and the detection result storage circuit via a first node. The detection signal is at an effective level when the freewheeling diode sampling current is lower than the light load threshold current. The detection result storage circuit is configured to store the voltage of the first node; The reset circuit is configured to reset the voltage of the first node to an invalid level when the freewheeling diode conduction signal or the clock signal flips to an active level; The level conversion circuit is configured to convert the effective level of the detection signal into a target level to generate the light load indication signal.

4. The light-load efficiency enhancement circuit according to claim 3, wherein, The freewheeling diode current detection circuit includes: a current comparator and a voltage-controlled switch. The first input terminal of the current comparator is provided with the light load threshold current, the second input terminal of the current comparator is provided with the freewheeling tube sampling current, and the output terminal of the current comparator is coupled to the first terminal of the voltage-controlled switch. The controlled terminal of the voltage-controlled switch is provided with the freewheeling tube conduction signal, and the second terminal of the voltage-controlled switch is coupled to the first node.

5. The light-load efficiency enhancement circuit according to claim 3, wherein, The detection result storage circuit includes: a first capacitor, Wherein, the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second voltage terminal.

6. The light-load efficiency enhancement circuit according to claim 3, wherein, The reset circuit includes: a first transistor, In this configuration, the control electrode of the first transistor is provided with either the clock signal or the freewheeling diode conduction signal; the first electrode of the first transistor is coupled to the second voltage terminal; and the second electrode of the first transistor is coupled to the first node.

7. The light-load efficiency enhancement circuit according to any one of claims 1 to 6, wherein, The freewheeling diode driving circuit includes: a first inverter, a first NAND gate, a freewheeling diode driving signal generation circuit, and a freewheeling diode accelerated turn-off driving circuit. The freewheeling diode drive signal generation circuit is configured to generate a freewheeling diode drive signal based on the freewheeling diode conduction signal, wherein when the freewheeling diode conduction signal is at an active level, the freewheeling diode drive signal drives the freewheeling diode to conduct, and when the freewheeling diode conduction signal is at an inactive level, the freewheeling diode drive signal drives the freewheeling diode to turn off. The input terminal of the first inverter is provided with the freewheeling diode conduction signal, and the output terminal of the first inverter is coupled to the first input terminal of the first NAND gate; The second input terminal of the first NAND gate is provided with the fast drive indication signal, and the output terminal of the first NAND gate is coupled to the input terminal of the freewheeling tube accelerated turn-off drive circuit, and the freewheeling tube accelerated drive signal is output from the output terminal of the first NAND gate. The freewheeling diode accelerated turn-off drive circuit is configured to increase the switching speed of the freewheeling diode drive signal to accelerate the turn-off speed of the freewheeling diode when the freewheeling diode accelerated drive signal is at an effective level.

8. The light-load efficiency enhancement circuit according to any one of claims 1 to 6, wherein, The power transistor drive circuit includes: a first AND gate, a power transistor drive signal generation circuit, and a power transistor acceleration conduction drive circuit. The power transistor drive signal generation circuit is configured to generate a power transistor drive signal based on the power transistor turn-on signal, wherein when the power transistor turn-on signal is at an active level, the power transistor drive signal drives the power transistor to turn on, and when the power transistor turn-on signal is at an inactive level, the power transistor drive signal drives the power transistor to turn off. The first input terminal of the first AND gate is provided with the power transistor turn-on signal, the second input terminal of the first AND gate is provided with the fast drive indication signal, and the output terminal of the first AND gate is coupled to the input terminal of the power transistor acceleration turn-on drive circuit, and the power transistor acceleration drive signal is output from the output terminal of the first AND gate. The power transistor acceleration drive circuit is configured to increase the switching speed of the power transistor drive signal to accelerate the turn-on speed of the power transistor when the power transistor acceleration drive signal is at an effective level.

9. A light-load efficiency enhancement circuit for a DC-DC converter in FCCM mode, comprising: The circuit includes a logic control circuit, a current comparator, a voltage-controlled switch, a first capacitor, a first transistor, a buffer, a first inverter, a first NAND gate, a freewheeling diode drive signal generation circuit, a freewheeling diode accelerated turn-off drive circuit, a first AND gate, a power transistor drive signal generation circuit, and a power transistor accelerated turn-on drive circuit. The logic control circuit is configured to generate a freewheeling diode turn-on signal and a power diode turn-on signal based on the duty cycle modulation signal and clock signal of the DC-DC converter, and to generate a fast drive indicator signal based on the light load indicator signal output from the buffer. The first input terminal of the current comparator is provided with a light-load threshold current, the second input terminal of the current comparator is provided with the freewheeling tube sampling current of the DC-DC converter, and the output terminal of the current comparator is coupled to the first terminal of the voltage-controlled switch. The controlled terminal of the voltage-controlled switch is provided with the freewheeling tube conduction signal, and the second terminal of the voltage-controlled switch is coupled to the first terminal of the first capacitor; The second terminal of the first capacitor is coupled to the second voltage terminal; The control electrode of the first transistor is provided with one of the clock signal and the freewheeling diode conduction signal, the first electrode of the first transistor is coupled to the second voltage terminal, and the second electrode of the first transistor is coupled to the first terminal of the first capacitor; The buffer is configured to convert a first level at the first terminal of the first capacitor into a target level to generate the light load indication signal; The freewheeling diode drive signal generation circuit is configured to generate a freewheeling diode drive signal based on the freewheeling diode conduction signal, wherein when the freewheeling diode conduction signal is at an active level, the freewheeling diode drive signal drives the freewheeling diode of the DC-DC converter to conduct, and when the freewheeling diode conduction signal is at an inactive level, the freewheeling diode drive signal drives the freewheeling diode to turn off. The input terminal of the first inverter is provided with the freewheeling diode conduction signal, and the output terminal of the first inverter is coupled to the first input terminal of the first NAND gate; The second input terminal of the first NAND gate is provided with the fast drive indication signal, and the output terminal of the first NAND gate is coupled to the input terminal of the freewheeling tube accelerated turn-off drive circuit, and the freewheeling tube accelerated drive signal is output from the output terminal of the first NAND gate. The freewheeling diode accelerated turn-off drive circuit is configured to: when the freewheeling diode accelerated drive signal is at an effective level, increase the switching speed of the freewheeling diode drive signal to accelerate the turn-off speed of the freewheeling diode. The power transistor drive signal generation circuit is configured to generate a power transistor drive signal based on the power transistor turn-on signal, wherein when the power transistor turn-on signal is at an active level, the power transistor drive signal drives the power transistor to turn on, and when the power transistor turn-on signal is at an inactive level, the power transistor drive signal drives the power transistor to turn off. The first input terminal of the first AND gate is provided with the power transistor turn-on signal, the second input terminal of the first AND gate is provided with the fast drive indication signal, and the output terminal of the first AND gate is coupled to the input terminal of the power transistor acceleration turn-on drive circuit, and the power transistor acceleration drive signal is output from the output terminal of the first AND gate. The power transistor acceleration drive circuit is configured to increase the switching speed of the power transistor drive signal to accelerate the turn-on speed of the power transistor when the power transistor acceleration drive signal is at an effective level.

10. A DC-DC converter, comprising: The light-load efficiency enhancement circuit according to any one of claims 1 to 9, wherein the DC-DC converter operates in FCCM mode.

Images