Transmitter circuit

Abstract

A transmitter circuit has an input port, a first transmission node, a second transmission node, a third transmission node, and a fourth transmission node, and includes a first operational amplifier, a first output stage, a first resistor capacitor network, a first switch group coupled between the first resistor capacitor network and the input port, a first impedance matching circuit coupled the first output stage, the first transmission node, and the second transmission node, a second operational amplifier, a second output stage, a second resistor capacitor network, a second switch group coupled between the second resistor capacitor network and the input port, and a second impedance matching circuit coupled the second output stage, the third transmission node, and the fourth transmission node.

Description

Technical Field

[0001] This invention relates to Ethernet networks, and more particularly to transmitter circuits for Ethernet networks. Background Technology

[0002] Figure 1 shows a functional block diagram of an existing Ethernet transmitter. The transmitter circuit 101 includes a first channel and a second channel.

[0003] The first channel includes an operational amplifier 104_t, an output stage 130_t, a resistor-capacitor circuit 110_t, a resistor-capacitor circuit 120_t, an impedance matching circuit 140_t, and a switched resistor network 146_t. The resistor-capacitor circuit 110_t is coupled between the output terminal of the output stage 130_t (one end of the output signal vop_t) and the input terminal of the operational amplifier 104_t (one end of the received signal vip_t). The resistor-capacitor circuit 120_t is coupled between the output terminal of the output stage 130_t (one end of the output signal von_t) and the input terminal of the operational amplifier 104_t (one end of the received signal vin_t). The impedance matching circuit 140_t includes switched resistor networks 142_t and 144_t. Switched resistor network 142_t is coupled between the output of output stage 130_t and transmitting node txop, while switched resistor network 144_t is coupled between the output of output stage 130_t and transmitting node txon. Transmitting node txop and transmitting node txon are coupled to load resistor RL1 through transformer 150_t.

[0004] The second channel includes an operational amplifier 104_r, an output stage 130_r, a resistor-capacitor circuit 110_r, a resistor-capacitor circuit 120_r, an impedance matching circuit 140_r, and a switched resistor network 146_r. The resistor-capacitor circuit 110_r is coupled between the output terminal of the output stage 130_r (one end of the output signal vop_r) and the input terminal of the operational amplifier 104_r (one end of the received signal vip_r). The resistor-capacitor circuit 120_r is coupled between the output terminal of the output stage 130_r (one end of the output signal von_r) and the input terminal of the operational amplifier 104_r (one end of the received signal vin_r). The impedance matching circuit 140_r includes switched resistor networks 142_r and 144_r. Switched resistor network 142_r is coupled between the output of output stage 130_r and transmitting node rxip, while switched resistor network 144_r is coupled between the output of output stage 130_r and transmitting node rxin. Transmitting node rxip and transmitting node rxin are coupled to load resistor RL2 via transformer 150_r.

[0005] Of the components mentioned above, transformer 150_t, transformer 150_r, load resistor RL1, and load resistor RL2 are located outside the chip, while the other components are located inside the chip.

[0006] When the transmitter circuit 101 operates in medium dependent interface (MDI) mode, the operational amplifier 104_t, output stage 130_t, resistor-capacitor circuit 110_t, and resistor-capacitor circuit 120_t are enabled; the operational amplifier 104_r, output stage 130_r, resistor-capacitor circuit 110_r, and resistor-capacitor circuit 120_r are disabled; the switched resistor network 142_t, switched resistor network 144_t, and switched resistor network 146_r are shorted; and the switched resistor network 142_r, switched resistor network 144_r, and switched resistor network 146_t are open. The transmitter circuit 101 outputs the signals generated by the digital-to-analog converter 102_t (signal vip_t and signal vin_t) from the transmit node txop and transmit node txon.

[0007] When transmitter circuit 101 operates in medium dependent interface crossover (MDIX) mode, operational amplifier 104_t, output stage 130_t, resistor-capacitor circuit 110_t, and resistor-capacitor circuit 120_t are disabled; operational amplifier 104_r, output stage 130_r, resistor-capacitor circuit 110_r, and resistor-capacitor circuit 120_r are enabled; switched resistor network 142_t, switched resistor network 144_t, and switched resistor network 146_r are open-circuited; switched resistor network 142_r, switched resistor network 144_r, and switched resistor network 146_t are short-circuited; and transmitter circuit 101 outputs the signals generated by digital-to-analog converter 102_r (signal vip_r and signal vin_r) from transmitter node rxip and transmitter node rxin.

[0008] Due to process drift, switched resistor networks 142_t, 144_t, 142_r, and 144_r typically require calibration. Figure 2 shows a schematic diagram of switched resistor network 142_t (the circuits of switched resistor networks 144_t, 142_r, and 144_r are similar). The traditional calibration method involves providing multiple parallel resistor (R0~Rn)-switch (SW0~SWn) pairs, generating different equivalent resistance values ​​by controlling the conduction states of these switches (SW0~SWn). In Figure 2, switches SW0~SWn are implemented using transmission gates, and signals powb_h, pow_h, tap_h, and tapb_h are the control signals for these transmission gates.

[0009] In transmitter circuit 101, switch SWp_t can be used to control the switching resistor network 142_t to form a short circuit (switch SWp_t is on) or an open circuit (switch SWp_t is not on). However, transmission gates manufactured using advanced processes have lower withstand voltage and cannot withstand high voltages. Therefore, existing switching resistor networks 142_t, 144_t, 142_r, and 144_r are not suitable for advanced processes. In other words, resistor networks 142_t, 144_t, 142_r, and 144_r manufactured using advanced processes cannot be practically switched. Therefore, a transmitter circuit that can still be switched (achieve the switching purpose) in advanced processes is needed. Summary of the Invention

[0010] In view of the shortcomings of the prior art, one object of the present invention is to provide a transmitter circuit to improve upon the shortcomings of the prior art.

[0011] An embodiment of the present invention provides a transmitter circuit having an input port, a first transmitting node, a second transmitting node, a third transmitting node, and a fourth transmitting node, and comprising: a first operational amplifier; a first output stage coupled to the first operational amplifier; a first resistor-capacitor network coupled to the first output stage and the first operational amplifier; a first switch group coupled between the first resistor-capacitor network and the input port; a first impedance matching circuit coupled to the first output stage, the first transmitting node, and the second transmitting node; a second operational amplifier; a second output stage coupled to the second operational amplifier; a second resistor-capacitor network coupled to the second output stage and the second operational amplifier; a second switch group coupled between the second resistor-capacitor network and the input port; and a second impedance matching circuit coupled to the second output stage, the third transmitting node, and the fourth transmitting node.

[0012] Another embodiment of the present invention provides a transmitter circuit having a first transmitting node, a second transmitting node, a third transmitting node, and a fourth transmitting node, and comprising: an operational amplifier; a first output stage coupled to the operational amplifier; a first resistor-capacitor network coupled to the first output stage; a first switch group coupled between the first resistor-capacitor network and the operational amplifier; a first impedance matching circuit coupled to the first output stage, the first transmitting node, and the second transmitting node; a second output stage coupled to the operational amplifier; a second resistor-capacitor network coupled to the second output stage; a second switch group coupled between the second resistor-capacitor network and the operational amplifier; a second impedance matching circuit coupled to the second output stage, the third transmitting node, and the fourth transmitting node; a common-mode feedback circuit; a first switch coupled between the common-mode feedback circuit and the first output stage; and a second switch coupled between the common-mode feedback circuit and the second output stage.

[0013] Compared to prior art, the transmitter circuit of the present invention can be manufactured using advanced processes, solving the problems encountered by prior art.

[0014] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1 shows a functional block diagram of an existing Ethernet transmitter;

[0016] Figure 2 is a schematic diagram of an existing switched resistor network.

[0017] Figure 3 A functional block diagram showing an embodiment of the Ethernet transmitter of the present invention; and

[0018] Figure 4 A functional block diagram showing another embodiment of the Ethernet transmitter of the present invention is shown. Detailed Implementation

[0019] The technical terms used in the following description refer to the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0020] The present invention discloses a transmitter circuit. Since some components of the transmitter circuit of the present invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0021] Please see Figure 3 , Figure 3This diagram shows a functional block diagram of an embodiment of the Ethernet transmitter of the present invention. The transmitter circuit 301 includes an input port 303 (including input nodes Ni1 and Ni2), a first channel, and a second channel.

[0022] The first channel receives input signals (e.g., signals vip and vin output by the digital-to-analog converter 302) from input port 303 and outputs signals from transmitting node txop and transmitting node txon.

[0023] The first channel includes an operational amplifier 304_t, a resistor-capacitor network 315_t (including resistor-capacitor circuits 310_t and 320_t), an output stage 330_t, an impedance matching circuit 340_t (including resistors 342_t and 344_t), a switched resistor network 346_t, and a switch group 360_t (including switches 361_t and 362_t). The impedance matching circuit 340_t does not include switches.

[0024] Operational amplifier 304_t is coupled or electrically connected to output stage 330_t. Resistor-capacitor network 315_t is coupled between the output terminal of output stage 330_t and the input terminal of operational amplifier 304_t. One end of resistor-capacitor circuit 310_t is coupled or electrically connected to one of the output terminals of output stage 330_t (one end of the output signal vop_t), and the other end of resistor-capacitor circuit 310_t is coupled or electrically connected to one of the input terminals of operational amplifier 304_t and switch 361_t. One end of resistor-capacitor circuit 320_t is coupled or electrically connected to the other output terminal of output stage 330_t (one end of the output signal von_t), and the other end of resistor-capacitor circuit 320_t is coupled or electrically connected to the other input terminal of operational amplifier 304_t and switch 362_t.

[0025] One end of resistor 342_t is coupled or electrically connected to one output terminal of output stage 330_t (one end of output signal vop_t), and the other end of resistor 342_t is coupled or electrically connected to transmitting node txop. One end of resistor 344_t is coupled or electrically connected to the output terminal of output stage 330_t (one end of output signal von_t), and the other end of resistor 344_t is coupled or electrically connected to transmitting node txon. Switched resistor network 346_t is coupled or electrically connected between transmitting node txop and transmitting node txon. Transmitting node txop and transmitting node txon are coupled to load resistor RL1 through transformer 350_t.

[0026] Switch group 360_t is coupled between input port 303 and the input terminal of operational amplifier 304_t. Switch 361_t is coupled or electrically connected between input node Ni1 and one of the input terminals of operational amplifier 304_t (coupled or electrically connected to that input terminal of resistor-capacitor circuit 310_t). Switch 362_t is coupled or electrically connected between input node Ni2 and the other input terminal of operational amplifier 304_t (coupled or electrically connected to that input terminal of resistor-capacitor circuit 320_t).

[0027] The second channel receives input signals (e.g., signals vip and vin) from input port 303 and outputs signals from transmitting node rxip and transmitting node rxin.

[0028] The second channel includes an operational amplifier 304_r, a resistor-capacitor network 315_r (including resistor-capacitor circuits 310_r and 320_r), an output stage 330_r, an impedance matching circuit 340_r (including resistors 342_r and 344_r), a switched resistor network 346_r, and a switch group 360_r (including switches 361_r and 362_r). The impedance matching circuit 340_r does not include switches.

[0029] Operational amplifier 304_r is coupled or electrically connected to output stage 330_r. Resistor-capacitor network 315_r is coupled between the output terminal of output stage 330_r and the input terminal of operational amplifier 304_r. One end of resistor-capacitor circuit 310_r is coupled or electrically connected to one of the output terminals of output stage 330_r (one end of the output signal vop_r), and the other end of resistor-capacitor circuit 310_r is coupled or electrically connected to one of the input terminals of operational amplifier 304_r and switch 361_r. One end of resistor-capacitor circuit 320_r is coupled or electrically connected to the other output terminal of output stage 330_r (one end of the output signal von_r), and the other end of resistor-capacitor circuit 320_r is coupled or electrically connected to the other input terminal of operational amplifier 304_r and switch 362_r.

[0030] One end of resistor 342_r is coupled or electrically connected to one of the output terminals of output stage 330_r (one end of the output signal vop_r), and the other end of resistor 342_r is coupled or electrically connected to transmitting node rxip. One end of resistor 344_r is coupled or electrically connected to the output terminal of output stage 330_r (one end of the output signal von_r), and the other end of resistor 344_r is coupled or electrically connected to transmitting node rxin. Switched resistor network 346_r is coupled or electrically connected between transmitting node rxip and transmitting node rxin. Transmitting node rxip and transmitting node rxin are coupled to load resistor RL2 through transformer 350_r.

[0031] Switch group 360_r is coupled between input port 303 and the input terminal of operational amplifier 304_r. Switch 361_r is coupled or electrically connected between input node Ni1 and one of the input terminals of operational amplifier 304_r (coupled or electrically connected to that input terminal of resistor-capacitor circuit 310_r). Switch 362_r is coupled or electrically connected between input node Ni2 and the other input terminal of operational amplifier 304_r (coupled or electrically connected to that input terminal of resistor-capacitor circuit 320_r).

[0032] When transmitter circuit 301 operates in MDI mode, operational amplifier 304_t, output stage 330_t, resistor-capacitor circuit 310_t, resistor-capacitor circuit 320_t, resistor 342_t, resistor 344_t, and switched resistor network 346_r are enabled; operational amplifier 304_r, output stage 330_r, resistor-capacitor circuit 310_r, resistor-capacitor circuit 320_r, resistor 342_r, resistor 344_r, and switched resistor network 346_t are disabled; switch group 360_t is turned on (i.e., switches 361_t and 362_t are turned on), and switch group 360_r is not turned on (i.e., switches 361_r and 362_r are not turned on). In MDI mode, transmitter circuit 301 transmits the signals vip and vin output by digital-to-analog converter 302 through transmit node txop and transmit node txon.

[0033] When transmitter circuit 301 operates in MDIX mode, operational amplifier 304_t, output stage 330_t, resistor-capacitor circuit 310_t, resistor-capacitor circuit 320_t, resistor 342_t, resistor 344_t, and switched resistor network 346_r are disabled. Operational amplifier 304_r, output stage 330_r, resistor-capacitor circuit 310_r, resistor-capacitor circuit 320_r, resistor 342_r, resistor 344_r, and switched resistor network 346_t are enabled. Switch group 360_t is not conducting (i.e., switches 361_t and 362_t are not conducting), and switch group 360_r is conducting (i.e., switches 361_r and 362_r are conducting). In MDIX mode, transmitter circuit 301 transmits the signals vip and vin output by digital-to-analog converter 302 through transmit node rxip and transmit node rxin.

[0034] Operational amplifiers 304_t and 304_r each include a common mode feedback (CMFB) circuit. The details and operating principle of the common mode feedback circuit are well known to those skilled in the art, and therefore will not be described in detail.

[0035] Figure 3 In the components, transformer 350_t, transformer 350_r, load resistor RL1 and load resistor RL2 are located outside the chip, while other components are located inside the chip.

[0036] By controlling the on / off states of switches 361_t, 362_t, 361_r, and 362_r, the transmitter circuit 301 operates in MDI or MDIX mode. Switches 361_t, 362_t, 361_r, and 362_r can be implemented using transistors. Since switches 361_t, 362_t, 361_r, and 362_r do not withstand large signal amplitudes (i.e., do not withstand high voltages), the transmitter circuit 301 can be manufactured using advanced processes. Of course, the transmitter circuit 301 can also be manufactured using conventional processes. Furthermore, compared to the transmitter circuit 101 of FIG. 1, the first and second channels of the transmitter circuit 301 of the present invention share a digital-to-analog converter 302, which can reduce circuit area and save costs.

[0037] Please see Figure 4 , Figure 4 A functional block diagram showing another embodiment of the Ethernet transmitter of the present invention is shown. Figure 4The transmitter circuit 401 is similar to the transmitter circuit 301, except that the first and second channels of the transmitter circuit 401 share the operational amplifier 404. The outputs of the operational amplifier 404 are both coupled or electrically connected to output stage 330_t and output stage 330_r. One input terminal of the operational amplifier 404 (the input terminal of the received signal vip, i.e., input node Ni1) is coupled to resistor-capacitor circuit 310_t via switch 361_t, and to resistor-capacitor circuit 310_r via switch 361_r; the other input terminal of the operational amplifier 404 (the input terminal of the received signal vin, i.e., input node Ni2) is coupled to resistor-capacitor circuit 320_t via switch 362_t, and to resistor-capacitor circuit 320_r via switch 362_r.

[0038] Because the operational amplifier 404 is shared, the common-mode feedback circuit 406 of the operational amplifier 404 must switch between the first channel and the second channel. For example... Figure 4 As shown, the common-mode feedback circuit 406 is coupled or electrically connected to switches 464_t and 464_r. Switch 464_t is coupled to node N1 (i.e., one of the output terminals of output stage 330_t) through resistor Rt1, and to node N2 (i.e., the other output terminal of output stage 330_t) through resistor Rt2. Switch 464_r is coupled to node N3 (i.e., one of the output terminals of output stage 330_r) through resistor Rr1, and to node N4 (i.e., the other output terminal of output stage 330_r) through resistor Rr2. The details and operating principles of the common-mode feedback circuit 406 are well known to those skilled in the art and will not be described further.

[0039] When the transmitter circuit 401 operates in MDI mode, the operational amplifier 404 is enabled, switches 361_t, 362_t, and 464_t are turned on, and switches 361_r, 362_r, and 464_r are not turned on; when the transmitter circuit 401 operates in MDIX mode, the operational amplifier 404 is enabled, switches 361_t, 362_t, and 464_t are not turned on, and switches 361_r, 362_r, and 464_r are turned on.

[0040] The transmitter circuit 401 can also be manufactured using advanced or conventional processes. Furthermore, compared to the transmitter circuit 301, the transmitter circuit 401 further shares the operational amplifier 404, thus reducing circuit area and cost.

[0041] Please note that the shapes, sizes, and proportions of the components in the previously disclosed icons are merely illustrative and intended to help those skilled in the art understand the present invention, and are not intended to limit the present invention.

[0042] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 101, 301, 401: Transmitter circuits

[0045] 104_t, 104_r, 304_t, 304_r, 404: Operational amplifiers

[0046] 130_t, 130_r, 330_t, 330_r: Output stage

[0047] 110_t, 120_t, 110_r, 120_r, 310_t, 320_t, 310_r, 320_r: Resistor-capacitor circuit

[0048] 140_t, 140_r, 340_t, 340_r: Impedance matching circuit

[0049] vop_t, vip_t, von_t, vin_t, vop_r, vip_r, von_r, vin_r, vip, vin: signals

[0050] powb_h, pow_h, tap_h, tapb_h: Control signals

[0051] 142_t, 144_t, 146_t, 142_r, 144_r, 146_r, 346_t, 346_r: Switched Resistor Network

[0052] 150_t, 150_r, 350_t, 350_r: Transformers

[0053] RL1, RL2: Load resistors

[0054] txop, txon, rxip, rxin: Sending nodes

[0055] 102_t, 102_r, 302: Digital-to-Analog Converters

[0056] SW0, SW1, SW2, SWn, SWp_t, 361_t, 362_t, 361_r, 362_r, 464_t, 464_r: switch

[0057] 303: Input Port

[0058] Ni1, Ni2: Input nodes

[0059] 315_t, 315_r: Resistor-capacitor network

[0060] R0, R1, R2, Rn, 342_t, 344_t, 342_r, 344_r, Rt1, Rt2, Rr1, Rr2: Resistors

[0061] 360_t, 360_r: Switch groups

[0062] 406: Common-mode feedback circuit

[0063] N1, N2, N3, N4: Nodes

Claims

1. A transmitter circuit having an input port, a first transmitting node, a second transmitting node, a third transmitting node, and a fourth transmitting node, the transmitter circuit comprising: First operational amplifier; The first output stage is coupled to the first operational amplifier; A first resistor-capacitor network is coupled to the first output stage and the first operational amplifier; A first switch group is coupled between the first resistor-capacitor network and the input port; A first impedance matching circuit is coupled to the first output stage, the first transmitting node, and the second transmitting node; Second operational amplifier; The second output stage is coupled to the second operational amplifier; A second resistor-capacitor network is coupled to the second output stage and the second operational amplifier; The second switch group is coupled between the second resistor-capacitor network and the input port; as well as The second impedance matching circuit is coupled to the second output stage, the third transmitting node, and the fourth transmitting node.

2. The transmitter circuit according to claim 1, wherein, The first resistor-capacitor network includes a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network includes a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.

3. The transmitter circuit according to claim 2, wherein, The input port includes a first input node and a second input node. The first switch group includes a first switch and a second switch. The second switch group includes a third switch and a fourth switch. The first switch is coupled between the first input node and the first resistor-capacitor circuit. The second switch is coupled between the second input node and the second resistor-capacitor circuit. The third switch is coupled between the first input node and the third resistor-capacitor circuit. The fourth switch is coupled between the second input node and the fourth resistor-capacitor circuit.

4. The transmitter circuit according to claim 1, wherein, The first impedance matching circuit includes a first resistor and a second resistor, and the second impedance matching circuit includes a third resistor and a fourth resistor. The first resistor is coupled between the first output stage and the first transmitting node, the second resistor is coupled between the first output stage and the second transmitting node, the third resistor is coupled between the second output stage and the third transmitting node, and the fourth resistor is coupled between the second output stage and the fourth transmitting node.

5. The transmitter circuit according to claim 1, wherein, The first impedance matching circuit and the second impedance matching circuit do not include switches.

6. A transmitter circuit having a first transmitting node, a second transmitting node, a third transmitting node, and a fourth transmitting node, the transmitter circuit comprising: Operational amplifier; The first output stage is coupled to the operational amplifier; A first resistor-capacitor network is coupled to the first output stage; A first switch group is coupled between the first resistor-capacitor network and the operational amplifier; A first impedance matching circuit is coupled to the first output stage, the first transmitting node, and the second transmitting node; The second output stage is coupled to the operational amplifier; The second resistor-capacitor network is coupled to the second output stage; The second switch group is coupled between the second resistor-capacitor network and the operational amplifier; The second impedance matching circuit is coupled to the second output stage, the third transmitting node, and the fourth transmitting node; Common-mode feedback circuit; The first switch is coupled between the common-mode feedback circuit and the first output stage; as well as The second switch is coupled between the common-mode feedback circuit and the second output stage.

7. The transmitter circuit according to claim 6, wherein, The first resistor-capacitor network includes a first resistor-capacitor circuit and a second resistor-capacitor circuit, and the second resistor-capacitor network includes a third resistor-capacitor circuit and a fourth resistor-capacitor circuit.

8. The transmitter circuit according to claim 7, wherein, The operational amplifier has a first input terminal and a second input terminal. The first switch group includes a third switch and a fourth switch, and the second switch group includes a fifth switch and a sixth switch. The third switch is coupled between the first input terminal of the operational amplifier and the first resistor-capacitor circuit. The fourth switch is coupled between the second input terminal of the operational amplifier and the second resistor-capacitor circuit. The fifth switch is coupled between the first input terminal of the operational amplifier and the third resistor-capacitor circuit. The sixth switch is coupled between the second input terminal of the operational amplifier and the fourth resistor-capacitor circuit.

9. The transmitter circuit according to claim 6, wherein, The first impedance matching circuit includes a first resistor and a second resistor, and the second impedance matching circuit includes a third resistor and a fourth resistor. The first resistor is coupled between the first output stage and the first transmitting node, the second resistor is coupled between the first output stage and the second transmitting node, the third resistor is coupled between the second output stage and the third transmitting node, and the fourth resistor is coupled between the second output stage and the fourth transmitting node.

10. The transmitter circuit according to claim 6, wherein, The first impedance matching circuit and the second impedance matching circuit do not include switches.

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