A UART interaction system and method in half-duplex mode

Abstract

This invention discloses a UART interaction system and method in half-duplex mode, comprising: first and second UARTs and pull-up control circuits; the first and second UARTs respectively include first and second TX pins, first and second RX pins, first and second data transmission and reception controllers, first and second forced transmission control registers, and first and second I / O ports; the first data transmission and reception controllers are electrically connected to the first TX pin and the first RX pin respectively, the first I / O port is electrically connected to the first TX pin and the first RX pin respectively, and the first and second forced transmission control registers are electrically connected to the first and second data transmission and reception controllers respectively; the second data transmission and reception controllers are electrically connected to the second TX pin and the second RX pin respectively, and the second I / O port is electrically connected to the second TX pin and the second RX pin respectively; and the pull-up control circuit is electrically connected to the first and second I / O ports respectively.

Description

Technical Field

[0001] This invention relates to the field of UART communication technology, and more specifically to a UART interaction system and method in half-duplex mode. Background Technology

[0002] UART devices are widely used for data transmission and generally operate in full-duplex mode. The data port includes TX and RX, where TX is the data transmission port and RX is the data reception port. However, in some applications, due to limitations in the number of available ports and the characteristics of the connected devices, UART devices may need to operate in half-duplex mode. In this mode, TX and RX share a single port, and the port's functionality—whether for data transmission or reception—is determined by software configuration; simultaneous transmission and reception are not possible.

[0003] Since UART data transmission generally occurs between asynchronous systems, software is required to control the direction of data transmission. For example, after the sending end finishes sending data to the receiving end, when it needs to receive data, it can send a specific signal frame to inform the receiving end that the data transmission is complete and it is ready to receive data. After that, the sending end switches to the receiving end, and the receiving end switches to the sending end. Figure 1 This is a schematic diagram of data transmission waveforms in existing technologies. Figure 1 Taking data transmission from the first UART to the second UART as an example, data transmission can only maintain one direction for a period of time. To ensure the reliability of data transmission, it is generally necessary to ensure that one party has completed sending data and notifies the other party of the completion of data transmission through a suitable handshake protocol before switching the data transmission direction. Even if the second UART has higher priority data that needs to be transmitted to the first UART midway, such as data verification errors, it must wait for the first UART to complete its transmission before it can proceed.

[0004] While the above methods partially solve the problem of data transmission direction in applications, their drawback is that control of the port can only be transferred after the sending end has completed data transmission, resulting in poor flexibility and potential bandwidth waste. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention provides a UART interaction system and method in half-duplex mode, which solves the technical problems of poor flexibility and easy bandwidth waste when existing UART devices transmit data in half-duplex mode, thereby achieving the purpose of flexibly switching directions during data transmission and improving bandwidth utilization efficiency.

[0006] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0007] A UART interaction system in half-duplex mode includes:

[0008] The first UART includes a first TX pin, a first RX pin, a first data transmit / receive controller, a first forced transmit control register, and a first I / O port. The first data transmit / receive controller is electrically connected to the first TX pin and the first RX pin, respectively. The first I / O port is electrically connected to the first TX pin and the first RX pin, respectively. The first forced transmit control register is electrically connected to the first data transmit / receive controller.

[0009] The second UART includes a second TX pin, a second RX pin, a second data transmit / receive controller, a second forced transmit control register, and a second I / O port. The second data transmit / receive controller is electrically connected to the second TX pin and the second RX pin, respectively. The second I / O port is electrically connected to the second TX pin and the second RX pin, respectively. The second forced transmit control register is electrically connected to the second data transmit / receive controller.

[0010] The pull-up control circuit is electrically connected to the first I / O port and the second I / O port respectively;

[0011] The first UART and the second UART are connected through the first IO port and the second IO port.

[0012] In a preferred embodiment of the present invention, the first data transmission and reception controller is responsible for controlling the enable control of the first TX pin and the first RX pin, and processing the data during transmission and reception; the second data transmission and reception controller is responsible for controlling the enable control of the second TX pin and the second RX pin, and processing the data during transmission and reception.

[0013] In a preferred embodiment of the present invention, the first forced transmission control register is used to set whether the first UART performs forced transmission; the second forced transmission control register is used to set whether the second UART performs forced transmission.

[0014] Specifically, if the first forced transmission control register is enabled, the first UART can perform forced transmission; if the second forced transmission control register is enabled, the second UART can perform forced transmission; if the first forced transmission control register is disabled, the first UART cannot perform forced transmission; and if the second forced transmission control register is disabled, the second UART cannot perform forced transmission.

[0015] In a preferred embodiment of the present invention, if the first forced transmission control register is enabled and the second forced transmission control register is disabled, the first UART can terminate the transmission process of the second UART, and the second UART cannot terminate the transmission process of the first UART.

[0016] In a preferred embodiment of the present invention, if the first forced transmission control register is set to disabled and the second forced transmission control register is set to enabled, the first UART cannot terminate the transmission process of the second UART, and the second UART can terminate the transmission process of the first UART.

[0017] In a preferred embodiment of the present invention, if the first forced transmission control register is enabled and the second forced transmission control register is enabled, the first UART can terminate the transmission process of the second UART, and the second UART can terminate the transmission process of the first UART.

[0018] In a preferred embodiment of the present invention, if the first forced transmission control register is set to disabled and the second forced transmission control register is set to disabled, the first UART cannot terminate the transmission process of the second UART, and the second UART cannot terminate the transmission process of the first UART.

[0019] In a preferred embodiment of the present invention, the pull-up control circuit is used to maintain the high potential of the first IO port and the second IO port, and the impedance of the pull-up control circuit is greater than the output impedance when the first TX pin and the second TX pin are enabled.

[0020] A UART interaction method in half-duplex mode, based on the above system, includes the following steps:

[0021] The first UART data is sequentially transmitted to the second UART in several data bits and one stop bit through the first UART;

[0022] The second UART sequentially collects the data bits and the stop bit until the stop bit is collected, and then determines whether the second UART has any data to send.

[0023] If so, the second UART data is sent directly through the second UART, and the level of the second IO port is reduced;

[0024] If the first UART detects a drop in the level of the second IO port, it is considered that the second UART has data to send, and it is determined whether the first UART has a next frame of first UART data to send;

[0025] If so, the first UART stops sending the next frame of first UART data and receives the second UART data through the first UART;

[0026] The first UART data includes the plurality of data bits and the stop bit, the first forced transmit control register in the first UART is set to disabled, and the second forced transmit control register in the second UART is set to enabled.

[0027] In a preferred embodiment of the present invention, when transmitting a stop bit to the second UART via the first UART, the following is included:

[0028] When the stop bit is started to be sent, the output enable signal of the first UART is kept at a high level until a few clock cycles before the center of the stop bit is reached, the output enable signal of the first UART is lowered to a low level, and the first TX pin stops outputting to the first IO port.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] (1) The present invention does not require additional signal control and can be effectively compatible with existing software control schemes;

[0031] (2) The present invention can switch the data transmission direction in a timely and accurate manner, and its functions are configurable and have strong flexibility.

[0032] (3) Compared with existing software control schemes, the present invention can effectively avoid bandwidth waste.

[0033] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0034] Figure 1 - This is a schematic diagram of the data transmission waveform of the prior art in the background art of this invention;

[0035] Figure 2 - is a schematic diagram of the structure of a UART interaction system in half-duplex mode according to an embodiment of the present invention;

[0036] Figure 3 - This is a schematic diagram of the data transmission waveform of the UART interaction method in half-duplex mode according to an embodiment of the present invention;

[0037] Figure 4 - This is a schematic diagram of the 16x oversampled UART clock in the half-duplex mode of the UART interaction method according to an embodiment of the present invention;

[0038] Figure 5 - This is a flowchart illustrating the steps of the UART interaction method in half-duplex mode according to an embodiment of the present invention.

[0039] The following diagrams are labeled as follows: 1. First UART; 2. Second UART; 3. Pull-up control circuit; 4. First TX pin; 5. First RX pin; 6. First data transmit / receive controller; 7. First forced transmit control register; 8. First I / O port; 9. Second TX pin; 10. Second RX pin; 11. Second data transmit / receive controller; 12. Second forced transmit control register; 13. Second I / O port. Detailed Implementation

[0040] The UART interaction system in half-duplex mode provided by this invention, such as Figure 2 As shown, it includes: a first UART 1, a second UART 2, and a pull-up control circuit 3.

[0041] like Figure 2 As shown, the first UART 1 includes a first TX pin 4, a first RX pin 5, a first data transmit / receive controller 6, a first forced transmit control register 7, and a first I / O port 8. The first data transmit / receive controller 6 is electrically connected to the first TX pin 4 and the first RX pin 5, respectively. The first I / O port 8 is electrically connected to the first TX pin 4 and the first RX pin 5, respectively. The first forced transmit control register 7 is electrically connected to the first data transmit / receive controller 6.

[0042] like Figure 2 As shown, the second UART 2 includes a second TX pin 9, a second RX pin 10, a second data transmit / receive controller 11, a second forced transmit control register 12, and a second I / O port 13. The second data transmit / receive controller 11 is electrically connected to the second TX pin 9 and the second RX pin 10, respectively. The second I / O port 13 is also electrically connected to the second TX pin 9 and the second RX pin 10, respectively. The second forced transmit control register 12 is electrically connected to the second data transmit / receive controller 11. The pull-up control circuit 3 is electrically connected to the first I / O port 8 and the second I / O port 13, respectively.

[0043] The first UART 1 and the second UART 2 are connected through the first IO port 8 and the second IO port 13.

[0044] Specifically, the data transmit / receive controller is responsible for controlling the enable control (TX_OE, RX_IE) of the UART device's TX and RX pins, as well as data processing during transmission and reception. The forced transmit control register stores the control register used to set whether to force transmit. If set to enable, the UART device can force transmit; if set to disable, forced transmission is not possible. Pull-up control circuit 3 is responsible for maintaining a high potential at the I / O port. Its impedance is generally greater than the output impedance when the TX pin is enabled, ensuring that the I / O port is at a high potential when the TX pin is disabled, and not affecting the potential output from the TX pin to the I / O port when the TX pin is disabled.

[0045] Relevant signals include:

[0046] TX: Output signal of UART device;

[0047] RX: Input signal of UART device;

[0048] TX_OE: Output enable signal for TX. If enabled, the value of the TX pin is sent to the I / O port; if disabled, the output of the TX pin to the I / O port is turned off.

[0049] RX_IE: Input enable signal for RX. If enabled, the value of the IO port is sent to the RX pin of the UART device. If disabled, the input from the IO port to the RX pin is turned off.

[0050] Furthermore, the first data transmission and reception controller 6 is responsible for controlling the enable control of the first TX pin 4 and the first RX pin 5, as well as processing the data during transmission and reception; the second data transmission and reception controller 11 is responsible for controlling the enable control of the second TX pin 9 and the second RX pin 10, as well as processing the data during transmission and reception.

[0051] Furthermore, the first forced transmission control register 7 is used to set whether the first UART 1 performs forced transmission; the second forced transmission control register 12 is used to set whether the second UART 2 performs forced transmission. If the first forced transmission control register 7 is enabled, the first UART 1 can perform forced transmission; if the second forced transmission control register 12 is enabled, the second UART 2 can perform forced transmission; if the first forced transmission control register 7 is disabled, the first UART 1 cannot perform forced transmission; if the second forced transmission control register 12 is disabled, the second UART 2 cannot perform forced transmission.

[0052] Furthermore, if the first forced transmit control register 7 is enabled and the second forced transmit control register 12 is disabled, the first UART 1 can terminate the transmission process of the second UART 2, but the second UART 2 cannot terminate the transmission process of the first UART 1.

[0053] Furthermore, if the first forced transmission control register 7 is set to disabled and the second forced transmission control register 12 is set to enabled, the first UART 1 cannot terminate the transmission process of the second UART 2, and the second UART 2 can terminate the transmission process of the first UART 1.

[0054] Furthermore, if the first forced transmit control register 7 is enabled and the second forced transmit control register 12 is enabled, the first UART 1 can terminate the transmission process of the second UART 2, and the second UART 2 can terminate the transmission process of the first UART 1.

[0055] Furthermore, if the first forced transmit control register is disabled and the second forced transmit control register is disabled, the first UART cannot terminate the transmission process of the second UART, and the second UART cannot terminate the transmission process of the first UART.

[0056] Furthermore, the pull-up control circuit 3 is used to maintain the high potential of the first IO port 8 and the second IO port 13. The impedance of the pull-up control circuit 3 is greater than the output impedance when the first TX pin 4 and the second TX pin 5 are enabled.

[0057] The UART interaction method in half-duplex mode provided by this invention is based on the above-mentioned system, such as... Figure 5 As shown, it includes the following steps:

[0058] Step S1: Send the first UART data to the second UART 2 sequentially via the first UART 1, consisting of several data bits and one stop bit;

[0059] Step S2: Sequentially collect several data bits and one stop bit through the second UART 2 until the stop bit is collected, then determine whether the second UART 2 has any second UART data to be transmitted;

[0060] Step S3: If so, the second UART data is sent directly through the second UART 2, and the level of the second IO port 13 is lowered;

[0061] Step S4: If the level of the second IO port 13 is detected to have dropped by the first UART 1, it is considered that the second UART 2 has data to be sent, and it is determined whether the first UART 1 has a next frame of first UART data to be sent;

[0062] Step S5: If so, the first UART 1 stops sending the next frame of first UART data and receives the second UART data through the first UART 1;

[0063] The first UART data includes several data bits and a stop bit. The first forced transmit control register 7 in the first UART 1 is set to disabled, and the second forced transmit control register 12 in the second UART 2 is set to enabled.

[0064] In step S1 above, when a stop bit is sent to the second UART 2 via the first UART 1, the following is included:

[0065] When the stop bit is started, the output enable signal of the first UART 1 is kept high until a few clock cycles before the center of the stop bit is reached. Then the output enable signal of the first UART 1 is lowered to low, and the first TX pin 4 stops outputting to the first IO port 8.

[0066] Specifically, Figure 3 This is a schematic diagram of the data transmission waveform of the interactive method provided by the present invention. Figure 3 Taking the transmission from UART 1 to UART 2 as an example, after UART 2 completes the acquisition of the stop bit (usually at the center of the stop bit), if data transmission is needed, it can directly send the data. At this time, the I / O port level drops (from the stop bit to the start bit), which is detected by UART 1. UART 1 then determines that UART 2 has data to send, stops sending the next frame of data (if any), and begins receiving data. It is important to note that the forced transmit register configurations of UART 1 and UART 2 in this example can be independent, meaning there are four possible scenarios:

[0067] (1) The forced transmit control register of the first UART 1 is enabled and the forced transmit control register of the second UART 2 is disabled. The first UART 1 can terminate the transmission process of the second UART 2, but the second UART 2 cannot terminate the transmission process of the first UART 1.

[0068] (2) The forced transmit control register of the first UART 1 is disabled, and the forced transmit control register of the second UART 2 is enabled. The first UART 1 cannot terminate the transmission process of the second UART 2, while the second UART 2 can terminate the transmission process of the first UART 1.

[0069] (3) When the forced transmit control register of the first UART 1 is enabled and the forced transmit control register of the second UART 2 is enabled, the first UART 1 can terminate the transmission process of the second UART 2, and the second UART 2 can also terminate the transmission process of the first UART 1.

[0070] (4) The forced transmit control register of the first UART 1 is disabled, and the forced transmit control register of the second UART 2 is disabled. Neither the first UART 1 nor the second UART 2 can terminate the transmission process of the other.

[0071] The above functions require the combination of pull-up control circuit 3 and the TX_OE signal. When the transmitter sends a stop bit, if the transmitter's TX_OE is enabled, then if the receiver forces transmission at this time, its TX_OE will also be enabled. At this time, the potential of the IO terminal will inevitably conflict (the original transmitter outputs 1, while the original receiver forces transmission of 0). Therefore, the transmitter needs to control its TX_OE signal during the transmission of the stop bit.

[0072] UART devices typically use an 8x or 16x oversampling clock for data transmission. Figure 4 This is a schematic diagram of the 16x oversampled UART clock in the interaction method provided by this invention. Figure 4 This section uses a 16x oversampling clock as an example to illustrate the actions of the TX_OE signal when the UART device outputs a stop bit. For example... Figure 4 As shown, when the TX_OE of the transmitting end transmits the stop bit, it can do so within the first few clock cycles of this phase (the specific number can be adjusted, but it must be before the center of the stop bit). Figure 4 For the first three clock cycles, TX_OE remains high, ensuring a rapid transition from data to stop bits in the UART output. During the clock cycle before the stop bit center, TX_OE is lowered to low, stopping the TX pin output from being sent to the I / O port. At this time, the I / O port's potential is maintained high by pull-up control circuit 3. If the receiver needs to force transmission, it can directly pull TX_OE high, sending the low potential of the start bit to the I / O port. Since the impedance of pull-up control circuit 3 is much greater than the output impedance of the TX pin, it will not affect the receiver's forced transmission level.

[0073] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0074] (1) The present invention does not require additional signal control and can be effectively compatible with existing software control schemes;

[0075] (2) The present invention can switch the data transmission direction in a timely and accurate manner, and its functions are configurable and have strong flexibility.

[0076] (3) Compared with existing software control schemes, the present invention can effectively avoid bandwidth waste.

[0077] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A system for UART interaction in half-duplex mode, characterized in that, include: The first UART includes a first TX pin, a first RX pin, a first data transmit / receive controller, a first forced transmit control register, and a first I / O port. The first data transmit / receive controller is electrically connected to the first TX pin and the first RX pin, respectively. The first I / O port is electrically connected to the first TX pin and the first RX pin, respectively. The first forced transmit control register is electrically connected to the first data transmit / receive controller. The second UART includes a second TX pin, a second RX pin, a second data transmit / receive controller, a second forced transmit control register, and a second I / O port. The second data transmit / receive controller is electrically connected to the second TX pin and the second RX pin, respectively. The second I / O port is electrically connected to the second TX pin and the second RX pin, respectively. The second forced transmit control register is electrically connected to the second data transmit / receive controller. The pull-up control circuit is electrically connected to the first I / O port and the second I / O port respectively; The first UART and the second UART are connected through the first I / O port and the second I / O port; The first forced transmission control register is used to set whether the first UART performs forced transmission; the second forced transmission control register is used to set whether the second UART performs forced transmission.

2. The half-duplex mode UART interaction system of claim 1, wherein, The first data transmission and reception controller is responsible for controlling the enable control of the first TX pin and the first RX pin, as well as processing the data during transmission and reception; the second data transmission and reception controller is responsible for controlling the enable control of the second TX pin and the second RX pin, as well as processing the data during transmission and reception.

3. The UART interaction system in half-duplex mode according to claim 1, characterized in that, If the first forced transmit control register is enabled, the first UART can perform forced transmission. If the second forced transmit control register is enabled, the second UART can perform forced transmission. If the first forced transmit control register is disabled, the first UART cannot perform forced transmission. If the second forced transmit control register is disabled, the second UART cannot perform forced transmission.

4. The UART interaction system in half-duplex mode according to claim 3, characterized in that, If the first forced transmit control register is enabled and the second forced transmit control register is disabled, the first UART can terminate the transmission process of the second UART, but the second UART cannot terminate the transmission process of the first UART.

5. The half-duplex mode UART interaction system of claim 3, wherein, If the first forced transmit control register is disabled and the second forced transmit control register is enabled, the first UART cannot terminate the transmission process of the second UART, and the second UART can terminate the transmission process of the first UART.

6. The half-duplex mode UART interaction system of claim 3, wherein, If the first forced transmit control register is enabled and the second forced transmit control register is enabled, the first UART can terminate the transmission process of the second UART, and the second UART can terminate the transmission process of the first UART.

7. The half-duplex mode UART interaction system of claim 3, wherein, If the first forced transmit control register is disabled and the second forced transmit control register is disabled, the first UART cannot terminate the transmission process of the second UART, and the second UART cannot terminate the transmission process of the first UART.

8. The half-duplex mode UART interaction system of claim 1, wherein, The pull-up control circuit is used to maintain the high potential of the first IO port and the second IO port. The impedance of the pull-up control circuit is greater than the output impedance when the first TX pin and the second TX pin are enabled.

9. A UART interaction method in half-duplex mode, based on the system according to any one of claims 1-8, characterized in that, Includes the following steps: The first UART data is sequentially transmitted to the second UART in several data bits and one stop bit through the first UART; The second UART sequentially collects the data bits and the stop bit until the stop bit is collected, and then determines whether the second UART has any data to send. If so, the second UART data is sent directly through the second UART, and the level of the second IO port is reduced; If the first UART detects a drop in the level of the second IO port, it is considered that the second UART has data to send, and it is determined whether the first UART has a next frame of first UART data to send; If so, the first UART stops sending the next frame of first UART data and receives the second UART data through the first UART; The first UART data includes the plurality of data bits and the stop bit, the first forced transmit control register in the first UART is set to disabled, and the second forced transmit control register in the second UART is set to enabled.

10. The half-duplex mode UART interaction method of claim 9, wherein, When sending a stop bit to the second UART via the first UART, the following is included: When the stop bit is started to be sent, the output enable signal of the first UART is kept at a high level until a few clock cycles before the center of the stop bit is reached, the output enable signal of the first UART is lowered to a low level, and the first TX pin stops outputting to the first IO port.

Images