Integrated circuit with vertical structure capacitive element and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to integrated circuits having vertical structure capacitive elements and methods of manufacturing the same. The capacitive element includes a trench extending vertically from a first side into a well. The trench is filled with a conductive center portion that is coated with an insulating cladding. The capacitive element further includes a first conductive layer overlying a first insulating layer on the first side and a second conductive layer overlying a second insulating layer on the first conductive layer. The conductive center portion and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer, and the second insulating layer form a dielectric region of the capacitive element.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese invention patent application No. 201810981962.8, filed on August 27, 2018, entitled "Integrated Circuit with Vertical Capacitor Element and Manufacturing Method Thereof".

[0003] Priority Statement

[0004] This application claims priority to French patent application No. 1757907, filed on August 28, 2017, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0005] Embodiments and implementations of the present invention relate to integrated circuits, and more particularly to capacitive elements operating in accumulation mode or inversion mode. Background Technology

[0006] Capacitive elements, such as charge storage capacitors, are typically large components in integrated circuit architectures.

[0007] Furthermore, the process steps for manufacturing integrated circuit components are typically numerous and expensive, and limit the implementation of steps dedicated to manufacturing a single component or a single type of component.

[0008] Therefore, it is desirable to increase the capacitance per unit area of ​​the integrated circuit capacitor element architecture, and it is desirable to implement its manufacturing steps together with the production of other components of the integrated circuit. Summary of the Invention

[0009] In this document, according to one aspect, an integrated circuit is provided, comprising: a semiconductor substrate including at least one semiconductor well doped with a first conductivity type; a capacitor element including at least one trench including a conductive central portion covered by an insulating cladding and extending perpendicularly from a first side into the well, a first conductive layer covering a first insulating layer located on the first side, a second conductive layer covering a second insulating layer located on the first conductive layer, the conductive central portion being electrically coupled or connected to the first conductive layer to form a first electrode of the capacitor element, the second conductive layer and the well being electrically coupled or connected to form a second electrode of the capacitor element, and the insulating cladding, the first insulating layer and the second insulating layer forming a dielectric region of the capacitor element.

[0010] Therefore, the at least one trench allows the area of ​​the first electrode to be maximized within the depth of the trap, thus increasing the capacitance per unit area of ​​the capacitor element.

[0011] According to one embodiment, the auxiliary semiconductor layer is configured to form a minority carrier source in the well.

[0012] The auxiliary semiconductor layer is advantageously doped with a second conductivity type opposite to the first conductivity type and is designed to receive a bias voltage.

[0013] Because the auxiliary layer is doped with a conductivity type opposite to that of the well, the auxiliary layer forms a minority carrier source, which allows the capacitor element to be used in both accumulation and inversion modes (i.e., both have positive and negative voltages between their electrodes).

[0014] For example, the auxiliary semiconductor layer includes a buried layer located below the well and below the at least one trench, and a contact segment extending from the first side to the buried layer.

[0015] The auxiliary semiconductor layer may include an auxiliary contact region that is flush with the first side and electrically coupled to or connected to the second electrode.

[0016] The at least one trench may also include an injection region of a second conductive type, located between the bottom of the central portion covered by the cladding and the burial layer.

[0017] For example, the auxiliary semiconductor layer is flush with the first side of the well.

[0018] The auxiliary semiconductor layer may include an auxiliary contact region extending from the first side and electrically coupled or connected to the second electrode.

[0019] According to one embodiment, the integrated circuit includes a memory device comprising a memory plane having non-volatile memory cells equipped with access transistors and floating gate transistors, each access transistor having a vertical gate, and the depth of the at least one trench being substantially equal to the depth of the vertical gate.

[0020] According to one embodiment, each vertical gate includes a gate material coated with a gate oxide, the material of the conductive central portion having the same properties as the gate material, and the material of the insulating cladding having the same properties as the gate oxide.

[0021] According to one embodiment, the floating gate transistor includes a dual-gate structure comprising a tunnel oxide, a conductive floating gate, a control gate dielectric, and a conductive control gate. A first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer form a structure having the same material and arrangement as the dual-gate structure.

[0022] According to another aspect, a method for manufacturing a capacitor element is provided, the method comprising: forming at least one trench extending vertically from a first side of the trench into a well doped with a first conductivity type, pre-formed in a semiconductor substrate; forming an insulating cladding layer on the sides and bottom of the at least one trench; forming a conductive material in a central portion covered by the insulating cladding layer; forming a first insulating layer on the first side and covering the first insulating layer to form a first conductive layer; forming a second insulating layer on the first conductive layer and covering the second insulating layer to form a second conductive layer; creating a first electrical connection or a first electrical coupling between the conductive central portion and the first conductive layer to form a first electrode of the capacitor element; and creating a second electrical connection or a second electrical coupling between the second conductive layer and the trench to form a second electrode of the capacitor element.

[0023] According to one embodiment, the method includes fabricating a non-volatile memory cell belonging to a memory plane and equipped with an access transistor having a vertical gate and a floating gate transistor in and on a semiconductor substrate, and: wherein forming at least one trench, forming an insulating cladding layer, and forming a conductive material are performed together with the step of forming the access transistor; forming a first insulating layer on a first side and a first conductive layer covering the first insulating layer, and forming a second insulating layer on the first conductive layer and a second conductive layer covering the second insulating layer are performed together with the step of fabricating the floating gate transistor.

[0024] For example, manufacturing a capacitor element includes forming an auxiliary semiconductor layer doped with a second conductivity type opposite to the first conductivity type, which is performed together with the steps of manufacturing a buried source region layer of an access transistor and electrically coupling or connecting the auxiliary layer to the second electrode.

[0025] For example, manufacturing a capacitor element includes forming an auxiliary semiconductor layer doped with a second conductivity type opposite to the first conductivity type, which is performed together with the steps of forming a directional injection region of a floating gate transistor and electrically coupling or connecting the auxiliary layer to the second electrode. Attached Figure Description

[0026] Other advantages and features of the invention will become apparent from a study of the detailed description of the completely non-limiting embodiments and implementations, as well as the accompanying drawings, wherein:

[0027] Figure 1 An embodiment of a capacitor element is schematically illustrated;

[0028] Figure 2 A top view of the capacitor element is shown;

[0029] Figure 3 It is an equivalent circuit diagram;

[0030] Figures 4 to 7An example of an embodiment of a capacitor element is shown;

[0031] Figure 8 A non-volatile memory device is shown; and

[0032] Figure 9 A method for co-fabricating capacitor elements and non-volatile memory cells on the same semiconductor substrate is shown. Detailed Implementation

[0033] Figure 1 An example embodiment of capacitor element C is shown.

[0034] The capacitor element C is formed in and on a semiconductor substrate 1 doped with a first conductivity type.

[0035] Substrate 1 includes a single well 3 (as opposed to, for example, a “triple well”), in which a trench TR is formed. As is conventional, well 3 is laterally confined by trench isolation STI, here being shallow trench isolation.

[0036] The trench TR extends from the first side 10 of the substrate 1 into the well 3, which is usually referred to as the "front side".

[0037] See below for reference. Figure 4 and Figure 8 As shown, for manufacturing process optimization, each trench TR may include an injection region 205 located in the well 3 below the corresponding bottom of each trench TR, the injection region 205 being doped with a second conductivity type opposite to the first conductivity type.

[0038] The trench includes a central portion 5 filled with conductive material and covered with an insulating cladding 7 that separates the central portion 5 from the well 3.

[0039] For example, the central portion 5 is made of doped polycrystalline silicon (also known as polycrystalline silicon), and the insulating cladding 7 is made of silicon dioxide or other dielectric materials.

[0040] On the first side 10 and above the well 3, a stack of a first insulating layer 17, a first conductive layer 15, a second insulating layer 27, and a second conductive layer 25 is formed.

[0041] The first conductive layer 15 and the second conductive layer 25 are formed, for example, by doped polycrystalline silicon, the first insulating layer 17 is formed by a dielectric material such as silicon dioxide, and the second insulating layer is formed by a silicon oxide-nitride-oxide (ONO) dielectric material structure.

[0042] As explained below, especially in reference Figure 5This structure is advantageously similar to the structure of a non-volatile memory cell. Specifically, the memory cell may include an access transistor with a vertical gate and a floating gate transistor, the access transistor having a structure similar to that of a trench TR, and the floating gate transistor having a structure similar to that of a stack of a first insulating layer 17 and a second insulating layer 27, and a first conductive layer 15 and a second conductive layer 25.

[0043] The first electrode E1 of the capacitor element C is formed by electrically coupling or connecting the conductive material of the central portion 5 of each trench TR to the first conductive layer 15.

[0044] Through-holes and metal connection tracks allow the conductive material in the central portion 5 of the trench TR to be connected to the first conductive layer 15.

[0045] The second electrode E2 of the capacitor element C is formed by electrically coupling or connecting the second conductive layer 25 to the doped semiconductor well 3.

[0046] The highly doped contact redistribution region 13 of the first conductivity type allows for the formation of a contact with an acceptable resistivity between the well 3 and, for example, a metal connection track connected to the second conductive layer 25.

[0047] In this example, the contact redistribution region 13 is laterally located on either side of the trench TR.

[0048] Figure 2 References are shown Figure 1 The example described is a top view; common elements are already referenced by the same reference numerals and will not be described in detail below.

[0049] The trench TR extends further longitudinally than the first insulating layer (17) covered by the first conductive layer 15 (i.e., in the direction perpendicular to the first insulating layer 15). Figure 1 (in the direction of the cross-section shown), thus allowing electrical contacts E1-5 to be formed together with the central portion (5) of each trench TR. Similarly, in this example, the first conductive layer 15 extends further in the longitudinal direction than the stack of the second insulating layer (27) and the second conductive layer 25, thereby allowing contacts E1-15 to be formed together with the first conductive layer.

[0050] The contacts E1-5 of the central portion 5 and the contacts E1-15 of the first conductive layer 15 are electrically coupled or connected, for example, through a metal track (not shown in the figure), thereby forming the first electrode (E1) of the capacitor element C.

[0051] In addition, electrical contacts E2-13 are generated on the contact-redistribution region 13 formed in the trap 3, and electrical contacts E2-25 are generated on the second conductive layer 25.

[0052] The contacts E2-13 of the substrate 1 and the contacts E2-25 of the second conductive layer 25 are electrically coupled or connected, for example, through a metal track (not shown in the figure), thereby forming the second electrode (E2) of the capacitor element C.

[0053] Figure 3 An equivalent circuit diagram of the above example is shown, and examples of other embodiments described below are also applicable.

[0054] Capacitor element C can be decomposed into three capacitor elements C in parallel. ONO C TUN and C TR One of the components.

[0055] First capacitor element C ONO It is formed by a first conductive layer 15 and a second conductive layer 25 that are separated from each other by a second insulating layer 27.

[0056] Second capacitor element C TUN It is formed by a first conductive layer 15 and a well 3 that are separated from each other by a first insulating layer 17.

[0057] Third capacitor element C TR It is formed by the central portion 5 of the trench TR and the well 3, which are separated from each other by the corresponding insulating cladding 7 of the trench TR.

[0058] In the example where the first conductivity type is p-type and the second conductivity type is n-type, the capacitor element C operates in accumulation mode, that is, when the voltage V between the first electrode E1 and the second electrode E2... C For V C =V E2 -V E1 When positive, due to the p-type conductivity of the charge carriers in well 3.

[0059] Although capacitors in integrated circuits are typically designed to operate specifically in accumulation mode, it may be advantageous for capacitors to also operate in inversion mode.

[0060] Figures 4 to 7 An example embodiment of the capacitor element C is shown, which is advantageously capable of operating in both accumulation mode and inversion mode.

[0061] In these embodiments, the auxiliary semiconductor layer is configured to form a minority carrier source in the well.

[0062] In short, minority carrier sources allow the use of capacitive elements in inverted mode.

[0063] Figure 4 An example embodiment of the capacitor element C capable of operating in inverted mode is shown, wherein, as referenced above... Figures 1 to 3The common graphical structural elements described in the examples have been given the same reference numerals and will not be described in detail below.

[0064] In this example, well 3 forms part of a triple-well structure and is electrically isolated from substrate 1 by an isolation layer doped with a second conductivity type opposite to the first conductivity type of well 3 and substrate.

[0065] The isolation layer includes a buried layer 200 doped with a second conductivity type below the well 3 and a contact segment 210 doped with a second conductivity type extending from the front side 10 to the buried layer 200.

[0066] The auxiliary contact region 213, which is highly doped with the second conductivity type, is formed flush with the front side 10 in the contact segment 210.

[0067] The auxiliary contact area 213 allows for contact with an acceptable resistivity between the terminal used to receive bias voltage (e.g., ground terminal GND) and the contact segment 210 and the buried layer 200.

[0068] The contact section 210 and the auxiliary contact area 213 form a ring and surround the trap 3 laterally and longitudinally.

[0069] The isolation layers 200, 210, and 213 thus form auxiliary semiconductor layers configured to form minority carrier sources in the well 3, allowing the capacitor element C to operate in inversion mode.

[0070] Both the contact redistribution region 13 and the auxiliary contact redistribution region 213 are electrically connected to the second electrode E2.

[0071] In addition, the trench TR may include an implantation region 205 doped with a second conductivity type, which is located between the corresponding bottom of the trench TR and the buried layer 200, allowing electrical continuity to be ensured between the edge of the trench TR and the buried semiconductor layer 200.

[0072] The contact redistribution region 13, which is highly doped with the first conductivity type and is injected into the well 3 and is flush with the first side 10, also forms a ring on the surface of the well 3, inside the ring formed by the contact segment 210 and the segment contact region 213.

[0073] Therefore, this example of capacitor element C is consistent with the reference. Figure 1 The described example operates similarly in accumulation mode and in inversion mode by forming a minority carrier region in the well 3, near the edge of the trench TR and near the first side below the insulating layer 17.

[0074] Figure 5 References are shown Figure 4 The example is a top view; the same reference numerals are given for common elements, and they will not be described in detail below.

[0075] The contacts E1-5 of the central portion 5 and the contacts E1-15 of the first conductive layer 15 are electrically coupled or connected, for example, through a metal track (not shown in the figure), thereby forming the first electrode (E1) of the capacitor element C.

[0076] In this example, the electrical contact E2-213 also forms an auxiliary contact area 213.

[0077] For example, an electrical coupling or connection is formed between the contact E2-13 of the well 3, the contact E2-213 of the auxiliary contact region 213, and the contact E2-25 of the second conductive layer 25 via a metal track (not shown in the figure), thus forming the second electrode (E2) of the capacitor element C.

[0078] Figure 6 An example of another embodiment of the capacitor element C capable of operating in inverted mode is shown, wherein, as referenced above... Figures 1 to 5 The common structural elements described in the examples have been given the same reference numerals and will not be described in detail below.

[0079] In this example, an auxiliary semiconductor layer serving as a minority carrier source is obtained by forming a so-called reverse injection layer 300, which is located on the surface of the well flush with the front side 10 and is doped with a second type of conductivity.

[0080] Similarly, the highly doped auxiliary contact region 313 of the second conductivity type allows contact with the auxiliary semiconductor layer 300 with an acceptable resistivity, allowing a bias voltage to be applied thereto.

[0081] The same auxiliary contact redistribution layer 313 is also connected to the second electrode E2 and allows the capacitor element C to operate in reverse mode, similar to the reference above. Figure 4 and 5 The example described is a reversal of the pattern operation.

[0082] Figure 7 References are shown Figure 6 The example is a top view; the same reference numerals are given for common elements, and they will not be described in detail below.

[0083] The contacts E1-5 of the central portion 5 and the contacts E1-15 of the first conductive layer 15 are electrically coupled or connected, for example, through a metal track (not shown in the figure), thereby forming the first electrode (E1) of the capacitor element C.

[0084] The contacts E2-13 of the well 3, the contacts E2-213 of the auxiliary contact redistribution layer 313, and the contacts E2-25 of the second conductive layer 25 are electrically coupled or connected, for example, through metal rails (not shown in the figure), thereby forming the second electrode (E2) of the capacitor element C.

[0085] Figure 6 and Figure 7 The example has the advantage of not being formed in a triple well, requiring an isolation "ring" to surround the well 3 containing the capacitor element C laterally and longitudinally, thus having a correspondingly smaller area.

[0086] Various examples of these embodiments are particularly compatible with processes used to produce non-volatile memory devices EE, whose memory plane PM has non-volatile memory cells CEL and vertical gate selection transistors TA, such as Figure 8 As shown schematically in the diagram.

[0087] More precisely, each memory cell CEL includes a floating gate transistor TFG generated in and on a semiconductor well PW of the first conductivity type in a triple-well architecture, i.e., the well is separated from the lower substrate PSUB of the first conductivity type by a buried semiconductor layer NISO and a semiconductor segment NW of the second conductivity type.

[0088] Conventionally, each floating-gate transistor (TFG) includes a source region S and a drain region D doped with a second conductivity type, as well as a floating gate (FG) and a control gate (CG), which are made of, for example, polysilicon and separated from each other by a control gate dielectric (ONO). The floating gate is located on a tunnel oxide layer (OXT) formed on the surface of the well (PW).

[0089] Each access transistor (TA) allows selection of a row of cells and is a MOS transistor. Its gate (GTA) is a gate buried in a p-type well and electrically insulated from the well by a gate dielectric (OXTA, typically silicon dioxide). The gate material (mGTA) of the vertical gate (GTA) is, for example, polysilicon.

[0090] The injection region RI of the second conductivity type, located between the bottom of the trench accommodating the vertical gate GTA and the buried layer NISO, allows the source region of the access transistor TA to be formed together with the buried layer NISO.

[0091] Figure 9 It is shown that the semiconductor substrate 1 is co-manufactured according to the above reference. Figures 1 to 7 The example capacitor element C and the reference Figure 8 Examples of implementations of the processes for those non-volatile memory cells (CELs) of the same type described.

[0092] Based on the above reference Figure 4 and Figure 5The steps 912 of forming the auxiliary layers 200-210-230 and 914 of forming the triple-well PW of the memory EE are implemented in a common step 910.

[0093] Specifically, the formation of a triple-well PW includes forming a buried semiconductor layer NISO and a second conductivity type semiconductor well NW, and typically forming a highly doped contact redistribution layer on the surface of the well NW, which has the same properties as the element in the auxiliary semiconductor layers 200-210-213.

[0094] Similarly, the trench TR and the vertical gate access transistor TA are formed in a common step 920.

[0095] Specifically, the formation 928 of the vertical gate GTA of the access transistor TA includes etching 922 of the trench, which is of the same nature as the etching of the trench belonging to the capacitor element C, forming a gate dielectric OXTA of the same nature as step 924 of forming the insulating cladding 7, and filling the gate material mGTA, which is of the same nature as step 926 of forming a conductive material in the central portion 5 of the trench TR.

[0096] Based on the above reference Figure 6 and Figure 7 The steps 932 of forming the auxiliary layer 300 and 934 of forming the reverse injection layer in the well of the floating gate transistor, as described in the embodiment, are implemented in a common step 930.

[0097] The step of forming a structure consisting of a first insulating layer 17, a first conductive layer 15, a second insulating layer 27, and a second conductive layer 25 is performed in step 940, which is the same as the formation of the floating gate transistor TFG of the memory EE.

[0098] Specifically, step 941 of forming the first insulating layer 17 has the same nature as step 942 of forming the tunnel oxide (OXT); step 943 of forming the first conductive layer 15 has the same nature as step 944 of forming the polysilicon floating gate layer (FG); step 945 of forming the second insulating layer 27 is the same as step 945 of forming the silicon oxide-nitride-oxide layer (ONO) of the gate of the discrete floating gate transistor (TFG); and step 947 of forming the second conductive layer 25 has the same nature as step 948 of forming the polysilicon control gate layer (CG).

[0099] Therefore, for conventional manufacturing steps, such as those required to manufacture the memory cell CL of the memory device EE, a capacitor element C has been produced that utilizes an interface of three types of conductive materials separated by an insulator and utilizes a substrate (or well) in depth to maximize the area of ​​the interface without occupying space on the front surface.

[0100] In other words, this example of a capacitor element structure allows for the maximization of capacitance per unit area (i.e., per unit area occupied on the front side of the trap).

[0101] For example, the capacitance per unit area in this embodiment can be 15 to 20 fF / μm. 2 Traditional capacitors have a capacitance of approximately 6 fF / μm² per unit area.

[0102] Furthermore, the present invention is not limited to these embodiments and implementations, but includes any variations thereof; for example, the step of manufacturing the capacitor element C can be performed separately from the conventional steps of manufacturing the memory cell, i.e., in a manner dedicated to manufacturing the capacitor element C; similarly, as shown in the figure, the first and second conductivity types can be p-type and n-type, respectively, or conversely, n-type and p-type, respectively.

Claims

1. A method comprising: Fabricating a capacitive element on and within a well located within a semiconductor substrate, wherein the well is doped with a first conductivity type, wherein fabricating the capacitive element comprises: A trench is formed that extends vertically from the first side of the trap into the trap; An insulating cladding is formed on the sidewalls and bottom of the trench; A conductive material is formed in the central portion of the trench covered by the insulating layer; A first insulating layer is formed on the first side and a first conductive layer is formed covering the first insulating layer; The conductive central portion is electrically connected to the first conductive layer to form the first electrode of the capacitive element; A second insulating layer is formed on the first conductive layer, and a second conductive layer covering the second insulating layer is formed; and The second conductive layer is electrically connected to the trap to form the second electrode of the capacitive element.

2. The method according to claim 1, further comprising: An auxiliary semiconductor layer is formed beneath the well, and the auxiliary semiconductor layer is doped with a second conductivity type opposite to the first conductivity type.

3. The method according to claim 2, further comprising: The auxiliary semiconductor layer is electrically connected to the second electrode.

4. The method according to claim 2, further comprising: An implantation region, doped with the second conductivity type and in contact with the auxiliary semiconductor layer, is formed below the trench.

5. The method according to claim 1, further comprising: An auxiliary semiconductor layer is formed on the first side of the well, the auxiliary semiconductor layer being doped with a second conductivity type opposite to the first conductivity type.

6. The method according to claim 5, further comprising: The auxiliary semiconductor layer is electrically connected to the second electrode.

7. The method according to claim 1, further comprising: An implantation region with a second conductivity type opposite to the first conductivity type is formed in the well below the trench.

8. The method of claim 1, further comprising forming a vertical gate transistor in the semiconductor substrate, wherein fabricating the vertical gate transistor comprises: Forming another trench that extends vertically into the semiconductor substrate; Another insulating cladding is formed on the sidewalls and bottom of the other trench; Another conductive material is formed in the central portion of the other trench that is covered by the other insulating layer; The steps of forming the trench and forming the other trench are performed together; The steps of forming the insulating cladding layer and forming the other insulating cladding layer are performed together; and The steps of forming the conductive material and forming the other conductive material are performed together.

9. The method of claim 8, further comprising: An auxiliary semiconductor layer is formed beneath the well, and the auxiliary semiconductor layer is doped with a second conductivity type opposite to the first conductivity type. as well as A buried source region is formed in the semiconductor substrate; The steps of forming the auxiliary semiconductor layer and forming the buried source region are performed together.

10. The method of claim 1, further comprising manufacturing a floating gate transistor supported by the semiconductor substrate, wherein manufacturing the floating gate transistor comprises: A first gate insulating layer is formed on the semiconductor substrate, and a floating gate conductive layer covering the first gate insulating layer is formed. as well as A second gate insulating layer is formed on the floating gate conductive layer, and a control gate conductive layer covering the second gate insulating layer is formed. The steps of forming the first insulating layer and forming the first gate insulating layer are performed together; The steps of forming the first conductive layer and forming the floating gate conductive layer are performed together; The steps of forming the second insulating layer and forming the second gate insulating layer are performed together; and The steps of forming the second conductive layer and forming the control gate conductive layer are performed together.

11. The method of claim 10, further comprising: An auxiliary semiconductor layer is formed on the first side of the well, and the auxiliary semiconductor layer is doped with a second conductivity type opposite to the first conductivity type; as well as Forming the reverse injection region of the floating gate transistor; The steps of forming the auxiliary semiconductor layer and forming the reverse implantation region are performed together.

12. A method comprising: Fabricating a capacitive element on and within a well located within a semiconductor substrate, wherein the well is doped with a first conductivity type, wherein fabricating the capacitive element comprises: A trench is formed that extends vertically from the first side of the trap into the trap; An insulating cladding is formed on the sidewalls and bottom of the trench; A conductive material is formed in the central portion of the trench covered by the insulating layer; An insulating layer is formed on the first side, and a conductive layer is formed covering the insulating layer; The conductive central portion is electrically connected to the conductive layer to form the first electrode of the capacitive element; The trap forms the second electrode of the capacitive element. The method further includes: forming an auxiliary semiconductor layer located on a surface flush with the first side of the well and doped with a second conductivity type opposite to the first conductivity type; and electrically connecting the auxiliary semiconductor layer to the second electrode.

13. The method of claim 12, further comprising: An implantation region, doped with a second conductivity type and in contact with the auxiliary semiconductor layer, is formed beneath the auxiliary semiconductor layer.

14. The method of claim 12, further comprising: An implantation region with a second conductivity type opposite to the first conductivity type is formed in the well below the auxiliary semiconductor layer.

15. The method of claim 12, further comprising fabricating a vertical gate transistor in the semiconductor substrate, wherein fabricating the vertical gate transistor comprises: Forming another trench that extends vertically into the semiconductor substrate; Another insulating cladding is formed on both sides and at the bottom of the other trench; Another conductive material is formed in the central portion of the other trench that is covered by the other insulating layer; The steps of forming the trench and forming the other trench are performed together; The steps of forming the insulating cladding layer and forming the other insulating cladding layer are performed together; and The steps of forming the conductive material and forming the other conductive material are performed together.

16. The method of claim 15, further comprising: An auxiliary semiconductor layer is formed beneath the well, and the auxiliary semiconductor layer is doped with a second conductivity type opposite to the first conductivity type. as well as A buried source region is formed in the semiconductor substrate; The steps of forming the auxiliary semiconductor layer and forming the buried source region are performed together.

17. The method of claim 12, further comprising manufacturing a transistor supported by the semiconductor substrate, wherein manufacturing the transistor comprises: A gate insulating layer is formed on the semiconductor substrate, and a gate conductive layer is formed covering the gate insulating layer; The steps of forming the insulating layer and forming the gate insulating layer are performed together; and The steps of forming the conductive layer and forming the gate conductive layer are performed together.

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