Quantum mechanical circuits, superconducting quantum mechanical computers, and methods of fabricating quantum mechanical circuits

Abstract

A quantum mechanical circuit (100) includes first and second electrical conductors (104, 106) disposed on a substrate (102) and spaced apart to provide a gap (112) therebetween, and a third electrical conductor (108) electrically connecting the first and second electrical conductors. The third electrical conductor has a thermal conductivity substantially lower than the thermal conductivity of the first and second electrical conductors to provide thermal isolation. A qubit (206) of a superconducting quantum processor (204) is provided on the substrate and electrically connected to ground via at least one of the first or second electrical conductors.

Description

Background Technology

[0001] The currently claimed embodiments of the present invention relate to quantum mechanical circuits, and more specifically, to quantum mechanical circuits having an electrical conductor that is a poor thermal conductor.

[0002] In a typical printed circuit board (PCB), a relatively large, continuous ground plane is typically provided. Return current from signals traversing a typical PCB travels unimpeded. While this might be desirable in normal electrical applications, in electrical applications where thermal isolation is critical, a conductive, continuous ground plane will also thermally short-circuit all components connected to it. This will create problems in any application sensitive to thermal gradients.

[0003] In applications requiring a common electrical ground, separating the ground planes is generally avoided entirely when signals need to cross the boundary between two separate ground planes. A common method to mitigate heat transfer is to bridge the gap between two separate or split ground planes using capacitors. For applications sensitive to thermal gradients, PCBs are typically not used due to the aforementioned thermal short-circuit issues.

[0004] Therefore, a circuit is still needed that allows electrical conduction while reducing heat transfer. Thus, it is desirable to address this and other problems of the prior art by providing a novel circuit for use in quantum computers, such as superconducting quantum computers, where heat dissipation or heat transfer is generally undesirable. Summary of the Invention

[0005] One aspect of the present invention is to provide a quantum mechanical circuit. The quantum mechanical circuit includes: a substrate; a first electrical conductor and a second electrical conductor disposed on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor electrically connected to the first and second electrical conductors. The third electrical conductor is a poor thermal conductor.

[0006] In one embodiment, the third electrical conductor comprises at least one of copper-nickel (CuNi) or stainless steel. In one embodiment, CuNi has a strength of approximately 3.8 × 10⁻⁶ at ambient temperature. -8 The resistivity is Ωm and the thermal conductivity is between 25 W / m·K and 40 W / m·K. In one embodiment, the first and second electrical conductors comprise copper (Cu). In one embodiment, the first, second, and third electrical conductors are configured to transmit radio frequency current. In one embodiment, the third electrical conductor is coupled to the substrate using a fastener. In one embodiment, the fastener comprises brass. In one embodiment, the first and second electrical conductors are connected to electrical ground. In one embodiment, the first and second electrical conductors are electrically decoupled by providing a gap or channel within the substrate between the first and second electrical conductors. In one embodiment, the quantum mechanical circuit further includes an attenuator chip electrically coupled to the first and second electrical conductors.

[0007] Another aspect of the present invention is a superconducting quantum mechanical computer. This superconducting quantum mechanical computer includes: a cooling system comprising a temperature-controlled container; a quantum processor disposed within the temperature-controlled container, the quantum processor comprising a plurality of qubits; and a superconducting circuit disposed within the temperature-controlled container. The superconducting circuit includes: a substrate; a first electrical conductor and a second electrical conductor disposed on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor electrically connected to the first and second electrical conductors, the third electrical conductor being a poor thermal conductor. Each of the plurality of qubits is provided on the substrate and is electrically connected to ground via at least one of the first or second electrical conductors.

[0008] Another aspect of the present invention is to provide a method for manufacturing a quantum mechanical circuit. The method includes: providing a substrate having a top surface and a bottom surface; forming a conductive layer on at least one of the top surface and the bottom surface of the substrate; forming wires in a selected pattern on the substrate by removing a portion of the conductive layer, the wires including a first electrical conductor and a second electrical conductor on the substrate, the first and second electrical conductors being spaced apart and separated by a gap therebetween; and electrically connecting the first and second electrical conductors using a third electrical conductor, the third electrical conductor being a poor thermal conductor. Attached Figure Description

[0009] The functionality of the relevant elements of this disclosure, as well as the economy of combination and manufacture of the components, will become more apparent after considering the following description and appended claims with reference to the accompanying drawings, all of which form part of this specification, wherein the same reference numerals denote corresponding components in the various drawings. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to define limitations on the invention.

[0010] Figure 1 This is an electronic schematic diagram of a quantum mechanical circuit 100 according to an embodiment of the present invention; Figure 2 This is a three-dimensional perspective view of the electrical coupling between a first electrical conductor, a second electrical conductor, and a third electrical conductor according to an embodiment of the present invention; Figure 3 This is a three-dimensional perspective view of the configuration of the first and second electrical conductors according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating a superconducting quantum mechanical computer according to an embodiment of the present invention; and Figure 5 This is a flowchart of a method for manufacturing a quantum mechanical circuit according to an embodiment of the present invention. Detailed Implementation

[0011] Figure 1 This is an electronic schematic diagram of a quantum mechanical circuit 100 according to an embodiment of the present invention. The quantum mechanical circuit 100 includes a substrate 102. The quantum mechanical circuit 100 also includes a first electrical conductor 104 and a second electrical conductor 106 disposed on the substrate 102. The quantum mechanical circuit 100 further includes a third electrical conductor 108 electrically connecting the first electrical conductor 104 and the second electrical conductor 106. Figure 2 (As shown in the diagram). The third conductor 108 is a poor thermal conductor. The term "poor thermal conductor" is used extensively herein to mean that the third conductor 108 has a thermal conductivity substantially lower than that of the first conductor 104 and the second conductor 106. In one embodiment, the material of the third conductor 108 (poor thermal conductor) may be selected to have a sufficiently low thermal conductivity such that a cooling device (e.g., a cooling container) in which the circuit 100 is used can adequately cool the circuit 100 to a desired temperature (e.g., the operating temperature of the circuit). The selection of a material with a certain thermal conductivity depends on the system using the circuit 100. For example, if the cooling device (e.g., a cooling container) has sufficient cooling capacity, a material with a higher thermal conductivity is acceptable.

[0012] Figure 2 This is a three-dimensional perspective view of the electrical coupling between the first electrical conductor 104, the second electrical conductor 106, and the third electrical conductor 108 according to an embodiment of the present invention. Figure 2 As shown, the third conductor 108 is configured to electrically connect the first conductor 104 and the second conductor 106. In one embodiment, the third conductor 108 comprises at least one of copper-nickel (CuNi) or stainless steel. In one embodiment, CuNi has a strength of approximately 3.8 × 10⁻⁶ at ambient temperature. -8 The resistivity is Ωm and the thermal conductivity is between approximately 25 W / m·K and 40 W / m·K. However, it must be understood that other materials with poor thermal conductivity can also be used for the third electrical conductor 108.

[0013] In one embodiment, the first electrical conductor 104 and the second electrical conductor 106 comprise copper (Cu). The material of the third electrical conductor 108 differs from the materials of the first electrical conductor 104 and the second electrical conductor 106. In one embodiment, the materials of the first electrical conductor 104 and the second electrical conductor 106 can be substantially the same. For example, the materials of the first electrical conductor 104 and the second electrical conductor 106 can both be substantially copper (Cu), while the material of the third electrical conductor 108 is substantially CuNi and / or stainless steel. In one embodiment, the substrate 102 is a non-conductive (electrically insulating) material, such as silicon (Si), sapphire (Al2O3), printed circuit board material (e.g., FR-4 (braided glass and epoxy resin) or other laminates, glass fiber), or polymer (e.g., polyimide).

[0014] In one embodiment, the third electrical conductor 108 is coupled to the substrate 102 using a fastener 110. In one embodiment, the fastener 110 includes, for example, a brass fastener. However, other types of fasteners may also be used. Furthermore, in another embodiment, the third electrical conductor 108 may also be coupled to the substrate 102 using other means, such as by using an adhesive.

[0015] In one embodiment, the first conductor 104, the second conductor 106, and the third conductor 108 are configured to transmit radio frequency (RF) current. In another embodiment, the first conductor 104 and the second conductor 106 are connected to ground potential.

[0016] In one embodiment, the first electrical conductor 104 and the second electrical conductor 106 are electrically decoupled by providing an interruption, gap, or channel 112 between the first electrical conductor 104 and the second electrical conductor 106 within the substrate 102. The first electrical conductor 104 and the second electrical conductor 106 are spaced apart to provide a gap 112 therebetween.

[0017] Figure 3 This is a three-dimensional perspective view of the configuration of the first electrical conductor 104 and the second electrical conductor 106 according to an embodiment of the present invention. Figure 3 As shown, an interruption, gap, or channel 112 is provided between the first electrical conductor 104 and the second electrical conductor 106. In an embodiment, as... Figure 3 As shown, the two layers 116A and 116B can be used for signal transmission. For example, the interruptions, channels, or gaps 112 in layers 116A and 116B provide improved thermal isolation and help guide return current. This dual-sided structure provides increased density. Furthermore, in one embodiment, the top and bottom separation locations 112 are offset by removing the internal ground plane from the inner layer (not shown) of the substrate 102 and by providing blind vias (i.e., misaligned vias on layers 116A and 11B) to reduce electrical coupling.

[0018] In addition, such as Figure 3 As shown, attenuator chip 114 can be disposed on the top and bottom sides of layers 116A and 116B to increase electrical signal isolation. Attenuator chip 114 is electrically coupled (e.g., wire-bonded or soldered) to first conductor 104 and second conductor 106. In one embodiment, attenuator chip 114 can be wire-bonded or soldered (e.g., surface mount soldering or ball grid array soldering) across ground opening 112. Furthermore, in other embodiments, other types of components, such as filters, can be used in addition to or as a replacement for attenuator chip 114. In one embodiment, such as... Figure 3As shown, removing the ground plane (not shown) inside the substrate 102 by providing a break or gap 112 in both layers 116A and 116B allows for reduced coupling to increase thermal isolation. Furthermore, vias 118 can be arranged within the substrate 102 (not shown) to allow electrical signals to undergo appropriate electromagnetic mode conversion to reduce coupling. In this way, the electromagnetic (EM) field can more effectively utilize the ground potential to return the current path across the break 112 in the ground plane (i.e., the break or gap or channel 112 between the first and second conductors in layers 116A and 116B). Therefore, the ground potential is provided by the first conductor 104, the second conductor 106, and the third conductor 108, which are connected to each other and grounded.

[0019] Therefore, as can be understood from the foregoing paragraphs, in some embodiments of the invention, the problem of thermal isolation can be solved by separating the ground plane. The ground plane corresponds to a first conductor 104 and a second conductor 106 both connected to ground potential. Thus, the separation in the ground plane corresponds to a gap, interruption, or channel 112 provided between the first conductor 104 and the second conductor 106. While the gap or channel 112 provides good thermal isolation, this can cause many problems with the return current path. As a result, a third conductor 108 is provided to electrically connect the first conductor 104 and the second conductor 106. However, in order to provide thermal isolation between the first conductor 104 and the second conductor 106 (in this example, in the ground plane), the third conductor 108 is selected as a poor thermal conductor, such as a CuNi alloy or stainless steel. CuNi is a relatively good electrical conductor, but a poor thermal conductor.

[0020] Figure 4 This is a schematic diagram illustrating a superconducting quantum mechanical computer 200 according to an embodiment of the present invention. The superconducting quantum mechanical computer 200 includes a cooling system comprising a temperature-controlled container 202. The superconducting quantum computer includes a quantum processor 204 disposed within the temperature-controlled container 202, the quantum processor comprising a plurality of qubits 206. The superconducting quantum mechanical computer 200 also includes quantum mechanical circuitry 100 disposed within the temperature-controlled container 202. Figure 1 As shown, circuit 100 includes a substrate 102, a first electrical conductor 104 and a second electrical conductor 106 disposed on the substrate 102. Circuit 100 also includes a third electrical conductor 108 for electrically connecting the first electrical conductor 104 and the second electrical conductor 106, the third electrical conductor 108 being a poor thermal conductor. Each of a plurality of qubits 206 is provided on the substrate 102 and is electrically connected to ground at least via one of the first or second electrical conductors 104 and 106.

[0021] Figure 5This is a flowchart of a method for manufacturing a quantum mechanical circuit according to an embodiment of the present invention. The method includes: 1. In S100, a substrate 102 (e.g., silicon, polymer, laminate, glass fiber, etc.) having a top surface and a bottom surface is provided; 2. In S102, a conductive layer (e.g., a copper layer) is formed on at least one of the top and bottom surfaces of the substrate; 3. In S104, by removing a portion of the conductive layer, conductor lines are formed on the substrate 102 in a selected pattern, the conductor lines including a first electrical conductor 104 and a second electrical conductor 106 on the substrate 102, the first electrical conductor 104 and the second electrical conductor 106 being spaced apart and separated by a gap therebetween; and 4. In S106, a third conductor 108 is used ( Figure 2 (As shown in the figure) Electrically connects the first conductor 104 and the second conductor 106, and the third conductor 108 is a poor thermal conductor (e.g., CuNi or stainless steel). In one embodiment, the first conductor 104 and the second conductor 106 may be connected to an electrical ground.

[0022] The method further includes, prior to forming conductor lines in a selected pattern on substrate 102: 5. Apply a photoresist layer onto the conductive layer; 6. Apply a light-absorbing material in a selected pattern to the photoresist layer to cover the portion of the photoresist layer corresponding to the selected pattern; 7. Irradiate the photoresist layer with electromagnetic radiation (e.g., ultraviolet radiation) to harden the areas of the photoresist layer not covered by light-absorbing material; 8. Remove the areas of the photoresist layer corresponding to the uncured portions of the photoresist layer to expose portions of the conductive layer; 9. Etch away the exposed portion of the conductive layer, but do not etch the portion of the conductive layer beneath the hardened area of ​​the photoresist; 10. Remove the hardened areas of the photoresist layer to expose the unetched portions of the conductive layer, which correspond to a selected pattern, to form conductor lines; and 11. Form a via in the substrate at a selected location within the substrate.

[0023] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum mechanical circuit, comprising: Substrate; A first electrical conductor and a second electrical conductor are disposed on the same surface of the substrate and spaced apart to provide a gap therebetween; as well as A third electrical conductor connects the first and second electrical conductors. The thermal conductivity of the third electrical conductor is lower than that of the first electrical conductor and the second electrical conductor. Wherein, by providing the gap within the substrate between the first electrical conductor and the second electrical conductor, the first electrical conductor and the second electrical conductor are electrically decoupled; The third electrical conductor is coupled to the substrate using fasteners.

2. The quantum mechanical circuit as described in claim 1, wherein, The third electrical conductor includes at least one of copper-nickel (CuNi) or stainless steel.

3. The quantum mechanical circuit according to claim 2, wherein CuNi has a strength of 3.8 × 10⁻⁶ at ambient temperature. -8 The resistivity in Ωm and the thermal conductivity between 25 W / m·K and 40 W / m·K.

4. The quantum mechanical circuit as described in any one of claims 1 to 3, wherein, The first electrical conductor and the second electrical conductor comprise copper (Cu).

5. The quantum mechanical circuit according to any one of claims 1 to 3, wherein, The first electrical conductor, the second electrical conductor, and the third electrical conductor are configured to transmit radio frequency current.

6. The quantum mechanical circuit as described in claim 1, wherein, The fasteners comprise brass.

7. The quantum mechanical circuit as described in any one of claims 1 to 3, wherein, The first and second electrical conductors are connected to electrical ground.

8. The quantum mechanical circuit according to any one of claims 1 to 3 further includes an attenuator chip electrically coupled to the first electrical conductor and the second electrical conductor.

9. A superconducting quantum mechanical computer, comprising: Refrigeration systems, including temperature-controlled containers; A quantum processor comprising multiple qubits is disposed within the temperature-controlled container. as well as A superconducting circuit, disposed within the temperature-controlled container, the superconducting circuit comprising: Substrate; A first electrical conductor and a second electrical conductor are disposed on the same surface of the substrate and spaced apart to provide a gap therebetween; and A third electrical conductor connects the first and second electrical conductors, wherein the thermal conductivity of the third electrical conductor is lower than that of both the first and second electrical conductors. Each of the plurality of qubits is provided on the substrate and is electrically connected to ground via at least one of the first or second electrical conductors; Wherein, by providing the gap within the substrate and between the first electrical conductor and the second electrical conductor, the first electrical conductor and the second electrical conductor are electrically decoupled; The third electrical conductor is coupled to the substrate using fasteners.

10. The superconducting quantum mechanical computer according to claim 9, wherein, The third electrical conductor comprises at least one of copper-nickel (CuNi) or stainless steel.

11. The superconducting quantum mechanical computer according to claim 10, wherein, CuNi has a temperature of 3.8 × 10⁻⁶ at ambient temperature. -8 The resistivity in Ωm and the thermal conductivity between 25 W / m·K and 40 W / m·K.

12. The superconducting quantum mechanical computer according to any one of claims 9 to 11, wherein, The first electrical conductor and the second electrical conductor comprise copper (Cu).

13. The superconducting quantum mechanical computer according to any one of claims 9 to 11, wherein, The first electrical conductor, the second electrical conductor, and the third electrical conductor are configured to transmit radio frequency current.

14. The superconducting quantum mechanical computer according to any one of claims 9 to 11, wherein, The first and second electrical conductors are connected to electrical ground.

15. The superconducting quantum mechanical computer according to any one of claims 9 to 11, further comprising an attenuator chip electrically coupled to the first and second conductors.

16. A method for manufacturing a quantum mechanical circuit, comprising: Provide a substrate with a top surface and a bottom surface; A conductive layer is formed on at least one of the top and bottom surfaces of the substrate; By removing a portion of the conductive layer, a wire is formed on the substrate in a selected pattern. The wire includes a first electrical conductor and a second electrical conductor on the substrate, the first electrical conductor and the second electrical conductor being spaced apart and separated by a gap therebetween, wherein the first electrical conductor and the second electrical conductor are electrically decoupled by providing the gap within the substrate and between the first electrical conductor and the second electrical conductor. as well as The first and second conductors are electrically connected by a third conductor, the third conductor having a lower thermal conductivity than both the first and second conductors, wherein the third conductor is coupled to the substrate using fasteners.

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