Semiconductor device

Abstract

Provided is a semiconductor device that is easy to assemble, has high reliability, and is resistant to corrosion. The semiconductor device includes a mounting member (1) having a wiring layer (1b) that has copper as a main component; a first cover layer (2) that contains nickel and covers the wiring layer (1b) in such a manner that a portion of the upper surface of the wiring layer (1b) is exposed at an opening (8); a bonding layer (3) that is metallically bonded to the wiring layer (1b) at the opening (8); a second cover layer (6) that contains nickel and is metallically bonded to the upper surface of the bonding layer (3); and a semiconductor chip (7) whose lower surface is covered by the second cover layer (6). The bonding layer (3) has a lower layer (5a) that is in contact with the wiring layer (1b), an upper layer (5b) that is in contact with the second cover layer (6), and an intermediate layer (4) between the lower layer (5a) and the upper layer (5b), the lower layer (5a) and the upper layer (5b) contain an intermetallic compound containing tin, copper, and nickel as a main component, and the intermediate layer (4) is an alloy that has tin as a main component and does not contain lead.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] In typical semiconductor devices, semiconductor chips carrying semiconductor components are bonded to mounting substrates such as printed wiring boards (PWB), insulating circuit boards, or lead frames. In recent years, lead-free (Pb-free) solders, which do not contain lead (Pb) harmful to the environment and human health, have become the primary bonding material for semiconductor devices. For example, tin-silver (SnAg) and tin-antimony (SnSb) based solders (Sn-based solders) are used as lead-free solders. Compared to the melting point of the traditional SnPb eutectic solder (around 183°C), SnAg-based solders have a melting point about 40°C higher, and SnSb-based solders have a melting point about 60°C higher. Mounting substrates use metal coatings such as copper foil and silver solder. To prevent the copper (Cu) and silver (Ag) in the metal coating from being corroded by hydrogen sulfide, a nickel (Ni) plating is applied to the surface of the metal layer.

[0003] In a semiconductor device where a semiconductor chip is bonded to a mounting substrate with a Ni-coated layer using Sn-based solder, a Ni-Sn intermetallic compound is formed in a flat, layered manner at the bonding layer interface. If such a semiconductor device is subjected to temperature cycling and power cycling tests, cracks extend parallel to the semiconductor chip from the edge of the chip towards the interior of the bonding layer, leading to premature failure of the semiconductor device.

[0004] Patent Document 1 describes a two-layer structure where the bonding layer formed between the Cu wiring layer of the mounting substrate and the semiconductor chip is a Cu3Sn intermetallic compound layer on the Cu wiring layer side and a (Cu,Ni)6Sn5 intermetallic compound layer on the semiconductor chip side, thereby suppressing crack formation. In Patent Document 1, a bonding material in which a Ni thin film, a Sn thin film, a Ni thin film, and a Cu thin film are sequentially stacked between the Cu wiring layer and the semiconductor chip is used, and bonding is performed at a temperature of approximately 232°C to 400°C using a liquid phase diffusion bonding method.

[0005] Patent documents 2 and 3 describe methods for forming a bonding layer by providing a Cu layer between a Ni-plated component to be bonded and a Sn-based solder to suppress Ni corrosion. Patent document 2 discloses that a Cu6Sn5 or (Cu,Ni)6Sn5 compound layer is formed at the central portion and a Ni3Sn4 or (Ni,Cu)3Sn4 compound layer is formed at the outer periphery between the bonding layer and the component to be bonded. Patent document 3 discloses forming a Cu6Sn5 or (Cu,Ni)6Sn5 compound layer between the component to be bonded and the Sn-based solder layer by heating at a temperature above the solidus temperature and below the liquidus temperature of the Sn-based solder.

[0006] Patent document 4 describes a method for soldering a Ni plating layer using a Sn-based solder with added Cu as the bonding material, thereby forming a Cu-Sn compound layer on the Ni plating layer.

[0007] If a Sn-based solder with added Cu is used, a Cu-Sn compound layer forms at the bonding interface, which can suppress crack propagation. However, adding Cu to the solder increases the melting point, thus raising the solder bonding temperature and increasing the thermal deformation of the bonded components. In addition, the viscosity also increases, thus deteriorating the solder's printability. As a result, the assemblability of the semiconductor device decreases.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2020-155761

[0011] Patent Document 2: Japanese Patent Application Publication No. 2018-85366

[0012] Patent Document 3: Japanese Patent Application Publication No. 2018-85360

[0013] Patent Document 4: Japanese Patent No. 6429208 Summary of the Invention

[0014] The problem the invention aims to solve

[0015] In view of the above-mentioned problems, the object of the present invention is to provide a semiconductor device that is easy to assemble and has high reliability and corrosion resistance.

[0016] Solution for solving the problem

[0017] The essence of one technical solution of the present invention is a semiconductor device comprising: (a) a mounting member having a wiring layer with copper as the main component; (b) a first cover layer containing nickel and covering the wiring layer such that a portion of the upper surface of the wiring layer is exposed at an opening; (c) a bonding layer metallically bonded to the wiring layer at the opening; (d) a second cover layer containing nickel and metallically bonded to the bonding layer at the upper surface of the bonding layer; and (e) a semiconductor chip having its lower surface covered by the second cover layer, the bonding layer having a lower layer in contact with the wiring layer, an upper layer in contact with the second cover layer, and an intermediate layer between the lower and upper layers, the lower and upper layers comprising an intermetallic compound containing tin, copper, and nickel as the main component, and the intermediate layer being an alloy with tin as the main component and free of lead.

[0018] The effects of the invention

[0019] According to the present invention, a semiconductor device that is easy to assemble and has high reliability and corrosion resistance can be provided. Attached Figure Description

[0020] Figure 1 This is a schematic cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present invention.

[0021] Figure 2 yes Figure 1 An enlarged view of part A in the image.

[0022] Figure 3 This is a schematic cross-sectional view of an example of a conventional semiconductor device.

[0023] Figure 4 yes Figure 3 An enlarged view of part B in the image.

[0024] Figure 5 This is a schematic cross-sectional view of the semiconductor device after a power cycling test has been performed on it according to the implementation method.

[0025] Figure 6 yes Figure 5 (a) SEM image, (b) Sn distribution image, (c) Ni distribution image and (d) Cu distribution image of part C.

[0026] Figure 7 This is a cross-sectional schematic diagram after a power cycle test was performed on a previous semiconductor device.

[0027] Figure 8 yes Figure 7 (a) SEM image of part D, (b) Sn distribution image and (c) Ni distribution image.

[0028] Figure 9 This is a schematic cross-sectional view showing an example of the process of manufacturing a semiconductor device according to an embodiment.

[0029] Figure 10 This is the next step in illustrating the manufacturing method of the semiconductor device according to the embodiment. Figure 9 A schematic cross-sectional view of an example of the process.

[0030] Figure 11 This is the next step in illustrating the manufacturing method of the semiconductor device according to the embodiment. Figure 10 A schematic cross-sectional view of an example of the process. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc., may sometimes differ from reality. Furthermore, the drawings may also contain parts with different dimensional relationships or ratios. Additionally, the embodiments shown below exemplify apparatus and methods for embodying the technical concept of the present invention; the technical concept of the present invention does not specify the material, shape, structure, arrangement, etc., of the constituent components as described below.

[0032] Furthermore, the definitions of up and down directions in the following description are merely for ease of explanation and do not limit the technical concept of the present invention. For example, if the object is rotated 90° for observation, the up and down direction is transformed into left and right for reading; if it is rotated 180° for observation, the up and down direction is reversed for reading. Similarly, the relationship between "front" and "back" is also such that if rotated 180°, the term "reversed" is defined.

[0033] like Figure 1 As shown, the semiconductor device according to an embodiment of the present invention includes a mounting member 1, a cover layer (first cover layer) 2, a bonding layer 3, a cover layer (second cover layer) 6, and a semiconductor chip 7. The mounting member 1, for example, has an insulating substrate 1a and a wiring layer 1b primarily composed of copper (Cu). The cover layer 2 contains nickel (Ni) and covers the wiring layer 1b. The cover layer 2 has an opening 8 that exposes a portion of the upper surface of the wiring layer 1b. The bonding layer 3 has a lower layer 5a metallically bonded to the wiring layer 1b at the opening 8 of the cover layer 2, an upper layer 5b metallically bonded to the cover layer 6, and an intermediate layer 4 between the lower layer 5a and the upper layer 5b. The intermediate layer 4 is an alloy layer primarily composed of Sn. The cover layer 6 contains nickel (Ni) and covers the lower surface of the semiconductor chip 7.

[0034] In this embodiment, the mounting member 1 is exemplified as an insulating circuit board with a wiring layer 1b provided on the upper surface of an insulating substrate 1a. The insulating circuit board can be, for example, a direct copper bonding (DCB) substrate with copper (Cu) eutecticly bonded to the surface of a ceramic substrate, or an AMB substrate with metals such as copper (Cu) disposed on the surface of a ceramic substrate using active metal soldering (AMB). The ceramic substrate material can be, for example, silicon nitride (Si3N4), aluminum nitride (AlN), or aluminum oxide (Al2O3). It should be noted that the mounting member 1 can also be a printed circuit board (PCB) with a wiring layer primarily composed of copper (Cu) on a resin substrate, or a wiring component such as a lead frame, metal plate, or metal foil primarily composed of copper (Cu) or aluminum (Al).

[0035] In the description of the implementation method, silicon carbide (SiC) is used as the semiconductor material for the semiconductor chip 7. In addition to SiC, other semiconductor materials such as silicon (Si), gallium nitride (GaN), lansdaleite (hexagonal diamond), and aluminum nitride (AlN) can also be used in the semiconductor chip 7. Semiconductor elements forming the semiconductor chip 7 include three-terminal elements such as IGBTs and MOSFETs, and two-terminal elements such as freewheeling diodes (FWD) and Schottky barrier diodes (SBD). Furthermore, bipolar transistors (BPTs), electrostatic induction transistors (SITs), electrostatic induction thyristors (SI thyristors), and gate turn-off thyristors (GTO thyristors) can also be used as semiconductor elements. From the viewpoint of corrosion resistance, cover layers 2 and 6 are respectively coated with Ni or the like on the upper surface of the wiring layer 1b of the mounting member 1 and the lower surface of the semiconductor chip 7.

[0036] When bonding the semiconductor chip 7 to the wiring layer 1b of the mounting component 1, a lead-free solder that does not contain Pb, which is harmful to the environment and human body, is used as the bonding material. For example, Sn-based solders with Sn as the main component, such as SnAg-based or SnSb-based solders, are used as lead-free solders. It should be noted that, in addition to the main additive elements Ag and Sb, Sn-based solders may also contain trace amounts of additive elements such as indium (In), zinc (Zn), bismuth (Bi), and magnesium (Mg). Sn-based solders preferably do not contain Cu, but if the content is trace, for example, less than 0.5% by mass, Cu may be included. Figure 1 The upper surface of the wiring layer 1b exposed at the opening 8 of the cover layer 2 is deposited with a bonding material, such as lead-free solder, using printing technology. A semiconductor chip 7, whose lower surface is covered by the cover layer 6, is then placed on top of the bonding material. Subsequently, in a bonding process, the semiconductor chip 7 is soldered to the mounting member 1 using a reflow oven or similar heating method at approximately 260°C. During this soldering process, the molten bonding material wets the wiring layer 1b and the cover layer 6, thereby metallically bonding the bonding layer 3 to the wiring layer 1b exposed at the opening 8 of the cover layer 2, and also metallically bonding to the cover layer 6. As a result, a bonding layer 3 is formed having a lower layer 5a in contact with the wiring layer 1b, an upper layer 5b in contact with the cover layer 6, and an intermediate layer 4 between the lower layer 5a and the upper layer 5b.

[0037] During the bonding process, as the bonding material is heated, Cu diffuses from wiring layer 1b into the molten bonding material, and Ni diffuses from capping layer 6 into the molten bonding material. At the interface between the molten bonding material and capping layer 6, an intermetallic compound containing Sn and Ni (hereinafter also referred to as Sn-Ni compound) is formed by Ni diffusing from capping layer 6. At this time, Cu diffuses from wiring layer 1b into the bonding material, forming an intermetallic compound containing Sn, Cu, and Ni (hereinafter also referred to as Sn-Cu-Ni (intermetallic) compound) at the interface on the capping layer 6 side, which acts as a barrier to the diffusion of Ni from capping layer 6. Therefore, the formation of Sn-Ni compound on the capping layer 6 side is restricted. Furthermore, during the cooling of the bonding material, the Sn-Cu-Ni compound solidifies into a columnar shape at the interface with wiring layer 1b and capping layer 6. As a result, as... Figure 1 As shown, after cooling, the bonding layer 3 forms a lower layer 5a and an upper layer 5b containing a Sn-Cu-Ni compound. The Sn-Cu-Ni compound mainly contains (Cu,Ni)6Sn5, and may also contain Cu3Sn containing trace amounts of Ni. Additionally, the intermediate layer 4 is an alloy with Sn as the main component and does not contain Pb. The intermediate layer 4 also contains Ag or Sb as components of the bonding material. The intermediate layer 4 may also contain Cu and Ni diffused from the wiring layer 1b and the capping layer 6. The lower layer 5a and the upper layer 5b each have a rough surface with multiple columnar protrusions forming towards the intermediate layer 4. The Sn-Cu-Ni intermetallic compound forming the lower layer 5a and the upper layer 5b has higher mechanical strength than the Sn-based alloy forming the intermediate layer 4. It should be noted that, from the viewpoint of corrosion resistance, as... Figure 1 As shown, it is desirable that the bonding material melts during the reflow soldering process, and the solder bonding end (filler) 9 is formed in such a way that the end of the bonding layer 3 covers the exposed wiring layer 1b at the opening 8 of the cover layer 2 and contacts the upper surface of the cover layer 2.

[0038] Figure 2 yes Figure 1 A magnified view of part A, namely the junction between the cover layer 6 and the bonding layer 3 covering the semiconductor chip 7. (See diagram below.) Figure 2 As shown, the semiconductor chip 7 has a semiconductor layer 7a such as SiC and an electrode layer 7b such as titanium (Ti). At the interface between the capping layer 6 and the bonding layer 3, a small amount of Ni corrosion occurs in the capping layer 6. Furthermore, the upper layer 5b of the bonding layer 3 has a rough surface with multiple columnar protrusions forming towards the intermediate layer 4. If temperature cycling and power cycling tests are performed on the semiconductor device, cracks 10 are generated at the bonding interface near the end of the semiconductor chip 7 due to thermal stress. The generated cracks 10 tend to extend into the intermediate layer 4, which has low mechanical strength and is mainly composed of Sn, but... Figure 2As shown, the propagation of crack 10 into the intermediate layer 4 is suppressed by the protrusions of the upper layer 5b, which is mainly composed of intermetallic compounds and has high mechanical strength. Furthermore, although not shown in the figure, the lower layer 5a of the bonding layer 3 also has a rough surface with multiple columnar protrusions forming towards the intermediate layer 4. Therefore, cracks generated at the bonding interface on the mounting member 1 side are also suppressed from propagating into the intermediate layer 4. In addition, the wiring layer 1b of the mounting member 1 is covered by the cover layer 2 except for the opening 8, thus ensuring corrosion resistance. In this embodiment, Sn-based solders such as SnAg-based or SnSb-based solders that do not contain a large amount of Cu are used as the bonding material. Therefore, thermal deformation and deterioration of solder printability caused by increases in the melting point and viscosity of the bonding material can be prevented, and the reduction in the assemblability of the semiconductor device can be suppressed.

[0039] In conventional semiconductor devices, the entire surface of the wiring layer, which is mainly composed of Cu, on the mounting substrate is plated with Ni to ensure corrosion resistance. Figure 3 This is a cross-sectional view of a semiconductor device using a conventional mounting substrate with Ni plating. (Example) Figure 3 As shown, a conventional semiconductor device includes a mounting member 1, a cover layer 12, a bonding layer 13, a cover layer 16, and a semiconductor chip 7. The mounting member 1 has an insulating substrate 1a and a wiring layer 1b mainly composed of Cu. The cover layer 12 contains Ni and covers the entire upper surface of the wiring layer 1b. The bonding layer 13 has a lower layer 15a metallically bonded to the upper surface of the cover layer 12, an upper layer 15b metallically bonded to the cover layer 16, and an intermediate layer 14 between the lower layer 15a and the upper layer 15b. The lower surface of the semiconductor chip 7 is covered by the Ni-containing cover layer 16.

[0040] Similar to the embodiment, in conventional semiconductor devices, a bonding material, which serves as lead-free solder, is deposited on the cover layer 12 covering the upper surface of the mounting member 1 using printing technology or the like. A semiconductor chip 7, whose lower surface is covered by the cover layer 16, is then placed on the bonding material. Subsequently, in a bonding process, the semiconductor chip 7 is soldered to the mounting member 1 by heating to approximately 260°C in a reflow oven or the like. Through this soldering process, the bonding material is metallically bonded to both the cover layer 12 and the cover layer 16. As a result, a bonding layer 13 is formed, comprising a lower layer 15a in contact with the cover layer 12, an upper layer 15b in contact with the cover layer 16, and an intermediate layer 14 between the lower layer 15a and the upper layer 15b.

[0041] During the heating process of the bonding step, Ni diffuses from capping layer 12 and capping layer 16 into the molten bonding material, but the diffusion of Cu from the wiring layer 1b covered by capping layer 12 is hindered. Therefore, as Figure 3As shown, in the cooled bonding layer 13, intermetallic compounds containing Sn and Ni are formed in a layered manner as the lower layer 15a and the upper layer 15b. For example, as the lower layer 15a, Ni3Sn2 intermetallic compound is mainly stacked on the capping layer 12 side, and Ni3Sn4 intermetallic compound is mainly stacked on the intermediate layer 14 side. As the upper layer 15b, Ni3Sn2 intermetallic compound is mainly stacked on the capping layer 16 side, and Ni3Sn4 intermetallic compound is mainly stacked on the intermediate layer 14 side. The intermediate layer 14 of the bonding layer 13 is an alloy with Sn as the main component and does not contain Pb. In addition, the intermediate layer 14 contains Ag or Sb and Ni.

[0042] Figure 4 yes Figure 3 The image shows an enlarged view of part B, specifically the junction between the cover layer 16 and the bonding layer 13 covering the semiconductor chip 7. Figure 4 As shown, the semiconductor chip 7 has a semiconductor layer 7a and an electrode layer 7b. At the interface between the capping layer 16 and the bonding layer 13, the capping layer 16 experiences significant Ni corrosion. Furthermore, since the upper layer 15b, primarily composed of Sn-Ni intermetallic compounds, is formed as a flat layer, cracks 10a generated at the ends of the bonding layer 13 tend to propagate in one direction parallel to the semiconductor chip 7 within the intermediate layer 14, leading to premature failure of the semiconductor device. Although not shown in the figure, at the interface with the bonding layer 13, significant Ni corrosion occurs in the capping layer 12, and the lower layer 15a, primarily composed of Sn-Ni intermetallic compounds, is formed as a flat layer facing the intermediate layer 14.

[0043] Figure 5 This is a cross-sectional view after the semiconductor device of the embodiment has undergone 100,000 power cycling tests. Figure 5 As shown, a filler 9 is formed such that the end of the bonding layer 3 covers the exposed wiring layer 1b at the opening 8 of the cover layer 2 and contacts the upper surface of the cover layer 2. Cracks 10 generated at the interface with the bonding layer 3 are locally present near the end of the semiconductor chip 7.

[0044] Figure 6 express Figure 5 The observations in Part C of this study are based on a scanning microscope / energy dispersive X-ray analysis (SEM / EDX) system. Figure 6 In the image, (a) represents the SEM image, (b) represents the Sn distribution image, (c) represents the Ni distribution image, and (d) represents the Cu distribution image. Figure 6 As shown in (a), the crack 10 generated at the interface of the bonding layer 3 near the end of the semiconductor chip 7 after the power cycling test was restricted from propagation and existed locally in a slight state. Figure 6As shown in image (b), the Sn distribution pattern reveals that dark gray areas are formed in a protruding manner near the interface of the capping layer 6 and gray areas are formed inside the bonding layer 3. Figure 6 In (b), the gray area corresponds to the middle layer 4 with a higher Sn content, and the protruding dark gray area is presumed to correspond to the upper layer 5b with a lower Sn content than the middle layer 4. For example... Figure 6 As shown in image (c), the Ni distribution corresponds to the light gray areas formed in the Ni-containing capping layer 6, and the gray areas are scattered corresponding to the granular Ni precipitates in the bonding layer 3. Figure 6 As shown in the Cu distribution image (d), gray areas are formed in a protruding shape corresponding to the Cu-containing upper layer 5b. It can be seen that in the semiconductor device of the embodiment, the upper layer 5b, which is mainly composed of Sn-Ni-Cu intermetallic compound, is formed in a protruding shape to suppress the propagation of cracks 10 generated at the interface of the bonding layer 3.

[0045] Figure 7 This is a cross-sectional view after performing 30,000 power cycle tests on a conventional semiconductor device. (Example) Figure 7 As shown, bonding layer 13 is formed on the upper surface of capping layer 12. Cracks 10a generated at the interface with bonding layer 13 extend parallel to semiconductor chip 7 within bonding layer 13.

[0046] Figure 8 express Figure 7 The observations based on SEM / EDX in part D of the diagram. Figure 8 In the image, (a) represents the SEM image, (b) represents the Sn distribution image, and (c) represents the Ni distribution image. For example... Figure 8 As shown in (a), it can be seen that after the power cycling test, the crack 10a generated at the interface of the bonding layer 13 near the end of the semiconductor chip 7 extends parallel to the semiconductor chip 7 within the bonding layer 13. According to Figure 8 Images (b) and (c) show the Sn and Ni distribution patterns. Sn and Ni are distributed in layers near the interface of the capping layer 16 of the bonding layer 13. It is presumed that the layers where Sn and Ni are distributed correspond to the upper layer 15b of the bonding layer 13. In this way, in conventional semiconductor devices, the upper layer 15b, which mainly contains the Sn-Ni intermetallic compound, is formed in a layered manner. Therefore, the crack 10a generated at the interface of the bonding layer 13 extends into the bonding layer 13 parallel to the semiconductor chip 7, causing early failure of the semiconductor device.

[0047] Next, refer to Figures 9-11 The manufacturing method of the semiconductor device according to the embodiment will be described. Hereinafter, an insulating circuit board will be used as the mounting member 1, but it can also be a wiring member such as a printed wiring board (PCB), lead frame, metal plate, or metal foil.

[0048] First, an insulating circuit substrate 1 is prepared, with a wiring layer 1b mainly composed of Cu on the upper surface of the insulating substrate 1a. A photoresist film is then coated on the upper surface of the wiring layer 1b, such as... Figure 9 As shown, a photoresist film is patterned using photolithography or similar techniques to form a photoresist mask 20. Using the photoresist mask 20 as a plating mask, a Ni plating layer is selectively formed on the upper surface of the wiring layer 1b. The photoresist mask 20 is then removed, as... Figure 10 As shown, a Ni-containing capping layer 2 with openings 8 is formed on the upper surface of the wiring layer 1b. It should be noted that, after plating the entire surface of the wiring layer 1b of the mounting member 1 with Ni, the capping layer 2 can be formed by selectively setting the openings 8 in the Ni plating layer through laser processing or machining. Alternatively, the capping layer 2 can be formed by selectively setting the openings 8 in the Ni plating layer covering the entire surface of the wiring layer 1b using photolithography and etching techniques.

[0049] Next, as Figure 11 As shown, Sn-based lead-free solder, such as SnAg-based solder, is deposited as bonding material 3a on the upper surface of the wiring layer 1b exposed at the opening 8 of the cover layer 2 using printing technology or the like. A semiconductor chip 7, whose lower surface is covered by a Ni-containing cover layer 6, is placed on the deposited bonding material 3a. Then, in the bonding process, the semiconductor chip 7 is soldered to the mounting member 1 by heating to approximately 260°C using a reflow oven or the like. During the heating in the reflow oven, the bonding material 3a melts and wets the wiring layer 1b and the cover layer 6. Cu diffuses from the wiring layer 1b into the molten bonding material 3a, and Ni diffuses from the cover layer 6 into the molten bonding material 3a. After the bonding process, as... Figure 1 As shown, a lower layer 5a, an intermediate layer 4, and an upper layer 5b are formed on the cooled bonding layer 3. The lower layer 5a is metallically bonded to the wiring layer 1b exposed at the opening 8 of the cover layer 2. The upper layer 5b is metallically bonded to the cover layer 6. The intermediate layer 4 is formed between the lower layer 5a and the upper layer 5b. The lower layer 5a and the upper layer 5b contain solidified intermetallic compounds containing Sn, Cu, and Ni in a protruding form, while the intermediate layer 4 contains an alloy with Sn as the main component. During the bonding process, the molten bonding material 3a extends across the opening 8 and onto the upper surface of the cover layer 2, thereby forming a filler 9 at the end of the bonding layer 3. Thus, the bonding process is completed. Figure 1 The semiconductor device shown.

[0050] In this embodiment, the surface of the wiring layer 1b of the mounting member 1 is selectively covered by the capping layer 2, and Sn-based solder is deposited on the wiring layer 1b exposed at the opening 8. During the bonding process, Cu diffuses from the wiring layer 1b into the molten bonding material 3a, forming a lower layer 5a and an upper layer 5b containing a Sn-Cu-Ni compound. Cracks 10 generated near the end of the semiconductor chip 7 meander through protrusions in the upper layer 5b, which contains a Sn-Cu-Ni compound as the main component and has high mechanical strength. Therefore, the propagation of cracks 10 into the intermediate layer 4 can be suppressed. In addition, the wiring layer 1b of the mounting member 1 is covered by the Ni-containing capping layer 2 except at the opening 8, thus ensuring corrosion resistance. Furthermore, in this embodiment, since Sn-based solder that does not substantially contain Cu is used, thermal deformation and deterioration of solder printability caused by the increase in the melting point and viscosity of the bonding material 3a can be prevented, and the reduction in the assemblability of the semiconductor device can be suppressed.

[0051] (Other implementation methods)

[0052] The present invention has been described through the embodiments disclosed above, but the discussions and drawings that constitute a part of this disclosure should not be construed as limiting the invention. Based on the disclosure of the specification and drawings of the present invention, those skilled in the art should recognize that various alternative embodiments, examples, and techniques will be apparent. Furthermore, this naturally includes structures in which the structures described in the above embodiments and variations are arbitrarily applied, and various embodiments not described herein. Therefore, the scope of protection of the present invention is determined only by the technical features appropriate to the foregoing exemplary description and those involved in the claims.

[0053] Explanation of reference numerals in the attached figures

[0054] 1 Installation components

[0055] 1a Insulating substrate

[0056] 1b Wiring Layer

[0057] 2. Covering layer (first covering layer)

[0058] 3, 13 bonding layer

[0059] 3a Bonding material

[0060] 4.14 Intermediate Layer

[0061] 5a, 15a lower layer

[0062] 5b, 15b upper layer

[0063] 6. Covering layer (2nd covering layer)

[0064] 7 Semiconductor chips

[0065] 7a Semiconductor layer

[0066] 7b Electrode Layer

[0067] 8. Opening

[0068] 9. Joint end (fill in the corner)

[0069] 10, 10a cracks

[0070] 12, 16 Covering Layers

[0071] 20 Resist Mask

Claims

1. A semiconductor device, characterized in that, This semiconductor device has: The mounting components have a wiring layer that is primarily composed of copper. A first cover layer containing nickel covers the wiring layer in such a way that a portion of the upper surface of the wiring layer is exposed at the opening; A bonding layer that is metallically bonded to the wiring layer at the opening; A second cover layer containing nickel is metallically bonded to the bonding layer on its upper surface. as well as The semiconductor chip, the lower surface of which is covered by the second capping layer, The bonding layer has a lower layer in contact with the wiring layer, an upper layer in contact with the second cover layer, and an intermediate layer between the lower layer and the upper layer. The lower and upper layers contain intermetallic compounds containing tin, copper, and nickel as the main components, and the middle layer is an alloy with tin as the main component and no lead.

2. The semiconductor device according to claim 1, characterized in that, The main component of the intermetallic compound is (Cu,Ni)6Sn5.

3. The semiconductor device according to claim 1 or 2, characterized in that, The alloy contains silver or antimony.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The end of the bonding layer contacts the upper surface of the first covering layer in a manner that covers the opening.

Images