Vertical memory device and method of operating the same

Abstract

The present disclosure relates to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line below the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can also include applying a ground voltage to the word line and applying a ground voltage to the bit line.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more particularly to a method for forming and operating a vertical memory device. Background Technology

[0002] Planar memory cells can be miniaturized to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Vertical memory architectures can address the density limitations of planar memory cells. Summary of the Invention

[0003] This disclosure describes embodiments of vertical memory structures and methods of forming thereof.

[0004] In some embodiments, a method may include performing a programming operation on a memory device. The memory device may include: a bottom select gate; a board line above the bottom select gate; a word line above the board line; a pillar extending through the bottom select gate, the board line, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method may include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method may further include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method may further include applying a ground voltage to the word line and applying a ground voltage to the bit line.

[0005] In some embodiments, a method may include performing an erase operation on a memory device. The memory device may include: a bottom select gate; a board line above the bottom select gate; a word line above the board line; a pillar extending through the bottom select gate, the board line, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method may include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the board line. The method may further include reducing the first positive voltage bias to the bottom select gate and applying a negative voltage bias to the source line.

[0006] In some embodiments, a method may include performing a programming operation on a memory device. The memory device may include: a board line; a bias gate above the board line; a word line above the board line; a post extending through the board line, the bias gate, and the word line; a source line below the post; a drain cap above the post; and a bit line formed above the drain cap. The method may include applying a first positive voltage bias to the bias gate and applying a second positive voltage bias to the word line. The method may further include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method may further include applying a ground voltage to the word line and applying a ground voltage to the bit line.

[0007] In some embodiments, a method may include performing an erase operation on a memory device. The memory device may include: a board line; a bias gate above the board line; a word line above the board line; a pillar extending through the board line, the bias gate, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method may include applying a first positive voltage bias to the bias gate and applying a second positive voltage bias to the board line. The method may further include reducing the first positive voltage bias to the bias gate and applying a negative voltage bias to the source line. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0009] Figure 1A A schematic cross-sectional view of an exemplary vertical memory cell according to some embodiments of the present disclosure is shown.

[0010] Figure 1B A schematic top view of a memory array according to some embodiments of the present disclosure is shown.

[0011] Figure 2 A schematic cross-sectional view of an exemplary vertical memory cell incorporating a bottom select gate (BSG) according to some embodiments of the present disclosure is shown.

[0012] Figure 3 A flowchart illustrating the formation of a memory structure having a bottom select gate according to some embodiments of the present disclosure is shown.

[0013] Figures 4A-4G Cross-sectional views of memory structures at various process stages according to some embodiments of the present disclosure are shown.

[0014] Figure 5A A flowchart illustrating a programming scheme for a memory structure having a bottom select gate according to some embodiments of the present disclosure is shown.

[0015] Figure 5B The diagram illustrates an operational scheme for performing a programming scheme on a memory structure with a bottom select gate according to some embodiments of the present disclosure.

[0016] Figure 6A A flowchart illustrating an erase scheme for a memory structure having a bottom select gate, according to some embodiments of the present disclosure, is shown.

[0017] Figure 6B Operational diagrams are shown for performing an erase scheme on a memory structure having a bottom select gate according to some embodiments of the present disclosure.

[0018] Figure 7 A schematic cross-sectional view of an exemplary vertical memory cell incorporating a biased gate, according to some embodiments of the present disclosure, is shown.

[0019] Figure 8 A schematic cross-sectional view of an exemplary memory structure incorporating a biased gate, according to some embodiments of the present disclosure, is shown.

[0020] Figure 9A A flowchart illustrating a programming scheme for a memory structure with biased gates according to some embodiments of the present disclosure is shown.

[0021] Figure 9B Operational diagrams are shown for performing a programming scheme on a memory structure with biased gates according to some embodiments of the present disclosure.

[0022] Figure 10A A flowchart illustrating an erase scheme for a memory structure with biased gates according to some embodiments of the present disclosure is shown.

[0023] Figure 10B Operational diagrams illustrating an erase scheme for a memory structure with biased gates according to some embodiments of the present disclosure are shown.

[0024] The features and advantages of the invention will become more apparent when viewed in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. Similar reference numerals in the drawings generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral(s) of the corresponding reference numeral(s).

[0025] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0026] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0027] Note that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in this specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment need not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge scope of those skilled in the art.

[0028] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0029] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with an intermediate feature or layer in between. Furthermore, “above” or “on top of” means not only “above” or “on top of” something, but also includes “above” or “on top of” something without an intermediate feature or layer in between (i.e., directly on) something.

[0030] Furthermore, spatial relative terms, such as “below,” “under,” “down,” “above,” and “above,” are used herein for ease of description to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in device use or process steps other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0031] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed on the top side of the substrate, unless otherwise stated. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0032] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively distant from the substrate. A layer may extend over the entire upper or lower layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0033] In this disclosure, for ease of description, the term "level" is used to refer to elements that have substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as a "level", a word line and the underlying insulating layer together may be referred to as a "level", word lines having substantially the same height may be referred to as a "word line level" or similar, and so on.

[0034] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0035] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0036] Dynamic random access memory (DRAM) is a type of random access semiconductor memory that can store each bit of data in a memory cell. Some types of memory cells include capacitors and arrayed transistors, also known as a 1T1C memory structure. Capacitors can be set to a charged or discharged state, representing bit values ​​of zero and one, respectively. As DRAM technology advances towards higher device density and higher storage capacity, the number of capacitors has increased dramatically, while the footprint of each capacitor has decreased. Changes in the number and size of capacitors can lead to longer process times and more complex process flows. Capacitor-less one-transistor (CRT) memory structures (also known as 1T memory structures) have been developed to improve device density and storage capacity. However, CRT structures face challenges such as word line floating and host capacitive coupling, which affect device performance.

[0037] Various embodiments of this disclosure provide structures and methods of fabricating capacitor-free multi-gate vertical 1T memory structures that improve data retention and reduce leakage current. A capacitor-free multi-gate vertical 1T memory structure may include pillars (e.g., vertical cylindrical floating bodies) and a plurality of gates surrounding the pillars. In some embodiments, the pillars may be surrounded by a top select gate, a board line gate, and a bottom select gate. In some embodiments, the pillars may be surrounded by a word line gate, a bias gate, and a board line gate. Bit lines may be formed above the pillars. Memory cells are formed at intersections between word lines and bit lines. The capacitor-free multi-gate vertical 1T memory structure of this disclosure can provide various benefits, including, but not limited to, improved transistor carrier density, improved programming / erasing speed, etc.

[0038] Figure 1A and Figure 1B This is a diagram illustrating a memory structure according to some embodiments of the present disclosure. Figure 1A A cross-sectional view of a capacitorless dual-gate vertical 1T memory cell 100 is shown. The memory cell 100 may be formed on a substrate 102 and may include a source line 104, a pillar 106, a plate line gate 108, a word line 110, a drain cap 112, and a bit line 114. Figure 1B This is a top view of a memory array 150 including multiple memory cells 100. Additional structures may be included, and for simplicity, the additional structures are... Figure 1A and Figure 1B It is not shown in the document.

[0039] Substrate 102 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, group III-V compounds, any other suitable material, and any combination thereof. In some embodiments, substrate 102 may be double-polished prior to peripheral device fabrication. In this example, substrate 102 includes surfaces on both the top and bottom sides, which are polished and processed to provide a smooth surface for high-quality semiconductor devices. In some embodiments, substrate 102 may be a dielectric layer formed of silicon, silicon oxide, silicon nitride, or any suitable dielectric material.

[0040] Source line 104 may be formed on substrate 102. In some embodiments, source line 104 may be a conductive structure, such as a semiconductor layer doped with a suitable dopant. In some embodiments, source line 104 may be formed of silicon material and doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, lithium, and / or combinations thereof. In some embodiments, the dopant concentration of the n-type dopant may be approximately 1 × 10⁻⁶. 18 atoms / cm 3 Up to approximately 1×10 22 atoms / cm 3 Between. In some embodiments, the dopant concentration of the n-type dopant can be greater than about 1 × 10⁻⁶. 20 atoms / cm 3 .

[0041] Pillar 106 may be formed on and electrically coupled to source line 104. Pillar 106 may extend in a vertical direction (e.g., z-direction) with reference to the top surface of substrate 102. In some embodiments, pillar 106 may be formed of a pillar structure, such as a cylinder having a rectangular cross-sectional shape. Pillar 106 may be formed of a semiconductor material doped with a suitable dopant. For example, pillar 106 may be silicon material doped with a p-type dopant, such as boron, aluminum, nitrogen, gallium, indium, and / or combinations thereof. In some embodiments, the dopant concentration of the p-type dopant may be approximately 1 × 10⁻⁶. 10 atoms / cm 3 Up to approximately 1×10 20 atoms / cm 3 In some embodiments, pillar 106 may be formed using an intrinsic semiconductor material, such as intrinsic polysilicon.

[0042] The plate line 108 is formed adjacent to the post 106. In some embodiments, the plate line 108 surrounds the lower portion of the sidewall surface of the post 106. For example, the sidewall surface of the plate line 108 may be positioned around the circumference of the post 106. In some embodiments, the sidewall surface of the plate line 108 may be concentric with the sidewall surface of the post 106. In some embodiments, the dielectric layer 111 ( Figure 1A Not shown in the image, but... Figure 1B (As shown in the figure) can be disposed between plate line 108 and post 106. Plate line 108 can be formed using a suitable conductive material, such as tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicide and / or combinations thereof.

[0043] The letter line 110 is formed adjacent to the post 106 and above the plate line 108. In some embodiments, the post 106 may be formed of a post structure, and the letter line 110 surrounds the upper portion of the sidewall surface of the post 106. In some embodiments, the dielectric layer 111 ( Figure 1A Not shown in the image, but... Figure 1B (As shown in the figure) can be disposed between word line 110 and post 106. Word line 110 can be formed using a suitable conductive material, such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide and / or combinations thereof.

[0044] According to some embodiments, the drain cap 112 may be formed on the pillar 106. In some embodiments, the drain cap 112 may be formed of a semiconductor material doped with a suitable dopant (e.g., an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, lithium, and / or combinations thereof). In some embodiments, the dopant concentration of the n-type dopant may be approximately 1 × 10⁻⁶. 18 atoms / cm 3 Up to approximately 1×10 22 atoms / cm 3 Between. In some embodiments, the dopant concentration of the n-type dopant can be greater than about 1 × 10⁻⁶. 20 atoms / cm 3 In some embodiments, the drain cap 112 can be formed by doping the top portion of the pillar 106 with an n-type dopant.

[0045] According to some embodiments, bit line 114 is formed above drain cap 112 and electrically coupled to drain cap 112. In some embodiments, bit line 114 may be formed using a suitable conductive material, such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, and / or combinations thereof.

[0046] Enlarged Figure 120 shows the charge carrier concentration distribution within pillar 106 after a programming scheme is performed on memory cell 100. In some embodiments, the majority of charge carriers within pillar 106 are electron holes, i.e., electrons are absent in the atom. After the programming scheme is performed on memory cell 100, the resulting holes are unevenly distributed within pillar 106. A region 122 with a higher charge carrier concentration of holes is located in the upper region of pillar 106 and near word line 110. In some embodiments, the higher charge carrier concentration can be approximately 3 × 10⁻⁶. 15 cm -3 With approximately 3×10 18 cm -3 Between. In some embodiments, the charge carrier concentration may decrease toward the lower region of pillar 106, resulting in a lower charge carrier concentration region 124 of holes located in a portion of the pillar near the source line 104. In some embodiments, the lower charge carrier concentration may be approximately 1 × 10⁻⁶. 7 cm -3 With approximately 5×10 12 cm -3 In some embodiments, a lower charge carrier concentration region 124 can cause leakage current to flow between the pillar 106 and the source line 104, resulting in reduced data retention in the memory cell, which in turn reduces the device performance of the memory cell 100.

[0047] Figure 1B A top view of a memory array 150 formed of capacitor-less dual-gate vertical 1T memory cells according to some embodiments of the present disclosure is shown. The 1T memory cell can be... Figure 1A The memory unit 100 described herein. (and...) Figure 1A The corresponding elements are indicated by similar reference numerals. The memory array 150 may include additional memory cells, which are not shown for simplicity.

[0048] Multiple bit lines and word lines intersect to form a memory array 150. For example... Figure 1B As shown, multiple word lines 110 may extend in a first lateral direction (e.g., the x-direction) and are designated as WL0, WL1, and WL2, etc. Similarly, multiple bit lines 112 may extend in a second lateral direction (e.g., the y-direction) and are designated as BL0, BL1, and BL2, etc. Memory cells are formed at the intersections of word lines and bit lines. For example, memory cells 100 may be formed at the intersections of WL0 and BL0 and WL2 and BL0.

[0049] Figure 2 A cross-sectional view of a capacitor-free vertical 1T memory cell 200 with a bottom select gate (BSG) for reduced leakage current and improved data retention is shown. Figure 1AThe corresponding elements in the figure are indicated by similar reference numerals.

[0050] like Figure 2 As shown, a bottom gate, such as BSG 210, is formed between plate line 108 and source line 104. In some embodiments, pillar 106 may be formed of a pillar structure, and BSG 210 may be configured to surround the lower portion of the sidewall surface of pillar 106. In some embodiments, a dielectric layer may be disposed between BSG 210 and pillar 106. BSG 210 may be formed using a suitable conductive material, such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, and / or combinations thereof. By applying a rated voltage bias to BSG 210, a region with a higher charge carrier concentration can be formed in the lower portion of pillar 106, which in turn can reduce leakage current and improve data retention of memory cell 200. Enlarged Figure 220 shows the charge carrier concentration distribution within pillar 106 after a programming scheme is performed on memory cell 200. Similar to Figure 1A In the memory cell described herein, the majority of charge carriers within pillar 106 can be electrons and holes. After a programming scheme is performed on memory cell 200, the resulting holes are unevenly distributed within pillar 106. A region 122 with a higher charge carrier concentration of holes is located in the upper region of pillar 106 and near word line 110. Another region 222 with a higher charge carrier concentration of holes is located in the lower region of pillar 106 and near BSG 220. The higher charge carrier concentration region 222 can be a saturation region to prevent leakage current formation. In some embodiments, the charge carrier concentration of the higher charge carrier concentration region 222 can be approximately 3 × 10⁻⁶. 15 cm -3 With approximately 3×10 18 cm -3 between.

[0051] Figure 3 Methods for forming a capacitorless 1T memory cell with a BSG for reducing leakage current and improving data retention, according to some embodiments of this disclosure, are illustrated. The operation of method 300 may be performed in different orders and / or variations, and method 300 may include further operations not described for simplicity. Figures 4A-4G This is a cross-sectional view of an exemplary memory structure 400 incorporating a BSG structure. Figures 4A-4G The figures are provided as exemplary cross-sectional views to facilitate explanation of method 300. The manufacturing process provided herein is exemplary, and alternative processes according to this disclosure may be performed, not shown in these figures. Additional layers and / or structures may be formed in the memory structure 400, and for simplicity, the additional layers and / or structures are... Figures 4A-4G Not shown in the image.

[0052] According to some embodiments of this disclosure, a stepped structure is formed on the substrate at operation 302. (See reference...) Figure 4A The memory structure 400 may include: a substrate 102; conductive lines 401; dielectric layers 402, 404, 406, and 408; a BSG 210; board lines 108; word lines 110; a pad layer 410; insulating layers 411 and 414; and an etch stop layer 412. At least the BSG 210, board lines 108, and word lines 110 may be formed laterally offset relative to each other to form a stepped structure. Figure 1A and Figure 2 The corresponding elements in the figure are indicated by similar reference numerals.

[0053] Substrate 102 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compounds, any other suitable material, or any combination thereof. In some embodiments, substrate 102 may be a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0054] Conductive lines 401 may be formed on substrate 102. In some embodiments, conductive lines 401 may be conductive structures, such as metal lines or semiconductor layers doped with suitable dopants. For example, conductive lines 401 may be formed of tungsten, cobalt, copper, aluminum, any suitable metal, and / or combinations thereof. Conductive lines 401 may be formed using thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), and / or any combination thereof.

[0055] The stepped structure 403 may include at least BSG 210, board line 108, and word line 110. Each of the aforementioned layers may be formed with a lateral offset relative to each other, such that the lateral offset forms a stepped shape to allow electrical connections to each level of the layer. In some embodiments, the stepped structure 403 may further include dielectric layers 404, 406, and 408 respectively formed on BSG 210, board line 108, and word line 110.

[0056] The thicknesses of BSG 210, plate line 108, and word line 110 can affect the charge carrier concentration of the subsequently formed pillars extending through the stepped structure 403. In some embodiments, the thickness T1 of BSG 210 can be between about 15 nm and about 80 nm. In some embodiments, the thickness T2 of plate line 108 can be between about 60 nm and about 300 nm. In some embodiments, the thickness T3 of word line 110 can be between about 15 nm and about 80 nm. In some embodiments, the ratio of thickness T1 to thickness T2 can be about 1:4. In some embodiments, the ratio of thickness T2 to thickness T3 can be about 4:1.

[0057] The BSG 210, board line 108, and word line 110 can be formed using one or more conductive materials. For example, conductive materials may include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicides, and / or combinations thereof. The pad layer 410, insulating layers 411 and 414, etch stop layer 412, and dielectric layers 402, 404, 406, and 408 can be formed using one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, any suitable dielectric material, and / or combinations thereof.

[0058] The pad layer 410, insulating layers 411 and 414, etch stop layer 412, dielectric layers 402, 404, 406 and 408, and the stepped structure 403, such as BSG 210, board line 108, word line 110, and dielectric layers 402, 404, 406 and 408, can be formed using suitable deposition methods. For example, deposition methods can include CVD, PVD, PECVD, ALD, high-density plasma CVD (HDP-CVD, high-density-plasma chemical vapor deposition), sputtering, spin coating, or any combination thereof.

[0059] According to some embodiments of this disclosure, at operation 304, an opening can be formed through the stepped structure. (See reference...) Figure 4BAn opening 420 can be formed by etching portions of the insulating layer 414, the etch stop layer 412, and the stepped structure 403 until the conductive line 401 is exposed. In some embodiments, the opening 420 may be a cylindrical hole having a generally rectangular cross-sectional area. A photolithography process may be used to expose the portion of the top surface of the insulating layer 414 to be etched. A dry plasma etching process or a wet chemical etching process may be used to sequentially remove portions of the insulating layer 414, the etch stop layer 412, and the stepped structure 403 until the conductive line 401 is exposed. The etching process may include multiple etching processes, each configured to remove a type of material being exposed. Specifically, the etchant used in each etching process may be selected based on the material composition of the insulating layer 414, the etch stop layer 412, the dielectric layers 402, 404, 406, and 408, and the conductive material forming the BSG 210, the board line 108, and the word line 110. For example, the etching process may include a suitable etchant for removing SiO2, SiN, and conductive materials (e.g., tungsten). The etching process continues until the top surface of the conductive line 401 is exposed. In some embodiments, the opening 420 extends into the conductive line 401 to ensure that the conductive line 401 is exposed within the opening 420. After the opening 420 is formed, a mask layer such as a photoresist can be removed.

[0060] According to some embodiments of this disclosure, at operation 306, a gate dielectric layer can be formed in the opening. (See reference...) Figure 4C A gate dielectric layer 421 may be formed in the opening 420 and contact the gate structure including BSG 210, board line 108, and word line 110. In some embodiments, an etch-back process may be performed before forming the gate dielectric layer. For example, BSG 210, board line 108, and word line 110 may be etched back laterally, and the gate dielectric layer may be disposed on the etched-back gate. In some embodiments, the gate dielectric layer 421 may be formed by uniformly disposing a gate dielectric material on all exposed surfaces of the opening 420, followed by an anisotropic etching process such that the disposed gate dielectric material remains in contact with the gate structure and adjacent dielectric layers. For example, the gate dielectric layer 421 contacts BSG 210 and dielectric layers 402 and 404. Similarly, the gate dielectric layer 421 contacts board line 108 and dielectric layers 404 and 406. Furthermore, the gate dielectric layer 421 contacts word line 110 and dielectric layers 406 and 408. In some embodiments, the vertical sidewalls of the gate dielectric layer 421 are coplanar with the vertical sidewalls of the dielectric layers 404, 406 and 408.

[0061] According to some embodiments of this disclosure, at operation 308, the source line of the memory cell can be formed in the opening. (See reference...) Figure 4DA source line 430 is formed at the bottom of the opening 420 and contacts the conductive line 401 and the dielectric layer 402. In some embodiments, the source line 430 may be formed of silicon material and doped with an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, lithium, and / or combinations thereof. In some embodiments, the source line 430 may be monocrystalline silicon and formed using an epitaxial growth process that uses the conductive line 401 as a seed layer. In some embodiments, the source line 430 may be similar to... Figure 1A , Figure 1B and Figure 2 The source line 104 is described in the text.

[0062] According to some embodiments of this disclosure, at operation 308, a semiconductor material is disposed to fill the opening. (See reference...) Figure 4E Semiconductor material 440 may be formed in the opening 420 and contact the source line 430 and the gate dielectric layer 421. In some embodiments, semiconductor material 440 extends through the entire opening 420 and undergoes a planarization process such that the top surface of semiconductor material 440 is coplanar with the top surface of insulating layer 414. In some embodiments, semiconductor material 440 may be formed using silicon material, such as polycrystalline silicon or monocrystalline silicon. In some embodiments, semiconductor material 440 may be an intrinsic material or doped with suitable dopants, such as one or more p-type dopants. For example, semiconductor material 440 may be doped with p-type dopants, such as boron, aluminum, nitrogen, gallium, indium, and / or combinations thereof.

[0063] According to some embodiments of this disclosure, at operation 310, a drain cap and a floating body for the memory cell can be formed. (See reference...) Figure 4F It can be done by... Figure 4E The top portion of the semiconductor material 440 shown is doped to form a drain cap 460. The remaining portion of the semiconductor material 440 between its doped top portion and the source line 430 may form a pillar 450. In some embodiments, the dopant used in the ion implantation process for doping the top portion of the semiconductor material 440 may be the opposite type of dopant used in forming the semiconductor material 440. For example, Figure 4E The semiconductor material 440 described herein may be doped with a p-type dopant, while the drain cap 460 may be doped with an n-type dopant. In some embodiments, the pillar 450 is a pillar structure extending in a vertical direction (e.g., the z-direction), and the sidewalls of the pillar 450 are surrounded by the BSG 210, the plate line 108, and the word line 110. In some embodiments, such as Figure 4F As shown, the top surface of column 450 is located in a horizontal plane above the top surface of word line 110, and the bottom surface of column 450 is located in a horizontal plane below the bottom surface of BSG 210.

[0064] According to some embodiments of this disclosure, bit lines and interconnect structures of memory cells can be formed at operation 312. (See reference...) Figure 4G Via 462 may extend through etch stop layer 412 and insulating layers 411 and 414. In some embodiments, via 462 may also extend through pad layer 410. Via 462 may contact and be electrically coupled to conductive line 401, BSG 210, board line 108, and word line 110 for providing voltage bias and / or transmitting electrical signals to the gate structure. In some embodiments, additional etch stop layer 416 and insulating layer 418 may be disposed on insulating layer 414. The composition of etch stop layer 416 and insulating layer 418 may be similar to etch stop layer 412 and insulating layer 414, respectively, and will not be described in detail for simplicity. Bit line 472 may be formed in insulating layer 418 and electrically coupled to drain cap 460 through via 462. Similarly, word line contact 474 may be formed in insulating layer 418 and electrically coupled to word line 110 through via 462. In some embodiments, board line contact 476 may be formed in insulating layer 418 and electrically coupled to board line 108 via via 462. In some embodiments, BSG contact 478 may be formed in insulating layer 418 and electrically coupled to BSG 210 via via 462. In some embodiments, source line contact 480 may be formed in insulating layer 418 and electrically coupled to source line 430 via via 462 and conductive line 401.

[0065] Figure 5A A method 500 for operational programming a capacitorless 1T memory cell having a BSG for reducing leakage current and improving data retention, according to some embodiments of this disclosure, is illustrated. The operation of method 500 may be performed in different orders and / or variations, and method 500 may include further operations not described for simplicity. Figure 5B This is an operational diagram of programming a capacitorless 1T memory cell with a BSG incorporated, according to some embodiments. Figure 5B The voltage-time operation diagrams provided herein are exemplary to facilitate the explanation of method 500. The operations provided herein are exemplary, and alternative operations not shown in these diagrams according to this disclosure may be performed. Additional operations may be performed in method 500, and for simplicity, the additional operations are... Figure 5A and Figure 5B Not shown in the image.

[0066] Figure 5B A method for using a capacitorless 1T memory cell (e.g.) is shown. Figure 4G The operation diagram of the programming scheme for the memory structure 400 described in the document is shown in the reference. Figure 2The proposed method involves incorporating a BSG near the lower portion of the column to improve data retention and reduce leakage current.

[0067] According to some embodiments, at operation 502, a positive voltage bias is applied to the BSG of the memory cell and the board line. In some embodiments, the positive voltage bias applied to the board line may be between about 0.5V and about 0.9V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 0.8V can be applied to the board line 108 via board line contacts 476 and vias 462. In some embodiments, the positive voltage bias applied to the BSG can be between approximately 0.9V and approximately 1.1V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 1V can be applied to BSG 210 via BSG contact 478 and via 462. The positive voltage bias described herein is an example of a voltage bias applied to board line 108 and BSG 210. In some embodiments, any suitable positive bias can be used, such as a positive voltage bias between approximately 0.5V and approximately 2.0V. In some embodiments, the BSG and board line can be maintained under a positive voltage bias during the programming process. In some embodiments, the source line is connected to ground voltage during the programming process. In some embodiments, ground voltage can be connected to BSG 210 after the programming process is completed. In some embodiments, board line 108 is maintained under a positive voltage bias after the programming process is completed.

[0068] According to some embodiments, at operation 504, a positive voltage bias is applied to the word line of the memory cell. In some embodiments, the positive voltage bias is applied to the word line at a first time point T1. In some embodiments, the positive voltage bias applied to the word line may be between about 1.3V and about 1.7V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 1.5V can be applied to the word line 110 via word line contacts 474 and vias 462. In some embodiments, the word line reaches the applied positive voltage bias at a second time point T2.

[0069] According to some embodiments, at operation 506, a positive voltage bias is applied to the bit line of the memory cell. In some embodiments, the positive voltage bias is applied to the bit line at a third time point T3, occurring after the second time point T2. In some embodiments, the positive voltage bias applied to the bit line can be between about 0.6V and about 1V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 0.7V can be applied to bit line 472. In some embodiments, the bit line reaches the applied positive voltage bias at a fourth time point T4.

[0070] According to some embodiments, at operation 508, a ground voltage is applied to the word line of the memory cell. In some embodiments, the ground voltage is applied to the word line at a fifth time point T5, occurring after a fourth time point T4. Figure 4G Taking the memory structure 400 as an example, a ground voltage can be applied to the word line 110 through the word line contact 474 and the via 462. In some embodiments, the word line reaches the ground potential at a sixth time point T6.

[0071] According to some embodiments, at operation 510, a ground voltage is applied to the bit line of the memory cell. In some embodiments, the ground voltage is applied to the bit line at a seventh time point T7, which occurs after the sixth time point T6. Figure 4G Taking the memory structure 400 as an example, a ground voltage can be applied to bit line 472.

[0072] Figure 6A A method 600 for operational erasure of a capacitorless 1T memory cell having a BSG for reducing leakage current and retaining data, according to some embodiments of the present disclosure, is illustrated. The operation of method 600 may be performed in different orders and / or variations, and method 600 may include further operations not described for simplicity. Figure 6B This is an operation diagram of erasing a capacitorless 1T memory cell with a BSG incorporated, according to some embodiments. Figure 6B The voltage-time operation diagrams provided herein are exemplary to facilitate the explanation of method 600. The operations provided herein are exemplary, and alternative operations according to this disclosure may be performed, but not shown in these diagrams. Additional operations may be performed in method 600, and for simplicity, the additional operations are... Figure 6A and Figure 6B Not shown in the image.

[0073] Figure 6B An example of a capacitorless 1T memory cell (e.g., is shown) is illustrated. Figure 4G The operation diagram of the erase scheme for the memory structure 400 described in the document is shown. (See reference...) Figure 2 The proposed method involves incorporating a BSG near the lower portion of the column to improve data retention and reduce leakage current.

[0074] According to some embodiments, at operation 602, a positive voltage bias is applied to the BSG of the memory cell and the board line. In some embodiments, the positive voltage bias applied to the board line may be between about 0.5V and about 0.9V. Figure 4GTaking the memory structure 400 as an example, a positive voltage bias of approximately 0.8V can be applied to the board line 108 via board line contacts 476 and vias 462. In some embodiments, the positive voltage bias applied to the BSG can be between approximately 0.9V and approximately 1.1V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 1V can be applied to the BSG210 via the BSG contact 478 and via 462.

[0075] According to some embodiments, at operation 604, the positive voltage bias applied to the BSG is decreased, and the positive voltage bias applied to the board line is increased. In some embodiments, the decrease and increase of the voltage bias to the BSG and the board line are performed substantially simultaneously. For example, the change in voltage bias can occur substantially at a first time point T. 11 Occurs. In some embodiments, the BSG and board line occur at a second time point T. 12 This achieves their respective reduced and increased voltage biases. In some embodiments, the positive voltage bias to the BSG can be reduced to about 0.7V to about 0.9V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 0.8V can be applied to the BSG 210 via BSG contacts 478 and vias 462. In some embodiments, the positive voltage bias to the board lines can be increased to approximately 0.9V to approximately 1.1V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 1.0V can be applied to the board line 108 via the board line contact 476 and via 462. In some embodiments, the BSG and the board line can be at a second time point T. 12 Essentially, the adjusted positive voltage bias is achieved simultaneously.

[0076] According to some embodiments, at operation 606, a negative voltage bias is applied to the source line of the memory cell. In some embodiments, at the second time point T... 12 The third time point T that appears afterward 13 A negative voltage bias is applied to the source line. In some embodiments, the negative voltage bias applied to the source line can be between approximately -1.8V and approximately -2.2V. Figure 4G Taking the memory structure 400 as an example, a negative voltage bias of approximately -2.0V can be applied to the source line 430 through the source line contact 480, via 462, and conductive line 401. In some embodiments, the source line at a fourth time point T 14 The applied negative voltage bias is achieved.

[0077] According to some embodiments, at operation 608, the positive voltage bias applied to the BSG is increased, and the positive voltage bias applied to the board line is decreased. In some embodiments, the increase and decrease of the voltage bias to the BSG and the board line are performed substantially simultaneously. For example, the change in voltage bias can occur substantially at the fifth time point T. 15 Occurs. In some embodiments, the BSG and board line occur at the sixth time point T. 16 To achieve their respective increased and decreased voltage biases. In some embodiments, the positive voltage bias to the BSG can be increased from about 0.9V to about 1.1V. Figure 4G Taking the memory structure 400 as an example, a positive voltage bias of approximately 1.0V can be applied to the BSG 210 via BSG contacts 478 and vias 462. In some embodiments, the positive voltage bias to the board lines can be reduced to approximately 0.5V to approximately 0.9V. Figure 4G As an example, the memory structure 400 can apply a positive voltage bias of about 0.8V to the board line 108 through the board line contact 476 and via 462.

[0078] According to some embodiments, at operation 610, a ground voltage is applied to the source line of the memory cell. In some embodiments, at a sixth time point T... 16 The seventh time point T that appeared afterwards 17 Apply a ground voltage to the source line. Figure 4G Taking the memory structure 400 as an example, a ground voltage can be applied to the source line 430 through the source line contact 480, via 462 and conductive line 401.

[0079] Figure 7 A cross-sectional view of a capacitorless vertical 1T memory cell 700 is shown, which has a bias gate for improving the programming speed of the memory cell and providing the ability to selectively increase electron-hole pairs in the pillar. Figure 7 Zhongyu Figure 2 The corresponding elements in the figure are indicated by similar reference numerals.

[0080] like Figure 7As shown, memory cell 700 includes a bias gate, such as bias gate 710, formed between board line 108 and word line 110. In some embodiments, pillar 106 may be formed of a pillar structure, and bias gate 710 may be configured to surround a portion of the sidewall surface of pillar 106. In some embodiments, bias gate 710 may be disposed near the upper portion of pillar 106. In some embodiments, bias gate 710 may be disposed near the upper half of pillar 106. In some embodiments, a dielectric layer may be disposed between bias gate 710 and pillar 106. Suitable conductive materials may be used to form the bias gate, such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicides, and / or combinations thereof. By applying a rated voltage bias to bias gate 710, a region with a higher charge carrier concentration can be formed by impact ionization, thereby increasing the programming speed during programming. Additionally, bias gate 710 may also serve as a top select gate, which can generate additional electron-hole pairs through gate-induced drain leakage or impact ionization. Enlarged Figure 720 shows the charge carrier concentration distribution within pillar 106 after a programming scheme is performed on memory cell 700. Similar to... Figure 1A and Figure 2 In the memory cell described herein, the majority of charge carriers within pillar 106 can be electrons and holes, and a higher charge carrier concentration region 122 can be formed in the upper portion of pillar 106. Memory cell 700 can differ from memory cell 200, at least because an additional higher charge carrier concentration region 724 can be formed below the higher charge carrier concentration region 122 by applying a voltage bias to the bias gate 710, thereby improving programming speed. After a programming scheme is performed on memory cell 700, the resulting holes are unevenly distributed within pillar 106. The higher charge carrier concentration region 122 for holes is located in the upper region of pillar 106 and near word line 110. Another higher charge carrier concentration region 724 for holes can also be located in the upper region of pillar 106 and near bias gate 710. In some embodiments, the charge carrier concentration of the higher charge carrier concentration region 724 can be approximately 3 × 10⁻⁶. 15 cm -3 With approximately 3×10 18 cm -3 between.

[0081] Figure 8 This illustrates the integration of a 1T memory cell with or without a capacitor (e.g., Figure 7 The memory structure 800 is described in the memory cell 700. Figure 8 Zhongyu Figures 4A-4G The corresponding elements in the diagram are indicated by similar reference numerals. The memory structure 800 can use similar reference numerals. Figure 3 The method described in section 300 is used to form the memory structure. For example, the various manufacturing stages of the memory structure 800 can be similar to those described in section 300. Figures 4A-4G The manufacturing stages described herein will not be described here for the sake of simplicity.

[0082] The stepped structure 803 may include at least a board line 108, a bias gate 710, and a word line 110. Each of the aforementioned layers may be formed with a lateral offset relative to each other, such that the lateral offset forms a stepped shape to allow electrical connections to each level of the layer. In some embodiments, the stepped structure 803 may further include dielectric layers 404, 406, and 408 respectively formed on the board line 108, the bias gate 710, and the word line 110. Interconnect structures for electrical coupling to the bias gate 710 may include a bias gate contact 876 and a via 462. The material composition and formation process of the bias gate contact 876 may be similar to... Figure 4G The material composition and forming process of BSG contact 478 are described in the document, but will not be described in detail here for the sake of simplicity.

[0083] The bias gate 710 may be formed using a conductive material, such as tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, and / or combinations thereof. In some embodiments, the bias gate 710 may be formed using CVD, PVD, PECVD, ALD, HDP-CVD, sputtering, and / or any combination thereof.

[0084] The thicknesses of the bias gate 710, plate line 108, and word line 110 can affect the charge carrier concentration of the subsequently formed pillars extending through the stepped structure 403. In some embodiments, the thickness T4 of plate line 108 can be between about 60 nm and about 300 nm. In some embodiments, the thickness T5 of bias gate 710 can be between about 15 nm and about 80 nm. In some embodiments, the thickness T6 of word line 110 can be between about 15 nm and about 80 nm. In some embodiments, the ratio of thickness T4 to thickness T5 can be about 4:1. In some embodiments, the ratio of thickness T4 to thickness T6 can be about 4:1.

[0085] Figure 9A A method 900 for operating and programming a capacitorless 1T memory cell having biased gates for improving operating speed, such as programming speed, is illustrated according to some embodiments of the present disclosure. The operation of method 900 may be performed in different orders and / or variations, and method 900 may include further operations not described for simplicity. Figure 9B This is an operational diagram of programming a capacitorless 1T memory cell with a biased gate incorporated according to some embodiments. Figure 9BThe voltage-time operation diagrams provided herein are exemplary to facilitate the explanation of method 900. The operations provided herein are exemplary, and alternative operations not shown in these diagrams according to this disclosure may be performed. Additional operations may be performed in method 900, and for simplicity, the additional operations are... Figure 9A and Figure 9B Not shown in the image.

[0086] Figure 9B A method for using a capacitorless 1T memory cell (e.g.) is shown. Figure 8 The operation diagram of the programming scheme for the memory structure 800 described in the document is shown in the reference. Figure 7 and Figure 8 The proposed method involves incorporating a bias gate near the upper portion of the pillar to improve operating speed.

[0087] According to some embodiments, at operation 902, a positive voltage bias is applied to the bias gate and board line of the memory cell. In some embodiments, the positive voltage bias applied to the board line may be between about 0.5V and about 0.9V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 0.8V can be applied to the board line 108 via board line contacts 476 and vias 462. In some embodiments, the positive voltage bias applied to the bias gate can be between approximately 0.9V and approximately 1.1V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 1V can be applied to the bias gate 710 via the bias gate contact 876 and via 462. In some embodiments, the bias gate and board line may be maintained under a positive voltage bias during the programming process. In some embodiments, the source line is connected to ground during the programming process. The positive voltage bias described herein is an example of a voltage bias applied to the board line 108 and the bias gate 710. In some embodiments, any suitable positive bias can be used, such as a positive voltage bias between approximately 0.5V and approximately 2.0V. In some embodiments, the source line is connected to ground during the programming process. In some embodiments, the ground voltage can be connected to BSG 210 after the programming process is completed. In some embodiments, the board line 108 is maintained under a positive voltage bias after the programming process is completed.

[0088] According to some embodiments, at operation 904, a positive voltage bias is applied to the word line of the memory cell. In some embodiments, at a first time point T 91 A positive voltage bias is applied to the word line. In some embodiments, the positive voltage bias applied to the word line can be between approximately 1.3V and approximately 1.7V. Figure 8Taking the memory structure 800 as an example, a positive voltage bias of approximately 1.5V can be applied to the word line 110 via word line contacts 474 and vias 462. In some embodiments, the word line at a second time point T 92 The applied positive voltage bias is achieved.

[0089] According to some embodiments, at operation 906, a positive voltage bias is applied to the bit line of the memory cell. In some embodiments, at the second time point T 92 The third time point T that appears afterward 93 A positive voltage bias is applied to the bit line. In some embodiments, the positive voltage bias applied to the bit line can be between about 0.6V and about 1V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 0.7V can be applied to bit line 472. In some embodiments, the bit line at a fourth time point T 94 The applied positive voltage bias is achieved.

[0090] According to some embodiments, at operation 908, a ground voltage is applied to the word line of the memory cell. In some embodiments, at a fourth time point T... 94 The fifth time point T that appears later 95 Apply ground voltage to the word line. Use Figure 8 Taking the memory structure 800 as an example, a ground voltage can be applied to the word line 110 through the word line contact 474 and via 462. In some embodiments, the word line at a sixth time point T 96 Reaching ground potential.

[0091] According to some embodiments, at operation 910, a ground voltage is applied to the bit line of the memory cell. In some embodiments, at a sixth time point T... 96 The seventh time point T that appeared afterwards 97 Apply ground voltage to the line. Use Figure 8 Taking the memory structure 800 as an example, a ground voltage can be applied to bit line 472.

[0092] Figure 10A A method 1000 for operating an erase scheme for a capacitorless 1T memory cell having a bias gate for improved operating speed, according to some embodiments of the present disclosure, is illustrated. The operation of method 1000 may be performed in different orders and / or variations, and method 1000 may include further operations not described for simplicity. Figure 10B This is an operation diagram of erasing a capacitorless 1T memory cell with a biased gate incorporated in some embodiments. Figure 10BThe voltage-time operation diagrams provided herein are exemplary to facilitate the explanation of method 1000. The operations provided herein are exemplary, and alternative operations not shown in these diagrams according to this disclosure may be performed. Additional operations may be performed in method 1000, and for simplicity, the additional operations are... Figure 10A and Figure 10B Not shown in the image.

[0093] Figure 10B This illustrates a capacitorless 1T memory cell (e.g., Figure 8 The operation diagram of the erase scheme for the memory structure 800 described in the document is shown below. (See reference...) Figure 7 and Figure 8 The proposed method involves incorporating a bias gate near the upper portion of the pillar to improve operating speed.

[0094] According to some embodiments, at operation 1002, a positive voltage bias is applied to the bias gate and board line of the memory cell. In some embodiments, the positive voltage bias applied to the board line may be between about 0.5V and about 0.9V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 0.8V can be applied to the board line 108 via board line contacts 476 and vias 462. In some embodiments, the positive voltage bias applied to the bias gate can be between approximately 0.9V and approximately 1.1V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of about 1V can be applied to the bias gate 710 through the bias gate contact 876 and the via 462.

[0095] According to some embodiments, at operation 1004, the positive voltage bias applied to the bias gate is decreased, and the positive voltage bias applied to the board line is increased. In some embodiments, the decrease and increase of the voltage bias to the bias gate and the board line are performed substantially simultaneously. For example, the change in voltage bias can occur substantially at a first time point T. 101 This occurs. In some embodiments, the bias gate and board line occur at a second time point T. 102 This achieves their respective reduced and increased voltage biases. In some embodiments, the positive voltage bias to the bias gate can be reduced to about 0.7V to about 0.9V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 0.8V can be applied to the bias gate 710 via the bias gate contact 876 and the via 462. In some embodiments, the positive voltage bias to the board line can be increased to approximately 0.9V to approximately 1.1V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 1.0V can be applied to the board line 108 via the board line contact 476 and via 462. In some embodiments, the bias gate and the board line can be at a second time point T.102 Essentially, the adjusted positive voltage bias is achieved simultaneously.

[0096] According to some embodiments, at operation 1006, a negative voltage bias is applied to the source line of the memory cell. In some embodiments, at the second time point T... 102 The third time point T that appears afterward 103 A negative voltage bias is applied to the source line. In some embodiments, the negative voltage bias applied to the source line can be between approximately -1.8V and approximately -2.2V. Figure 8 Taking the memory structure 800 as an example, a negative voltage bias of approximately -2.0V can be applied to the source line 430 through the source line contact 480, via 462, and conductive line 401. In some embodiments, the source line at a fourth time point T 104 The applied negative voltage bias is achieved.

[0097] According to some embodiments, at operation 1008, the positive voltage bias applied to the bias gate is increased, and the positive voltage bias applied to the board line is decreased. In some embodiments, the increase and decrease of the voltage bias to the bias gate and the board line are performed substantially simultaneously. For example, the change in voltage bias may occur substantially at the fifth time point T. 105 This occurs. In some embodiments, the bias gate and board line occur at a sixth time point T. 106 This achieves their respective increased and decreased voltage biases. In some embodiments, the positive voltage bias to the bias gate can be increased from about 0.9V to about 1.1V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 1.0V can be applied to the bias gate 710 via the bias gate contact 876 and the via 462. In some embodiments, the positive voltage bias to the board line can be reduced to approximately 0.5V to approximately 0.9V. Figure 8 Taking the memory structure 800 as an example, a positive voltage bias of approximately 0.8V can be applied to the board line 108 via the board line contact 476 and via 462.

[0098] According to some embodiments, at operation 1010, a ground voltage is applied to the source line of the memory cell. In some embodiments, at the sixth time point T... 106 The seventh time point T that appeared afterwards 107 Apply a ground voltage to the source line. Figure 8 Taking the memory structure 800 as an example, a ground voltage can be applied to the source line 430 through the source line contact 480, via 462 and conductive line 401.

[0099] Various embodiments of this disclosure provide structures and methods of fabricating capacitor-free multi-gate vertical 1T memory structures that improve data retention and reduce leakage current. The capacitor-free multi-gate vertical 1T memory structure may include pillars in the shape of vertical pillars surrounded by a plurality of gates. In some embodiments, the pillar may be surrounded by a top select gate, a board line gate, and a bottom select gate. In some embodiments, the pillar may be surrounded by a word line gate, a bias gate, and a board line gate. Bit lines may be formed above the pillars. Memory cells are formed at the intersections between word lines and bit lines. The capacitor-free multi-gate vertical 1T memory structure of this disclosure can provide various benefits, including, but not limited to, improved transistor carrier density, improved programming / erasing speed, etc.

[0100] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt these specific embodiments for various applications by applying knowledge of the art without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the disclosure and guidance.

[0101] Embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined provided the specified functions and their relationships are properly performed.

[0102] The summary and abstract section may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0103] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for performing programming operations on a memory device, wherein, The memory device includes: a bottom select gate; a board line above the bottom select gate; a word line above the board line; a pillar extending through the bottom select gate, the board line, and the word line; a source line below the pillar; and a bit line formed above the pillar. The method includes: A first positive voltage bias is applied to the bottom selection gate; A second positive voltage bias is applied to the word line; After the word line reaches the second positive voltage bias, a third positive voltage bias is applied to the bit line; Apply a ground voltage to the word line; and The ground voltage is applied to the bit line.

2. The method according to claim 1, wherein, Applying the ground voltage includes applying it to the word line after the bit line reaches the third positive voltage bias.

3. The method according to claim 1, wherein, Applying the ground voltage to the bit line includes performing the application after the word line reaches the ground voltage.

4. The method of claim 1, further comprising applying a fourth positive voltage bias to the board line.

5. The method according to claim 1, wherein, Applying the first positive voltage bias includes applying a voltage between approximately 0.9V and approximately 1.1V to the bottom select gate.

6. A method for performing an erase operation on a memory device, wherein, The memory device includes: a bottom select gate; a board line above the bottom select gate; a word line above the board line; a pillar extending through the bottom select gate, the board line, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method includes: A first positive voltage bias is applied to the bottom selection gate; A second positive voltage bias is applied to the board line; Reduce the first positive voltage bias to the bottom select gate; and A negative voltage bias is applied to the source line.

7. The method according to claim 6, wherein, After the bottom selected gate reaches a reduced first positive voltage bias, the negative voltage bias is applied to the source line.

8. The method of claim 6, further comprising increasing the second positive voltage bias to the board line.

9. The method of claim 6, further comprising increasing the first positive voltage bias to the bottom select gate.

10. The method of claim 6, further comprising reducing the second positive voltage bias to the board line.

11. A method for performing programming operations on a memory device, wherein, The memory device includes: a board line; a bias gate above the board line; a word line above the board line; a pillar extending through the board line, the bias gate, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method includes: A first positive voltage bias is applied to the bias gate; A second positive voltage bias is applied to the word line; After the word line reaches the second positive voltage bias, a third positive voltage bias is applied to the bit line; Apply a ground voltage to the word line; and The ground voltage is applied to the bit line.

12. The method according to claim 11, wherein, After the bit line reaches the third positive voltage bias, the ground voltage is applied to the word line.

13. The method according to claim 11, wherein, The ground voltage is applied to the bit line after the word line reaches the ground voltage.

14. The method of claim 11, further comprising applying a fourth positive voltage bias to the board line.

15. The method according to claim 11, wherein, Applying the first positive voltage bias includes applying a voltage between approximately 0.9V and approximately 1.1V to the bias gate.

16. A method for performing an erase operation on a memory device, wherein, The memory device includes: a board line; a bias gate above the board line; a word line above the board line; a pillar extending through the board line, the bias gate, and the word line; a source line below the pillar; a drain cap above the pillar; and a bit line formed above the drain cap. The method includes: A first positive voltage bias is applied to the bias gate; A second positive voltage bias is applied to the board line; Reduced to the first positive voltage bias of the bias gate; and A negative voltage bias is applied to the source line.

17. The method according to claim 16, wherein, After the bias gate reaches a reduced first positive voltage bias, the negative voltage bias is applied to the source line.

18. The method of claim 16, further comprising increasing the second positive voltage bias to the board line.

19. The method of claim 16, further comprising increasing the first positive voltage bias to the bias gate.

20. The method of claim 16, further comprising reducing the second positive voltage bias to the board line.

Images