Microelectronic devices having support posts spaced apart along a slit between an array of columns, and related methods and systems

Abstract

This application relates to a microelectronic device having support pillars separated by slit regions between pillar array blocks, and to related methods and systems. A microelectronic device includes a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one slit region divides the stacked structure into blocks. Each block includes an active pillar array. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stacked structure. Additional microelectronic devices, and related methods and electronic systems, are also disclosed.

Description

[0001] Priority requirements

[0002] This application is a national phase entry of International Patent Application PCT / US2021 / 053326, filed on October 4, 2021, designating the People's Republic of China, and published in English as International Patent Publication WO 2022 / 076287A1 on April 14, 2022, which claims the benefit of U.S. Patent Application No. 17 / 063,101, filed on October 5, 2020, entitled "Microelectronic Devices with Support Pillars Spaced Along a Slit Regiion Between Pillar Array Blocks, and Related Methods and Systems," entitled "Microelectronic Devices with Support Pillars Spaced Along a Slit Regiment Between Pillar Array Blocks, and Related Methods and Systems," filed pursuant to Article VIII of the Patent Cooperation Treaty. Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods, related systems, and methods for forming microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having a layered stacked structure comprising vertically alternating conductive and insulating structures. Background Technology

[0004] Memory devices provide data storage for electronic systems. Flash memory devices are one type of memory device and are widely used in modern computers and other electrical devices. A conventional flash memory device may comprise a memory array having a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In the NAND architecture type of flash memory, the memory cells arranged in columns are coupled in series, and the first memory cell of the column is coupled to a data line (e.g., a bit line).

[0005] In a “three-dimensional NAND” memory device (which may also be referred to herein as a “3D NAND” memory device), the type of vertical memory device is not merely memory cells arranged in rows and columns in a horizontal array, but rather a series of horizontal arrays stacked on top of each other (e.g., as vertical strings of memory cells) to provide a “three-dimensional array” of memory cells. The stacked layers are vertically alternating between insulating (e.g., dielectric) and conductive materials. The conductive materials act as control gates for the access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars including channel and tunnel structures) extend along the vertical string of memory cells. The drain end of the string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while the source end of the string is adjacent to the other of the top and bottom of the pillar. The drain end is operatively connected to a bit line, while the source end is operatively connected to a source line. A 3D NAND memory device also includes electrical connections, such as access lines (e.g., word lines), to other conductive structures of the device, such that the memory cells of the vertical string can be selected for write, read, and erase operations.

[0006] Fabricating 3D NAND memory devices often presents challenges. For example, varying residual stresses can cause some features to bend away from the intended true vertical direction. As another example, fabricating features can create voids or seams that can become points of structural failure during subsequent processing, disposal, or use. Therefore, reliably manufacturing features for microelectronic devices such as 3D NAND memory devices is challenging. Summary of the Invention

[0007] A microelectronic device is disclosed. The microelectronic device includes a stacked structure. The stacked structure includes a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one slit region divides the stacked structure into blocks. Each block includes an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. Each slit structure segment and each support pillar structure extends vertically through the stacked structure.

[0008] A microelectronic device comprising a column array block is also disclosed. The column array of the block includes columns extending vertically through a stacked structure. The stacked structure includes conductive structures that alternate vertically with insulating structures. The columns include at least one channel material. Along a region separating adjacent blocks in the column array block, a series of support columns extend vertically through the stacked structure in the region separating adjacent blocks. Each of the series of support columns is horizontally inserted between a pair of slit structures in the series of slit structures.

[0009] Furthermore, a method for forming a microelectronic device is disclosed. The method includes forming a stacked structure comprising a vertically alternating sequence of insulating structures and other structures arranged in layers. An array of pillar openings is formed, the pillar openings extending through the stacked structure. A series of support pillar openings are formed in regions between the pillar opening arrays. The support pillar openings extend through the stack. The support pillar openings are substantially filled with additional insulating material to form an intermediate support pillar structure. Pillars are formed in the pillar opening array to form a pillar array. The pillars include at least one channel material. Adjacent arrays in the pillar array are separated by the regions. A series of slits are formed in the regions between adjacent arrays. Each slit is horizontally inserted between a pair of support pillar structures formed by the intermediate support pillar structure. The series of slits is filled with a non-conductive material to form a series of slit structure segments that horizontally alternate with the support pillar structures.

[0010] An electronic system is also disclosed, comprising an input device, an output device, a processor device, and a memory device. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes a column array block laterally separated from each other by regions. The regions include a series of insulating support columns longitudinally alternating with a series of slit structures. The column array block includes columns extending vertically through a stacked structure. The stacked structure includes conductive structures vertically intersecting with the insulating structures. The columns include at least one channel material. The insulating support columns and the slit structures each extend vertically through the stacked structure in the regions separating the column array blocks. Attached Figure Description

[0011] For diagrams that are not numbered using accompanying letters Figures 1 to 10 It is according to embodiments of this disclosure in the manufacture of microelectronic device structures (e.g.) Figure 10 Top views and schematic diagrams of the various processing stages of the microelectronic device structure, wherein:

[0012] Figure 1A It is along Figure 1 A schematic frontal view of the cross section taken by section line A; Figure 1B It is along Figure 1 A schematic frontal view of the cross-section taken by section line B; and Figure 1C It is along Figure 1 A schematic frontal view of the cross section taken by section line C;

[0013] Figure 2A It is along Figure 2 A schematic frontal view of the cross section taken by section line A. Figure 2B It is along Figure 2A schematic frontal view of the cross-section taken by section line B; and Figure 2C It is along Figure 2 A schematic frontal view of the cross section taken by section line C;

[0014] Figure 3A It is along Figure 3 A schematic frontal view of the cross section taken by section line A. Figure 3B It is along Figure 3 A schematic frontal view of the cross-section taken by section line B; and Figure 3C It is along Figure 3 A schematic frontal view of the cross section taken by section line C;

[0015] Figure 4A It is along Figure 4 A schematic frontal view of the cross section taken by section line A. Figure 4B It is along Figure 4 A schematic frontal view of the cross-section taken by section line B; and Figure 4C It is along Figure 4 A schematic frontal view of the cross section taken by section line C;

[0016] Figure 5A It is along Figure 5 A schematic frontal view of the cross section taken by section line A. Figure 5B It is along Figure 5 A schematic frontal view of the cross-section taken by section line B; and Figure 5C It is along Figure 5 A schematic frontal view of the cross section taken by section line C;

[0017] Figure 6A It is along Figure 6 A schematic frontal view of the cross section taken by section line A. Figure 6B It is along Figure 6 A schematic frontal view of the cross-section taken by section line B; and Figure 6C It is along Figure 6 A schematic frontal view of the cross section taken by section line C;

[0018] Figure 7A It is along Figure 7 A schematic frontal view of the cross section taken by section line A. Figure 7B It is along Figure 7 A schematic frontal view of the cross section taken by section line B; Figure 7C It is along Figure 7 A schematic frontal view of the cross-section taken by section line C; and Figure 7D It is along Figure 7 A schematic frontal view of the cross section taken by section line D;

[0019] Figure 8A It is along Figure 8 A schematic frontal view of the cross section taken by section line A. Figure 8B It is along Figure 8 A schematic frontal view of the cross section taken by section line B; Figure 8C It is along Figure 8 A schematic frontal view of the cross-section taken by section line C; and Figure 8D It is along Figure 8 A schematic frontal view of the cross section taken by section line D;

[0020] Figure 9A It is along Figure 9 A schematic frontal view of the cross section taken by section line A. Figure 9B It is along Figure 9 A schematic frontal view of the cross section taken by section line B; Figure 9C It is along Figure 9 A schematic frontal view of the cross-section taken by section line C; and Figure 9D It is along Figure 9 A schematic frontal view of the cross-section taken by section line D, and

[0021] Figure 10A It is along Figure 10 A schematic frontal view of the cross section taken by section line A. Figure 10B It is along Figure 10 A schematic frontal view of the cross section taken by section line B; Figure 10C It is along Figure 10 A schematic frontal view of the cross-section taken by section line C; and Figure 10D It is along Figure 10 A schematic frontal view of the cross section taken by section line D.

[0022] Figure 11 These are top views and schematic illustrations of a microelectronic device structure according to embodiments of the present disclosure, and the microelectronic device structure can be... Figures 1 to 9 The various stages shown are formed, in which Figure 11 Further statement Figure 9 The processing stage following the processing stage, in which Figure 11A It is along Figure 11 A schematic frontal view of the cross section taken by section line A. Figure 11B It is along Figure 11 A schematic frontal view of the cross section taken by section line B; Figure 11C It is along Figure 11 A schematic frontal view of the cross-section taken by section line C; and Figure 11D It is along Figure 11 A schematic frontal view of the cross section taken by section line D.

[0023] For diagrams that are not numbered using accompanying letters Figures 12 to 14 It is according to embodiments of this disclosure in the manufacture of microelectronic device structures (e.g.) Figure 14 Top views and schematic diagrams of the various processing stages of a microelectronic device structure. Figure 12 The stage at Figure 1 After the stage, among which:

[0024] Figure 12A It is along Figure 12 A schematic frontal view of the cross section taken by section line A. Figure 12B It is along Figure 12 A schematic frontal view of the cross-section taken by section line B; and Figure 12C It is along Figure 12 A schematic frontal view of the cross section taken by section line C;

[0025] Figure 13A It is along Figure 13 A schematic frontal view of the cross section taken by section line A. Figure 13B It is along Figure 13 A schematic frontal view of the cross-section taken by section line B; and Figure 13C It is along Figure 13 A schematic frontal view of the cross-section taken by section line C; and

[0026] Figure 14A It is along Figure 14 A schematic frontal view of the cross section taken by section line A. Figure 14B It is along Figure 14 A schematic frontal view of the cross-section taken by section line B; and Figure 14C It is along Figure 14 A schematic frontal view of the cross section taken by section line C.

[0027] Figure 15A , Figure 15B , Figure 15C and Figure 15D This is a schematic cross-sectional front view of a memory cell according to an embodiment of the present disclosure, where the areas shown correspond to, for example... Figure 10 , Figure 11 and / or Figure 14 The dashed box section.

[0028] Figure 16 This is a partial cross-sectional perspective schematic illustration of a microelectronic device according to an embodiment of the present disclosure.

[0029] Figure 17 This is a block diagram of an electronic system according to an embodiment of the present disclosure.

[0030] Figure 18 This is a block diagram of a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0031] Structures (e.g., microelectronic device structures), devices (e.g., microelectronic devices), and systems (e.g., electronic systems) according to embodiments of this disclosure comprise stacks of vertically alternating conductive and insulating structures arranged in layers, with pillars extending vertically through the stack. Slit structures separate the pillar array blocks from each other. The gaps between the slit structures are support pillars of insulating material. The support pillars interrupt what would otherwise be a continuous, elongated slit structure, which can provide structural weakness lines that are susceptible to material failure (e.g., physical cracking) during subsequent handling, disposal, or use. Support pillars spaced apart from the slit structures also provide reinforced structural support throughout the height of the support pillars and the stack. This reinforced structural support prevents adjacent blocks in the pillar array from bending toward or away from each other. Thus, the microelectronic device structure can be configured to have enhanced structural integrity, such as fewer blocks bending and less likelihood of cracks forming between blocks.

[0032] As used herein, the terms “opening,” “groove,” “slit,” “recess,” “void,” and “joint” mean and include a volume extending through at least one structure or at least one material, leaving a gap in said at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between structures or materials. Unless otherwise described, an “opening,” “groove,” “slit,” and / or “recess” does not necessarily empty material. That is, an “opening,” “groove,” “slit,” or “recess” does not necessarily have to be a void space. An “opening,” “groove,” “slit,” or “recess” formed in or between structures or materials may include structures or materials other than those in which the opening is formed. Furthermore, one or more structures or materials “exposed” within an opening, groove, slit, or recess may not necessarily be in contact with the atmosphere or a non-solid environment. A structure or material “exposed” within an opening, groove, slit, or recess may be adjacent to or in contact with other structures or materials disposed within the opening, groove, slit, or recess. Conversely, unless otherwise stated, "voids" and / or "joints" may substantially or completely empty material. "Voids" or "joints" formed in or between structures or materials may exclude structures or materials other than those in which the "voids" or "joints" are formed. Furthermore, structures or materials "exposed" within "voids" or "joints" may be in contact with atmospheric pressure or a non-solid environment.

[0033] As used herein, the terms “groove,” “slit,” and “joint” mean and include an elongated opening, while the terms “opening” and “void” may include any one or both of an elongated opening or elongated void and / or a non-elongated opening or non-elongated void.

[0034] As used herein, the terms “substrate” and “substrate structure” mean and include the substrate material or other construction on which components, such as those within a memory cell, are formed. A substrate or substrate structure can be a semiconductor substrate, a substrate semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. A substrate can be a conventional silicon substrate or other bulk substrate containing a semiconductor material. As used herein, the term “bulk substrate” means and includes not only silicon wafers but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) or silicon-on-glass (“SOG”) substrates, silicon epitaxial layers on a substrate semiconductor basis, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si-G) substrates. 1-x Ge x , where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referring to “substrate” or “substrate structure” in the following description, prior process stages may have been used to form materials, structures, or junctions in the substrate semiconductor structure, substrate structure, or other basis.

[0035] As used herein, the term "insulating" as used in reference to materials or structures means and includes electrically insulating materials or structures. An "insulating" material or structure may be formed of one or more of the following and includes one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2) x C z N y )) and / or air. This document contains one or more of the chemical formulas (e.g., SiO2) selected from "x", "y" and / or "z". x AlO x HfO x NbO x TiOx SiN y SiO x N y SiO x C z N y A chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and / or "z" atoms of an additional element (if present), respectively, relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating materials or insulating structures may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and violates the law of definite proportions. Furthermore, "insulating structure" means and includes structures formed from and containing insulating materials.

[0036] As used herein, the term “sacrifice” as used with reference to materials or structures means and includes materials or structures that are formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0037] As used herein, the term "horizontal" means and includes a direction parallel to the principal surface of the substrate on which the mentioned material or structure is situated. The width and length of the corresponding material or structure can be defined as dimensions in the horizontal plane. Referring to the diagrams, the "horizontal" direction may be perpendicular to the indicated "Z" axis, parallel to the indicated "X" axis, and parallel to the indicated "Y" axis.

[0038] As used herein, the term "lateral" means and includes a direction in a horizontal plane parallel to the principal surface of the substrate on which the mentioned material or structure lies, and generally perpendicular to the "longitude" direction. The width of the corresponding material or structure can be defined as a dimension in the lateral direction of the horizontal plane. Referring to the diagram, the "lateral" direction may be parallel to the indicated "X" axis, perpendicular to the indicated "Y" axis, and perpendicular to the indicated "Z" axis.

[0039] As used herein, the term "longitude" means and encompasses a direction in a horizontal plane parallel to the principal surface of the substrate on which the mentioned material or structure lies, and generally perpendicular to the "lateral" direction. The length of the corresponding material or structure can be defined as a dimension in the longitudinal direction of the horizontal plane. Referring to the diagram, the "longitude" direction may be parallel to the indicated "Y" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Z" axis.

[0040] As used herein, the term "vertical" means and includes a direction perpendicular to the principal surface of the substrate on which the mentioned material or structure rests. The height of the corresponding material or structure can be defined as a dimension in the vertical plane. Referring to the diagrams, the "vertical" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Y" axis.

[0041] As used herein, the term “width” means and includes a dimension that defines the maximum distance along the “X” axis indicated by a horizontal plane (e.g., in a front view, if indicated), along such an “X” axis in the horizontal plane of the material or structure in question. For example, the “width” of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer “X” axis diameter of a hollow or filled cylindrical structure.

[0042] As used herein, the term "length" means and includes the dimension along the "X" axis indicated by a horizontal plane (e.g., in a front view, if labeled), which defines the maximum distance of the material or structure in question along such an "X" axis in the horizontal plane. For example, the "length" of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer "Y" axis diameter of a hollow or filled cylindrical structure.

[0043] As used herein, the terms “thickness” or “thinness” mean and encompass a dimension in a straight line perpendicular to the nearest surface of an adjacent material or structure that is of a different composition or otherwise distinguishable from materials or structures whose thickness, thinness, or height is discussed.

[0044] As used herein, the term "between" is a spatial relative term used to describe the relative position of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" may encompass both an arrangement in which a material, structure, or substructure is immediately adjacent to another material, structure, or substructure, and an arrangement in which a material, structure, or substructure is indirectly adjacent to another material, structure, or substructure.

[0045] As used herein, the term “proximity” is a spatially relative term used to describe the placement of one material, structure, or substructure in proximity to another material, structure, or substructure. The term “closeness” includes placement that is indirectly adjacent to, immediately adjacent to, or internal to another.

[0046] As used herein, the term "adjacent" when referring to a material or structure means and refers to the immediately adjacent, closest material or structure of the identified component or characteristic. Materials or structures of other components or characteristics besides the identified component or characteristic may be situated between a material or structure of the identified component or characteristic and its "adjacent" material or structure. For example, a structure of material X "adjacent" to a structure of material Y is, for example, a first material X structure of a plurality of material X structures, whose second closest structure to material Y. "Adjacent" materials or structures may be directly or indirectly adjacent to the structure or material of the identified component or characteristic.

[0047] As used herein, the term "consistent"—when referring to the parameters, properties, or conditions of a structure, material, feature, or part thereof compared with those of another such structure, material, feature, or part thereof—means and includes two such structures, materials, features, or parts that are at least equal, substantially equal, or approximately equal in terms of their respective placement. For example, two structures having "consistent" thicknesses may each be defined at the same, substantially the same, or approximately the same thickness as the feature at a vertical distance X. As another example, a structure having "consistent" widths may have two parts each defined at the same, substantially the same, or approximately the same width at elevation Y1 and at elevation Y2 of such structures.

[0048] As used herein, the terms “about” and “approximately” include the numerical value when used with reference to a particular parameter, and those skilled in the art will understand that the deviation from the numerical value is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” with respect to a numerical value may include additional values ​​in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0049] As used herein, when referring to a parameter, property, or condition, the term "substantially" means and includes a parameter, property, or condition equal to or within the extent of deviation from a given value, such that a person skilled in the art would understand that such a given value is acceptable to satisfy, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, a parameter, property, or condition may be a "substantially" given value when the value is satisfied at least 90.0%, at least 95.0%, at least 99.0%, or actually satisfied at least 99.9%.

[0050] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent, longitudinally adjacent, vertically adjacent) another element, at the bottom of another element, or in direct contact with another element. It also includes that the element is indirectly on top of, adjacent to (e.g., laterally adjacent, longitudinally adjacent, vertically adjacent) another element, at the bottom of another element, or near another element, wherein other elements are present therein. In contrast, when an element is referred to as "directly on" or "immediately adjacent to" another element, no intermediate element is present.

[0051] As used herein, for ease of description, spatial relative terms such as “below,” “lower,” “bottom,” “above,” “upper,” “top,” and similar terms may be used to describe the relationship of one element or feature to another(s) element(s) illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figure is inverted, then an element described as “below,” “under,” or “on the bottom” of other elements or features would be oriented “above” or “on the top” of those other elements or features. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (rotated ninety degrees, inverted, etc.), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0052] As used herein, the terms “level” and “height” are spatially relative terms used to describe the relationship between one material or feature and another material or feature illustrated in a diagram, using – as a reference point – the principal surface of the substrate or base structure on which the reference material or structure rests. As used herein, “level” and “height” are each defined freely by a horizontal plane parallel to the principal surface. “Lower level” and “lower height” are closer to the principal surface of the substrate, while “upper level” and “upper height” are further away from the principal surface. Unless otherwise specified, spatially relative terms are intended to cover different orientations of the material, other than those depicted in the diagram. For example, the material in the diagram may be inverted, rotated, etc., where the spatially relative “height” descriptor remains unchanged because the referenced principal surface will similarly be reoriented.

[0053] As used herein, the terms “comprising,” “including,” “having,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional unlisted elements or method steps, but also include the more restrictive terms “consisting of” and “substantially consisting of” and their grammatical equivalents. Thus, a structure described as “comprising,” “including,” and / or “having” materials may be a structure that also includes additional materials in some embodiments and / or does not include any other materials in some embodiments. Similarly, a composition described as “comprising,” “including,” and / or “having” species (e.g., a gas) may be a composition that also includes additional species in some embodiments and / or does not include any other species in some embodiments.

[0054] As used herein, the term “may” in relation to a material, structure, feature, or method action indicates that the material, structure, feature, or method action is intended for implementation of embodiments of this disclosure, and this term is preferred over the more restrictive term “yes” in order to avoid any implication that other compatible materials, structures, features, and methods that should or must be excluded from use in combination with it.

[0055] As used herein, “and / or” means and includes any and all combinations of one or more of the associated listed items.

[0056] As used herein, unless the context explicitly indicates otherwise, the singular forms “a”, “an” and “the” are also intended to include the plural forms.

[0057] As used herein, unless the context clearly indicates otherwise, the “(s)” at the end of a term means and includes the singular and / or plural forms of the term.

[0058] As used herein, the term “configured / configuration” means and refers to the size, shape, material composition, orientation, and arrangement of the mentioned material, structure, component, or equipment in a predetermined manner to facilitate the mentioned operation or characteristics of the mentioned material, structure, component, or equipment.

[0059] The illustrations presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but are merely idealized representations used to describe embodiments of this disclosure.

[0060] Embodiments are described herein with reference to cross-sectional views as schematic illustrations. Therefore, the shapes to be illustrated may vary due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes or structures shown, but may include shape deviations, for example, due to manufacturing techniques. For example, structures shown or described as frame-shaped may have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the materials, features, and structures shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the materials, features, or structures and do not limit the scope of the claims of this invention.

[0061] The following description provides specific details, such as material types and processing conditions, to provide an exhaustive description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without these specific details. In fact, embodiments of the apparatus and methods can be practiced in conjunction with conventional semiconductor manufacturing techniques used in the industry.

[0062] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary for understanding embodiments of the equipment (e.g., apparatus, system) and methods of the present invention are described herein.

[0063] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by those skilled in the art.

[0064] Unless the context otherwise indicates, the removal of the material described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization, or other known methods.

[0065] In the reference drawings, the same labels always refer to the same parts. The drawings are not necessarily drawn to scale.

[0066] Figures 1 to 10 (Including its "A", "B", "C" and / or "D" views) illustrates the various stages of a method for forming a microelectronic device structure with supporting pillars in slits between pillar array blocks. Common Reference Figure 1 , Figure 1A (It is along) Figure 1 (The front view of the cross section taken by section line A) Figure 1B (It is along) Figure 1 (The front view of the cross section taken by section line B) and Figure 1C (that is) Figure 1 A cross-sectional front view taken by section line C can form a stacked structure 102, wherein the insulating structure 104 and the sacrificial structure 106 are vertically intersected and arranged in layers 108. The stacked structure 102 can be formed on one or more base structures 110 and can be supported by one or more base structures.

[0067] The stacked structure 102 can be formed by sequentially forming (e.g., depositing) the material of the electrically insulating structure 104 and the sacrificial material of the sacrificial structure 106, the stacked structure being eventually replaced by a conductive structure. Each of the layers 108 may individually contain a layer of one or two layers of insulating structure 104 directly vertically adjacent to the sacrificial structure 106. One or more additional insulating structures 112 may be formed (e.g., deposited) above the stacked structure 102.

[0068] The insulating structure 104 may be formed of and contain at least one electrically insulating material, such as one or more of the insulating materials discussed above (e.g., dielectric oxide materials, such as silicon dioxide). In this and other embodiments described herein, the insulating material of the insulating structure 104 may be the same as or different from other insulating materials of the microelectronic device structure.

[0069] The sacrificial structure 106 may be formed of an insulating material different from the insulating material of the insulating structure 104, and may contain an insulating material different from the insulating material of the insulating structure 104, and exhibit etch selectivity relative to the insulating material of the insulating structure 104. The sacrificial structure 106 may be selectively etchable relative to the insulating structure 104 during common (e.g., collectively, mutually) exposure to a first etchant, and the insulating structure 104 may be selectively etchable relative to the sacrificial structure 106 during common exposure to a second different etchant. As used herein, the first material is "selectively etchable" relative to the second material if it exhibits an etch rate at least about five times (5×) greater than the etch rate of the second material, for example, about ten times (10×), about twenty times (20×), or about forty times (40×). In some embodiments, the sacrificial structure 106 is formed of one or more of a dielectric nitride material (e.g., silicon nitride (Si3N4)) and a dielectric oxide nitride material (e.g., silicon oxynitride) and comprises one or more of the dielectric nitride material and the dielectric oxide nitride material. In some embodiments, the sacrificial structure 106 comprises silicon nitride, and the insulating structure 104 comprises silicon dioxide.

[0070] In some embodiments, the additional insulating structure 112 above the stacked structure 102 may be formed of and comprise an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, the additional insulating structure 112 comprises the same material composition as the insulating material of the insulating structure 104. In other embodiments, the additional insulating structure 112 comprises a different material composition than the insulating material of the insulating structure 104. In some embodiments, the additional insulating structure 112 (e.g., a single additional insulating structure 112) is formed of and comprises silicon dioxide. Additional insulating structures 112 that are some or all thicker than those in the insulating structure 104 may be formed individually.

[0071] The stacked structure 102 may be formed on and supported by one or more substrate structures 110, such as a source structure (e.g., a source plate), which may be formed and comprise a semiconductor material, such as a polysilicon doped with a P-type conductive material (e.g., polysilicon doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium)) or an N-type conductive material (e.g., polysilicon doped with at least one N-type dopant (e.g., one or more of arsenic, phosphorus, and antimony)).

[0072] The lowest layer 108 of the stacked structure 102 (e.g., the lowest insulating structure 104) may be directly on the substrate structure 110 (e.g., the source structure), or the stacked structure 102 may be overlaid on a stacked structure including additional layers (e.g., additional layers in the layer 108 of the insulating structure 104 and the sacrificial structure 106).

[0073] The stacked structure 102 shown can represent a single "stack" of a microelectronic device structure being manufactured. Additional stacks of layer 108 can be formed below (e.g., in the formation of...). Figure 1 The stacked structure 102 is previously formed on the substrate structure 110 or may be formed on it (e.g., on...). Figure 1 (on the stacked structure 102), and can be separated from the stacked structure 102 and from each other by one or more dielectric structures (e.g., one or more of the additional insulating structures 112).

[0074] The stack structure 102 can be formed and configured such that pillars (e.g., electrically active pillars) grouped into “blocks” can be formed within the stack structure to be separated from each other by slit structures formed during subsequent processing. For example, the stack structure 102 can be configured to include a slit region 116 between each pair of adjacent blocks, each block having a pillar array region 118 sized to accommodate a pattern of pillar openings 114, which may be defined by one or more reticles. The slit region 116 is wide enough for subsequent formation of block-defined slits, and wide enough to accommodate a pattern of pillar openings 120 between slits, which may be defined by the same one or more reticles or by one or more additional reticles.

[0075] Common Reference Figure 2 , Figure 2A (It is along) Figure 2 (The front view of the cross section taken by section line A) Figure 2B (It is along) Figure 2 (The front view of the cross section taken by section line B) and Figure 2C (that is) Figure 2 (The front view of the cross section taken by section line C), according to the pattern of column opening 114 ( Figure 1 A pillar opening 202 can be formed in the pillar array region 118. For example, the pillar opening 202 can be etched into the substrate structure 110 through layers 108 of the additional insulating structure 112 and the stacked structure 102. In some embodiments, the cross-section of the pillar opening 202 is substantially circular, and the width gradually decreases with increasing depth toward the substrate structure 110.

[0076] Slit-to-pillar openings 204 are formed in the slit region 116, spaced out along the slit region 116 in, for example, the y-axis direction. The slit-to-pillar openings 204 can be formed by etching through the additional insulating structure 112, the layers 108 of the stacked structure 102, at least to the substrate structure 110. In some embodiments, the slit-to-pillar openings 204 may extend at least partially into the substrate structure 110. Therefore, Figure 2A The diagram shows that the slit column opening 204 extends into the base structure 110, while the column opening 202 extends into the base structure 110. The greater depth of the slit column opening 204 allows the slit support columns to be formed to anchor the stacked structure 102 to the base structure 110, thereby suppressing delamination between the lowest layer 108 of the stacked structure 102 and the upper surface of the base structure 110.

[0077] The slit-shaped column opening 204 may individually define a cross-sectional area that is larger, smaller, or substantially equal to the cross-sectional area of ​​the column opening 202. Furthermore, in some embodiments, the cross-sectional shape of the slit-shaped column opening 204 may be the same as or different from the cross-sectional shape of the column opening 202.

[0078] In some embodiments, the cross-sectional shape of the slit-to-column opening 204 may be rectangular, for example, relatively elongated compared to the cross-sectional shape of the column opening 202. However, this disclosure is not limited to a rectangular shape for the slit-to-column opening 204. In other embodiments, the slit-to-column opening 204 may be formed to have other cross-sectional shapes.

[0079] The relative spacing of the slit column openings 204 along each slit region 116 can be customized according to the structural supports provided by the slit columns to be formed in the slit column openings 204.

[0080] In some embodiments, a slit-shaped column opening 204 may be formed, and it may be configured... Figure 1 The pattern of the slit column openings 120 is such that the width of each slit column opening 204 is smaller than the width of the slit region 116. Therefore, each slit column opening 204 can be substantially formed at the center of the width of each slit region 116, wherein at least a portion of the slit region 116 is laterally retained between the slit column opening 204 and each adjacent column array region 118.

[0081] In some embodiments, the column opening 202 and the inter-slit column opening 204 can be formed substantially simultaneously, such that the inter-slit column opening 204 can be etched while the column opening 202 is etched through the stacked structure 102. By forming the column opening 202 and the inter-slit column opening 204 simultaneously, material removal effects (e.g., etching effects) can be minimized, and the relative horizontal spacing (e.g., positioning) of the inter-slit column opening 204 and the column opening 202 can be reliably controlled. In such embodiments, the larger cross-sectional area of ​​the inter-slit column opening 204 relative to the column opening 202 allows the inter-slit column opening 204 to be formed deeper, at least partially formed in the substrate structure 110, while the column opening 202 is formed to terminate near the upper surface of the substrate structure 110.

[0082] In other embodiments, one of the slit column opening 204 and column opening 202 may be formed first, and then the other of the slit column opening 204 and column opening 202 may be formed.

[0083] Common Reference Figure 3 , Figure 3A (It is along) Figure 3 (The front view of the cross section taken by section line A) Figure 3B (It is along) Figure 3 (The front view of the cross section taken by section line B) and Figure 3C (that is) Figure 3 A hard mask 302 can be formed (e.g., irregularly deposited) above the stacked structure 102 (e.g., on the additional insulating structure 112). An opening 304 can be formed (e.g., etched) through the hard mask 302 to expose the inter-slit pillar opening 204 while leaving the pillar opening 202 covered. The size of the opening 304 can be set to expose at least the top of the inter-slit pillar opening 204. In some embodiments, the size of the opening 304 is also set to expose a portion of the upper surface of the additional insulating structure 112.

[0084] When covered by the hard mask 302, the pillar opening 202 can be empty (e.g., a void space). In other embodiments, one or more sacrificial materials (e.g., Al2O3) can be formed to substantially fill the pillar opening 202 before the hard mask 302 is formed.

[0085] The hard mask 302 may be formed of a material that is selectively etchable relative to the sacrificial material and may include the selectively etchable material. In some such embodiments, the hard mask 302 may be formed of, for example, carbon, silicon dioxide and / or doped silicon nitride and may include carbon, silicon dioxide and / or doped silicon nitride.

[0086] Common Reference Figure 4 , Figure 4A (It is along) Figure 4 (The front view of the cross section taken by section line A) Figure 4B (It is along) Figure 4 (The front view of the cross section taken by section line B) and Figure 4C (that is) Figure 4 (A cross-sectional front view taken by section line C), the sacrificial structure 106 may be recessed relative to the insulating structure 104, for example by a nitride selective etching operation (e.g., wet etching). Thus, the recess 402 is vertically formed between the ends of the insulating structure 104 that meet the slot post opening 204.

[0087] The etching conditions and timing can be controlled to ensure that the sacrificial structure 106 does not recess beyond the horizontal boundary (e.g., in the X-axis direction) of the slit region 116. The maximum recess horizontal dimension 404 (e.g., in the X-axis direction) does not exceed the width (e.g., X-axis dimension) of the slit region 116.

[0088] Due to the nature of the etchant used, for example, in an etching process to form the recesses of the sacrificial structure 106, the width (e.g., X-axis dimension) and length (e.g., Y-axis dimension) of the recess 402 may not necessarily be consistent with each other at every level of the sacrificial structure 106. Therefore, as... Figure 4A As shown, in the central X-axis view along the slit column opening 204, the maximum horizontal dimension 404 of the recess (e.g., the maximum recess width) can be located at approximately the midpoint of the height of the sacrificial structure 106, while... Figure 4C As shown in the central Y-axis view along the slit column opening 204, the maximum horizontal dimension 404 of the recess (e.g., the maximum recess length) can be located at the upper height of the sacrificial structure 106. However, the recess 402 may not extend into the column array region 118.

[0089] The formation of the inter-slit column opening 204 interrupts the hierarchy of the insulation structure 104 between adjacent column array regions 118. Along the longitudinal direction of the inter-slit column opening 204 adjacent to the slit region 116 (e.g., to the Y-axis, longitudinal side of the inter-slit column opening 204), the insulation structure 104 continues to bridge between adjacent column array regions 118. Upon contact with the inter-slit column opening 204, the sacrificial structure 106 is recessed to form a recess 402, and the bridging portions 406 of the insulation structure 104 are staggered with the recess 402, but each level in the insulation structure 104 provides one of the bridging portions 406 between adjacent column array regions 118. Laterally adjacent to the inter-slit column opening 204 toward the column array region 118 (e.g., to the X-axis lateral side of the inter-slit column opening 204), the insulation structure 104 forms an extension 408 that protrudes into the inter-slit column opening 204 due to the formation of the recess 402.

[0090] Common Reference Figure 5 , Figure 5A (It is along) Figure 5 (The front view of the cross section taken by section line A) Figure 5B (It is along) Figure 5 (The front view of the cross section taken by section line B) and Figure 5C (It is along) Figure 5 (A cross-sectional front view taken by section line C) Insulating material 502 can be formed (e.g., by ALD deposition) in the slit column opening 204 to fill the recess 402. Figures 4A to 4C The insulating material 502 may be any of the aforementioned insulating materials for the insulating structure 104 or other insulating materials for the microelectronic device structure, provided that the insulating material 502 is selectively etchable relative to the sacrificial structure 106. In some embodiments, the sacrificial structure 106 may include silicon nitride, and the insulating material 502 may be substantially free of nitride materials.

[0091] In some embodiments, the insulating material 502 may have the same composition as the insulating structure 104. However, since these materials are formed separately, the interface between the insulating structure 104 and the insulating material 502 can be detected during inspection.

[0092] The formation of insulating material 502 may or may not result in the formation of seam 504 within insulating material 502. In those embodiments where seam 504 is formed, the presence of seam 504 may not be detrimental to subsequent manufacturing operations, as subsequent manufacturing operations may not expose seam 504 to, for example, etchants.

[0093] The insulating material 502 can be obtained from layers within the substrate structure 110 (e.g., in an embodiment, the inter-slit post opening 204). Figure 2 It is formed to extend at least partially into the base structure 110, extends to at least the top of the stacked structure 102, and in some embodiments, also through the additional insulating structure 112.

[0094] The structure can then be planarized (e.g., by CMP) to remove the insulating material 502 and hard mask 302 covering the additional insulating structure 112, as shown below. Figure 6 , Figure 6A (It is along) Figure 6 (The front view of the cross section taken by section line A) Figure 6B (It is along) Figure 6 (The front view of the cross section taken by section line B) and Figure 6C (It is along) Figure 6 The cross-sectional front view (taken from section line C) is shown together. In some embodiments, some of the additional insulation structure 112 may also be removed.

[0095] Remove hard mask 302 (e.g., Figure 5A) Expose column opening 202 (e.g., Figure 5A In embodiments where the sacrificial material is formed to fill the pillar opening 202 before the hard mask 302 is formed, the sacrificial material can be removed (e.g., etched) after the hard mask 302 is removed to re-form the pillar opening 202.

[0096] In the event that the column opening 202 is exposed or reformed, the column 602 can then be formed (e.g., deposited) in the column opening 202, for example, by methods known in the art. Figure 5A ), to form a column array in column array region 118.

[0097] Common Reference Figure 7 , Figure 7A (It is along) Figure 7 (The front view of the cross section taken by section line A) Figure 7B (It is along) Figure 7 (The front view of the cross section taken by section line B) Figure 7C (It is along) Figure 7 (The front view of the cross section taken by section line C) and Figure 7D (It is along) Figure 7 The cross-sectional front view taken by the section line D can then be used to form (e.g., etch) slits 702 in slit region 116 by means of stacked structure 102. Instead of forming a single elongated slit along the entire length of slit region 116, the size of slit 702 is set and configured in a segment interspersed with previously formed insulating material 502.

[0098] The slit 702 is sized and configured to extend into the region of the maximum horizontal dimension 404 of the recess, and removes at least the central portion of each level of the sacrificial structure 106, which was previously retained on the longitudinal Y-axis side of the insulating material 502. This sizing can accommodate, for example, any curvature of the recess 402 (e.g., as...). Figure 4A and Figure 4B (as shown) or any gradual narrowing of the recess (e.g., Figure 4C As shown in the diagram), and any bends or gradual narrowing of the slit 702 to be formed, to ensure that no level of the sacrificial structure 106 is retained to fully extend through the slit region 116 between adjacent column array regions 118. Therefore, as Figure 7C As shown, along the centerline extending the length of the slit region 116, the slit support column 704 is formed of insulating material 502, wherein the slit 702 is defined by the remaining portion of the bridging portion 406 of the insulating structure 104 intersecting with the insulating material 502 of the slit support column 704, but does not have the sacrificial structure 106 portion retained along the Y-axis center of the slit region 116. Figure 7D The diagram shows a bridging portion 406 of the insulating structure 104 extending across the slit region 116. Figure 7D This is an X-axis view of the longitudinal region between one of the slits 702 and the central portion of the interslit support column 704.

[0099] During the formation of slit 702 (e.g., during etching), any seams 504 or other voids that may exist in the insulating material 502 may not be exposed to material removal chemicals (e.g., etchant) because at least the upper level of the inter-slit support post 704 (e.g., the level adjacent to the additional insulating structure 112) can be substantially filled with insulating material 502. Therefore, the presence of seams 504 or other voids in the insulating material 502 may not be detrimental to the formation of slit 702.

[0100] After forming slit 702 at a selected location along slit region 116, as Figure 8 , Figure 8A (It is along) Figure 8 (The front view of the cross section taken by section line A) Figure 8B (It is along) Figure 8 (The front view of the cross section taken by section line B) Figure 8C (It is along) Figure 8 (The front view of the cross section taken by section line C) and Figure 8D (It is along) Figure 8 As shown in the cross-sectional front view (cut by section line D), the remaining portion of the sacrificial structure 106 can be substantially removed (e.g., excavated). Excavating the sacrificial structure 106 (e.g., Figure 7A ), leaving a stacked structure 802 with layers 804, said layers 804 including those at the location of the sacrificial structure 106 (e.g., Figure 7A The gaps 806 formed by the interlaced insulating structure 104. Because the slits 702 are formed in this way to ensure that there is no hierarchy of sacrificial structures 106 extending continuously across the slit area 116 between two adjacent column array areas 118, the sacrificial structures 106 are excavated at least along the center of the width of the inter-slit support column 704 and no gaps 806 are formed to the Y-axis, the longitudinal side of the inter-slit support column 704. Therefore, as Figure 8C As shown, for slit 702, the sidewalls intersecting the width of slit region 116 are formed by insulating material 502 and the remaining portion of insulating structure 104, which provides bridging portion 406 between adjacent column array regions 118.

[0101] Common Reference Figure 9 , Figure 9A (It is along) Figure 9 (The front view of the cross section taken by section line A) Figure 9B (It is along) Figure 9 (The front view of the cross section taken by section line B) Figure 9C (It is along) Figure 9(The front view of the cross section taken by section line C) and Figure 9D (It is along) Figure 9 (A cross-sectional front view taken by section line D), one or more conductive materials can be formed in the voids 806 (e.g., Figure 8A In ) to effectively replace the sacrificial structure 106 (e.g., Figure 7A Therefore, the stacked structure 902 is formed by layers 904 of insulating structure 104 and conductive structure 906. The insulating structure 104 and conductive structure 906 are vertically interleaved throughout the stacked structure 902. Due to the construction of the slit 702, no layer of conductive structure 906 completely spans the slit region 116. Therefore, due to the construction of the slit 702 and due to the insulating properties between the slits, the conductive structure 906 in one of the column array regions 118 is separated from the conductive structure 906 in the adjacent column array region 118, and the bridging portion 406 of the support column 704 and the insulating structure 104 that do span the slit region 116 is at least longitudinally adjacent to the inter-slit support column 704.

[0102] The conductive structure 906 may be formed of and contain a conductive material, such as one or more of the following: at least one metal (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, and gold); at least one alloy (e.g., an alloy of one or more of the aforementioned metals); or at least one metal-containing material containing one or more of the aforementioned metals (e.g., metal nitride, metal silicide, metal carbide, metal oxide, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x The conductive structure 906 comprises at least one of the aforementioned conductive materials, alloys thereof, at least one conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.), polycrystalline silicon, and / or at least one other material exhibiting conductivity. In some embodiments, the conductive structure 906 comprises at least one of the aforementioned conductive materials and at least one additional conductive material formed as a liner. For example, the conductive structure 906 may comprise at least one of the aforementioned metals and a conductive liner comprising at least one of the aforementioned metal-containing materials. For example, some or all of the conductive structure 906 may comprise a conductive nitride liner (e.g., tungsten nitride liner) having a conductive metal (e.g., tungsten) surrounded at least partially by a conductive nitride liner. The conductive liner may be directly adjacent to the insulating structure 104. In other embodiments, the conductive structure 906 may consist substantially of a conductive material or a homogeneous combination of conductive materials, wherein the conductive material is directly adjacent to and extends therebetween the vertically adjacent insulating structure 104, for example, without an indistinguishable conductive liner.

[0103] The conductive structure 906 can be configured as a "replacement gate" word line (e.g., a word line formed by a so-called "replacement gate" or "gate delay" process). In some embodiments, the number (e.g., quantity) of the layers 904 of the stacked structure 902 and therefore the number of conductive structures 906 in the stacked structure 902 can range from thirty-two layers 904 (and conductive structures 906) to two hundred and fifty-six layers 904 (and conductive structures 906). In some embodiments, the stacked structure 902 comprises one hundred and twenty-eight layers 904 (and conductive structures 906). However, this disclosure is not limited thereto, and the stacked structure 902 may comprise a different number of layers 904 (and conductive structures 906).

[0104] Common Reference Figure 10 , Figure 10A (It is along) Figure 10 (The front view of the cross section taken by section line A) Figure 10B (It is along) Figure 10 (The front view of the cross section taken by section line B) Figure 10C (It is along) Figure 10 (The front view of the cross section taken by section line C) and Figure 10D (It is along) Figure 10 The cross-sectional front view taken by section line D can be seen in slit 702 (e.g., Figure 9 One or more non-conductive materials are formed in the slit structure 1002 to form the microelectronic device structure 1000, wherein the slit structure 1002 extends between the slit support pillars 704 in the slit region 116. The bridging portion 406 of the insulating structure 104 may be directly adjacent to the slit structure 1002 (e.g., directly horizontally adjacent, directly longitudinally adjacent).

[0105] The slit structure 1002 may be formed of and comprise a non-conductive material. For example, the slit structure 1002 may be formed of and comprise a dielectric material, such as one or more of dielectric oxide materials (e.g., silicon dioxide), dielectric nitride materials (e.g., silicon nitride), and / or non-conductive polymer materials. In some embodiments, the slit structure 1002 may be formed of and comprise one or more of the following materials: phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, the slit structure 1002 comprises silicon dioxide. The material of the slit structure 1002 may be formulated or otherwise configured to serve as a stress-compensating material.

[0106] The physical stability of each block comprising one of the column array regions 118 can be enhanced due to the presence of the interslit support pillar 704 and the bridging portion 406 of the insulating structure 104 spanning the slit region 116 and extending from one column array region 118 to another. That is, the presence of the interslit support pillar 704 and the bridging portion 406 can be achieved during processing, for example, during the formation of the slit 702 (e.g., Figure 7 During the period of excavation of sacrificial structure 106 (e.g., Figure 8A And / or during the filling of slit 702 with the material of slit structure 1002, it inhibits adjacent blocks (e.g., adjacent column array regions 118) from moving toward or away from each other. Thus, the inter-slit support columns 704 and bridging portions 406 provide enhanced structural support for the microelectronic device structure 1000, and in particular the blocks (e.g., column array regions 118) of the microelectronic device structure 1000.

[0107] Furthermore, due to the enhanced structural support for the column array region 118 provided by the bridging portions 406 of the interslit support pillars 704 and the insulating structure 104, in some embodiments, the material of the slit structure 1002 can be selected from a wider variety of materials than those otherwise considered in conventional structures. For example, the microelectronic device structure 1000 can be formed of a material with less independent material strength and stability, such as a material with relatively lower rigidity or strength compared to the materials originally required for the slit structure material between blocks (e.g., between column arrays). Therefore, in some embodiments, during the formation of one or more portions of the slit structure 1002, one or more materials of the slit structure 1002 can be formed from and contain a liquid. This liquid may or may not be subsequently treated (e.g., heat-treated) to solidify the slit structure 1002.

[0108] Therefore, a microelectronic device is disclosed. The microelectronic device includes a stacked structure. The stacked structure includes a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one slit region divides the stacked structure into blocks. Each block includes an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stacked structure.

[0109] Common Reference Figure 11 , Figure 11A (It is along) Figure 11 (The front view of the cross section taken by section line A) Figure 11B (It is along) Figure 11 (The front view of the cross section taken by section line B) Figure 11C (It is along) Figure 11 (The front view of the cross section taken by section line C) and Figure 11D (It is along) Figure 11 (A cross-sectional front view taken by section line D). In an additional embodiment, the microelectronic device structure 1100 may include a non-monolithic slit structure 1002. For example, one or more seams 1102 may be formed in the material of the slit structure 1002. Since the slit structure 1002 is formed in sections separated by inter-slit support pillars 704 and by bridging portions 406 of the insulating structure 104, the presence of seams 1102 in the slit structure 1002 may not present significant structural failure points (e.g., cracking) during subsequent processing or use. Therefore, there are fewer restrictions on the formation of the material of the slit structure 1002 compared to, for example, a single elongated structure extending the entire length of the slit region 116.

[0110] In some embodiments, even when the bridging portion 406 of the insulation structure 104 does not cross the slit region 116, improved structural support (and, for example, reduced likelihood of block bending) and avoidance of material failure points can be achieved. Accordingly, the recessed sacrificial structure 106 can be omitted (e.g., Figure 4A ).For example, Figure 12 (together) Figure 12A , Figure 12B and Figure 12C )to Figure 14 (together) Figure 14A , Figure 14B and Figure 14C An example of this is shown.

[0111] Figure 12 (as well as Figure 12A It is along Figure 12 A front view of the cross section taken by section line A; Figure 12B It is along Figure 12 The front view of the cross section taken by section line B; and Figure 12C , it is Figure 12 The stages shown in the front view of the cross-section (cut by section line C) can follow the steps outlined in the reference above. Figure 1 The aforementioned stage. According to... Figure 12 Formed (e.g., etched) through the stacked structure 102 for the interslit support pillars 704 (e.g., Figure 11 The slit-column opening 1202 may be wider and / or longer in width and / or length compared to an embodiment where the sacrificial structure 106 is recessed. However, the size and shape of the slit-column opening 1202 are configured not to extend beyond the width of the slit region 116.

[0112] In some embodiments, the interslit pillar opening 1202 and the pillar opening 202 may be formed (e.g., etched) simultaneously through the stacked structure 102, and a hard mask 302 may then be formed to at least cover the pillar opening 202 (e.g., a sacrificial material may be formed or not formed initially to fill the pillar opening 202). In other embodiments, the pillar opening 202 may be formed first in the stacked structure 102, followed by the formation of a hard mask 302 on the pillar opening 202 (e.g., a sacrificial material may be formed or not formed initially to fill the pillar opening 202), and the hard mask 302 may then be patterned to define an opening 304, which may then be transferred downwards through the stacked structure 102 to form the interslit pillar opening 1202.

[0113] Without first recessing the sacrificial structure 106, the slit column opening 1202 can then be filled, as shown below. Figure 13 , Figure 13A (It is along) Figure 13 (The front view of the cross section taken by section line A) Figure 13B (It is along) Figure 13 (The front view of the cross section taken by section line B) and Figure 13C (It is along) Figure 13 The cross-sectional front view taken by section line C is shown in common. For example, as described above, an insulating material 502 can be formed. In some embodiments, forming the insulating material 502 may involve forming voids or seams in the insulating material 502. In other embodiments, the insulating material 502 may be formed without voids or seams.

[0114] Then, the manufacturing process can be referred to as above. Figures 1 to 11 The process described is as follows. For example, the structure can be planarized (e.g., via CMP) to remove the upper height of the insulating material 502 and remove the hard mask 302. Slit 702 (e.g., Figure 7 It can be formed in sections along the slit area 116, supported by inter-slit support columns 704 (e.g., Figure 7 The insulating material 502 is separated. Then, as... Figure 14 , Figure 14A (It is along) Figure 14 (The front view of the cross section taken by section line A) Figure 14B (It is along) Figure 14 (The front view of the cross section taken by section line B) and Figure 14C (It is along) Figure 14 As shown in the cross-sectional front view taken by section line C, the sacrificial structure 106 can be substantially excavated and replaced by a conductive structure 906 and a non-conductive material formed in the slit 702 (e.g., with or without seam 1102) to form the slit structure 1002.

[0115] As in the above embodiments, slit 702 (e.g., Figure 7 The size of ) is set and configured to ensure that the sacrifice structure 106 (e.g., Figure 13C The height of the conductive structure 906 will not span the entire slit region 116. Therefore, the height of the conductive structure 906 will not completely span the width of the slit region 116 in the microelectronic device structure 1400.

[0116] In forming the slit column opening 1202 ( Figure 12 The sacrificial structure 106 is not recessed between the insulating material 502 forming the slit support column 704 and the slit support column 704. Figure 13A In the case of ), such as Figure 14C As shown, the slit support post 704 can be directly adjacent (e.g., directly longitudinally adjacent) to the slit structure 1002 along the interface between the slit structure 1002 and the slit support post 704, without the bridging portion 406 of the insulating structure 104 (e.g., Figure 10C ).

[0117] In some embodiments, the sidewalls of the conductive structure 906 may be substantially aligned with the sidewalls of the insulating structure 104 along the slot support post 704, for example... Figure 14A and Figure 14B As shown, this is because the sacrificial structure 106 is not recessed before the insulating material 502 forms the interslit support post 704, and because the sacrificial structure 106 is completely replaced with the conductive structure 906. In other embodiments, the conductive structure 906 may be formed to not completely fill the space created by excavating the sacrificial structure 106 (e.g., Figure 7B The gap 806 left behind (for example, Figure 8B This allows the conductive structure 906 to remain slightly recessed relative to the insulating structure 104 in the microelectronic device structure 1400.

[0118] In the microelectronic device structure 1400, even without the bridging portion 406 of the insulating structure 104 spanning the slit region 116, the presence of the inter-slit support pillar 704 can still contribute to the formation of the slit 702 (e.g., Figure 7 ), excavating sacrificial structures 106 (e.g., Figures 7B to 8B This provides structural support for adjacent column array regions 118 during such processing operations and during the material formation of the slit structure 1002. Therefore, the inter-slit support columns 704 can prevent adjacent blocks (e.g., adjacent column array regions 118) from bending toward each other. In some embodiments, the inter-slit support columns 704 can also prevent adjacent blocks (e.g., adjacent column array regions 118) from bending away from each other, for example due to the material adhesion between the insulating material 502 of the inter-slit support columns 704 and the adjacent material of the stacked structure 902.

[0119] Furthermore, in the microelectronic device structure 1400, the presence of the interslit support pillar 704 interrupts the slit region 116, causing the slit structure 1002 to be formed as a segment along the entire length of the slit region 116 rather than a single elongated structure. The presence of any seams 1102 or other voids in the material of the slit structure 1002 may not present significant material failure points (e.g., cracking) during subsequent processing or operation, as referenced above. Figures 11 to 11C As described. In some embodiments, since the slit area 116 is interrupted by the presence of the slit support post 704, the slit structure 1002 can be formed with a predetermined seam 1102, or with other openings retained in the slit structure 1002, without the problem of crack formation.

[0120] Figures 1 to 14 The illustrations (including their views “A”, “B”, “C” and / or “D” where appropriate) can represent the structure of a microelectronic device (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100, Figure 14 The microelectronic device structure 1400 is a stack. In an additional embodiment, the microelectronic device structure may include more than one stack. In such a multi-stack embodiment, each stack can be formed sequentially according to the manufacturing method described above. For example, it can be performed... Figures 1 to 10 The method is to form the first stack, and then it can be repeated for each additional stack. Figures 1 to 10 The method, wherein the previously formed stack is represented by the base structure 110 shown in the figure. In other embodiments, Figures 1 to 14 The structures shown (including their views “A”, “B”, “C” and / or “D” as appropriate) can represent more than one stack of microelectronic device structures, making it possible to process all layers 108 of multiple (e.g., some or all) stacks simultaneously.

[0121] Although the foregoing description assumes that the insulating structure 104 is initially interleaved with the sacrificial material in the form of the sacrificial structure 106 (e.g., such that the microelectronic device structure is formed via a so-called "replacement gate" or "gate delay" process), in other embodiments, the structure shown and described as the sacrificial structure 106 may not be sacrificial, but may be formed from the outset as the material of the conductive structure 906 (e.g., such that the microelectronic device structure includes a so-called "floating gate"). In these latter embodiments, the structure interleaved with the insulating structure 104 does not need to be excavated and replaced. Otherwise, the manufacturing method may be as described above.

[0122] Therefore, a method for forming a microelectronic device is disclosed. The method includes forming a stacked structure comprising a vertically alternating sequence of insulating structures and other structures arranged in layers. An array of pillar openings extending through the stacked structure is formed. A series of support pillar openings are formed in regions between the pillar opening arrays. The support pillar openings extend through the stacked structure. The support pillar openings are substantially filled with additional insulating material to form an intermediate support pillar structure. Pillars are formed in the pillar opening array to form a pillar array. The pillars include at least one channel material. Adjacent arrays in the pillar array are separated by the regions. A series of slits are formed in the regions between adjacent arrays. Each slit is horizontally inserted between a pair of support pillar structures formed by the intermediate support pillar structure. The series of slits is filled with a non-conductive material to form a series of slit structure segments that horizontally alternate with the support pillar structures.

[0123] The pillar 602 of the microelectronic device structure constructed and / or formed according to embodiments of this disclosure can provide a memory cell string of a memory device. Therefore, Figures 15A to 15D A magnified view shows the structure of a microelectronic device according to some embodiments of the present disclosure (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The memory cell 1502 of the microelectronic device structure 1400 (e.g., Figure 15A Memory cell 1502' Figure 15B Memory cell 1502", Figure 15C The memory cell 1502"' and Figure 15D The memory unit 1502""). Figures 15A to 15D Each diagram can represent Figure 10A , Figure 11A and / or Figure 14A A simplified enlarged view of block MC is shown, but for ease of illustration and discussion, the gradually narrowing sidewalls of column 602 are not illustrated. References to one or more "memory cells 1502" are also made to this. Figures 15A to 15D One or more of the memory cells 1502 shown (e.g., Figure 15A Memory cell 1502' Figure 15B Memory cell 1502″ Figure 15C The memory cell 1502”' and Figure 15D The memory unit 1502"").

[0124] like Figures 15A to 15D Each of these is shown, for example in a microelectronic device structure (e.g., Figure 10 Microelectronic device structure 1000, Figure 11Microelectronic device structure 1100 and / or Figure 14 In an embodiment of a microelectronic device architecture 1400 formed via a so-called "replacement gate" process, memory cells 1502 are located near at least one layer 904, wherein at least one of the insulating structures 104 is vertically adjacent to another structure 1504 (e.g., conductive structure 906) formed by and containing the conductive structure 1506. In other embodiments, such as in a microelectronic device architecture (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 In embodiments where the microelectronic device structure 1400 is formed with a so-called "floating gate" configuration, other structures 1504 may be formed of and contain conductive semiconductor-based materials.

[0125] Adjacent to the layer 904 having insulating structure 104 and other structures 1504 (e.g., conductive structure 906) is the material of pillar 602, comprising unit material 1508 and insulating material 1510. Unit material 1508 comprises at least channel material 1512. Channel material 1512 can be horizontally inserted between insulating material 1510 and layer 904 of stacked structure 902 (e.g., Figure 10A , Figure 11A , Figure 14A ).

[0126] The insulating material 1510 may be formed of and comprise an electrically insulating material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), nitrogen oxides (e.g., silicon oxynitride), dielectric carbon nitride materials (e.g., silicon carbon nitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 1510 comprises silicon dioxide.

[0127] The channel material 1512 may be formed of and include one or more of the following materials: semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V composite semiconductor material, at least one II-VI composite semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials), and oxide semiconductor materials. In some embodiments, the channel material 1512 comprises amorphous silicon or polycrystalline silicon. In some embodiments, the channel material 1512 includes a doped semiconductor material. An insulating material 1510 may be horizontally adjacent to the channel material 1512.

[0128] In some embodiments, for example Figure 15A In one embodiment, the cell material 1508 of the memory cell 1502' further comprises: a tunnel dielectric material 1514 (also referred to as a "tunneling dielectric material") which is horizontally adjacent to the channel material 1512; a memory material 1516 which is horizontally adjacent to the tunnel dielectric material 1514; a dielectric barrier material 1518 (also referred to as a "charge barrier material") which is horizontally adjacent to the memory material 1516; and a dielectric barrier material 1520 which is horizontally adjacent to the dielectric barrier material 1518.

[0129] The tunnel dielectric material 1514 may be formed of and contain a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions, for example, by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. The tunnel dielectric material 1514 may be formed of and contain one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 1514 comprises silicon dioxide or silicon oxynitride.

[0130] Memory material 1516 may include a charge-trapping material or a conductive material. Memory material 1516 may be formed from and include one or more of the following materials: silicon nitride, silicon oxynitride, polycrystalline silicon (e.g., doped polycrystalline silicon), conductive materials (e.g., tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting materials, polycrystalline or amorphous semiconductor materials, containing at least one elemental semiconductor element and / or containing at least one compound semiconductor material, conductive nanoparticles (e.g., ruthenium nanoparticles), and metal dots. In some embodiments, memory material 1516 includes silicon nitride. Dielectric barrier material 1518 may be formed from and include a dielectric material such as an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride) or one or more of another material. In some embodiments, dielectric barrier material 1518 includes silicon oxynitride.

[0131] In some embodiments, the tunnel dielectric 1514, the memory material 1516, and the dielectric barrier material 1518 together may form a structure configured to trap charges, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric 1514 comprises silicon dioxide, the memory material 1516 comprises silicon nitride, and the dielectric barrier material 1518 comprises silicon dioxide.

[0132] The dielectric barrier material 1520 may be formed from one or more of the following and includes one or more of the following: metal oxides (e.g., one or more of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, gadolinium oxide, niobium oxide, and titanium trioxide), dielectric silicides (e.g., aluminum silicide, hafnium silicate, zirconium silicate, lanthanum silicide, yttrium silicide, and tantalum silicide), and dielectric nitrides (e.g., aluminum nitride, hafnium nitride, lanthanum nitride, yttrium nitride, and tantalum nitride).

[0133] In some embodiments of the memory cell, for example having Figure 15A The memory cell 1502', with dielectric barrier material 1520, can be horizontally adjacent to the stacked structure 902. Figure 10A , Figure 11A , Figure 14AThe channel material 1512 may be horizontally inserted between the insulating material 1510 and the tunnel dielectric material 1514; the tunnel dielectric material 1514 may be horizontally inserted between the channel material 1512 and the memory material 1516; the memory material 1516 may be horizontally inserted between the tunnel dielectric material 1514 and the dielectric barrier material 1518; the dielectric barrier material 1518 may be horizontally inserted between the memory material 1516 and the dielectric barrier material 1520; and the dielectric barrier material 1520 may be horizontally inserted between the dielectric barrier material 1518 and the layers of the other structures 1504 (e.g., the layers of the conductive structure 906).

[0134] Reference Figure 15B The illustration shows a memory cell 1502" according to an embodiment of the present disclosure, wherein the microelectronic device structure (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The microelectronic device structure 1400 has been formed by replacing the gate process. Figure 15A One or more (e.g., all) memory cells 1502' may be provided by Figure 15B The memory cell 1502" is replaced. The memory cell 1502" may contain a plurality of conductive materials 1506 within the conductive structure 906 of layer 904 (e.g., within other structures 1504). Figure 15A For example, conductive structure 906 may include conductive material 1522 within conductive liner material 1524. Conductive liner material 1524 may be directly adjacent to the upper and lower surfaces of insulating structure 104, and conductive material 1522 may be directly and vertically positioned between portions of conductive liner material 1524. During the manufacture of memory cell 1502", conductive liner material 1524 may include, for example, a seed material capable of forming conductive material 1522. Conductive liner material 1524 may be formed from and include, for example, metals (e.g., titanium, tantalum), metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, conductive liner material 1524 includes titanium nitride, and conductive material 1522 includes tungsten.

[0135] In other embodiments, the conductive liner material 1524 is not included, and the conductive material 1522 may be adjacent to and in physical contact with the insulating structure 104, for example, with... Figure 15A The conductive material 1506 contacts the memory cell 1502′ as described above.

[0136] refer to Figure 15CAccording to an additional embodiment of this disclosure, a simplified cross-section is shown for memory cell 1502”'. Figure 15A Memory cell 1502' and / or Figure 15B One or more (e.g., all) of the memory cells 1502″ can be generated by Figure 15C The memory cell 1502″' is replaced. The memory cell 1502″' may include an insulating material 1510 and a channel material 1512, as described above, and may also include a first dielectric material 1526 (e.g., a tunnel dielectric material) horizontally adjacent to the channel material 1512. A second dielectric material 1528 (e.g., a charge trapping material) may be horizontally adjacent to the first dielectric material 1526; and a third dielectric material 1530 (e.g., a charge blocking material) may be horizontally adjacent to the second dielectric material 1528 and the conductive material 1522. In some embodiments, the first dielectric material 1526 includes an oxide material (e.g., silicon dioxide), the second dielectric material 1528 includes a nitride material (e.g., silicon nitride), and the third dielectric material 1530 includes an oxide material (e.g., silicon dioxide). For clarity, in Figure 15C In the middle, conductive lining material 1524 ( Figure 15B (Not shown) around the conductive material 1522; however, in some embodiments, the memory cell 1502″′ may further include such a conductive liner material 1524.

[0137] refer to Figure 15D The simplified cross-section shows a memory cell 1502″″ according to an additional embodiment of the present disclosure, wherein the memory cell 1502″″ can be configured as a so-called “floating gate” memory cell. Figure 15A Memory cell 1502' Figure 15B The memory cell 1502" and / or Figure 15C One or more (e.g., all) of the memory cells 1502”' can be used Figure 15DThe memory cell 1502"" is replaced. In addition to the insulating material 1510 and the channel material 1512, the memory cell 1502"" may also include an electrode structure 1536, which may be referred to as a "floating gate". The electrode structure 1536 may include a conductive material, such as polysilicon and / or one or more of the materials described with respect to conductive material 1522 (e.g., tungsten). The memory cell 1502"" may further include a dielectric material 1532, which may be referred to as a "gate dielectric" material. The dielectric material 1532 may include one or more of the materials described above with reference to tunnel dielectric material 1514. In some embodiments, the dielectric material 1532 includes silicon dioxide. Another dielectric material 1534 may be located around a portion of the electrode structure 1536. The other dielectric material 1534 may include one or more of the materials described above with reference to tunnel dielectric material 1514. In some embodiments, the other dielectric material 1534 has the same material composition as dielectric material 1532. Another dielectric material 1534 may be located between the electrode structure 1536 and the conductive material 1522. For clarity, in Figure 15D In the middle, conductive lining material 1524 ( Figure 15B (Not shown) Around the conductive material 1522. However, it should be understood that in some embodiments, the memory cell 1502”” may include a conductive liner material 1524.

[0138] Therefore, column 602 ( Figure 10 , Figure 11 , Figure 14 Each of the units in the stack structure 902 can provide a string of memory cells 1502 that extend vertically or at least partially vertically through the stack structure 902.

[0139] Regardless of the memory cell 1502, and therefore the microelectronic device structure (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The microelectronic device structure 1400) uses a replacement gate (e.g., to form a...) Figure 15A Memory cell 1502' Figure 15B Memory cell 1502", Figure 15C The memory cell 1502”’) or with a floating gate (e.g., to form a ... Figure 15D The memory cell 1502 is formed, and the memory cell 1502 may be located in one of the other structures 1504 (e.g., one of the layers 904 of the stacked structure 902). Figure 10 , Figure 11 , Figure 14 ()) and one of the columns 602 extending through the stacked structure 902 ( Figure 10 , Figure 11 , Figure 14At the intersection of the two columns, column 602 contains at least channel material 1512.

[0140] Therefore, an electronic device comprising a column array is disclosed. The column array includes columns extending vertically through a stacked structure. The stacked structure includes conductive structures that alternate vertically with insulating structures. The columns include at least one channel material. A series of support columns run along a region separating adjacent columns in the column array. The support columns extend vertically through the stacked structure. A series of slit structures extend vertically through the stacked structure in the region separating the adjacent columns. Each of the series of support columns is horizontally inserted between a pair of slit structures in the series of slit structures.

[0141] refer to Figure 16 This illustration shows a partial cross-sectional perspective schematic diagram of a portion of a microelectronic device 1600 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 1602. The microelectronic device structure 1602 may be substantially similar to, for example... Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The microelectronic device structure 1400.

[0142] like Figure 16 As shown, the microelectronic device structure 1602 may include a stepped structure 1604, which defines a method for connecting access lines 1606 to conductive layers 1608 (e.g., conductive layers, conductive plates, etc.). Figure 10 , Figure 11 and / or Figure 14 The conductive structure 906 of the stacked structure 902 Figure 10 , 11 , Figure 14 The contact area of ​​the microelectronic device structure 1602 may include pillars 602 forming strings 1610 of memory cells 1612. Figure 10 , Figure 11 , Figure 14 ), for example, previous references Figures 15A to 15D The string of one or more memory cells 1502 is described. The pillars 602 forming the string 1610 of memory cells 1612 may be relative to conductive layer 1608, relative to data line 1614, relative to source layer 1616 (e.g., in substrate structure 110). Figure 10 , Figure 11 , Figure 14The gate is at least partially vertical (e.g., along the Z direction) and extends vertically relative to access line 1606, relative to first select gate 1618 (e.g., upper select gate, drain select gate (SGD)), relative to select line 1620 and / or relative to second select gate 1622 (e.g., lower select gate, source select gate (SGS)).

[0143] The first selection gate 1618 may be horizontally (e.g., in the X direction) divided into multiple blocks 1630 (e.g., each block 1630 includes a column array region 118). Figure 10 , Figure 11 , Figure 14 One of the plurality of blocks passes through slit 1628 (e.g., along slit region 116). Figure 10 , Figure 11 , Figure 14 The sections of slit 702 interrupted by the slit support column 704 are separated from each other (e.g., along the X-axis direction).

[0144] Vertical conductive contacts 1624 can electrically couple components to each other, as shown. For example, select line 1620 can be electrically coupled to first select gate 1618, and access line 1606 can be electrically coupled to conductive layer 1608. The microelectronic device 1600 may also include a control unit 1626 located below the memory array, which may include control logic configured to control various operations of other features of the microelectronic device 1600 (e.g., memory string 1610, memory cell 1612). As a non-limiting example, control unit 1626 may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V -NEGWLThe control unit 1626 includes, for example, a charge pump (DVC2 charge pump), a delay-locked loop (DLL) circuit (e.g., a ring oscillator), a Vdd regulator, a driver (e.g., a string driver), a decoder (e.g., a local stack decoder, a column decoder, a row decoder), a sense amplifier (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a repair circuit (e.g., a column repair circuit, a row repair circuit), an I / O device (e.g., a local I / O device), a memory test device, a MUX, an error checking and correction (ECC) device, a self-refresh / wear-out equalization device, and / or other chip / stack control circuitry. The control unit 1626 may be electrically coupled to, for example, a data line 1614, a source layer 1616, an access line 1606, a first select gate 1618, and / or a second select gate 1622. In some embodiments, the control unit 1626 includes complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, the control unit 1626 may be characterized by having an "array-under-CMOS" ("CuA") configuration.

[0145] The first selection gate 1618 may extend horizontally in a first direction (e.g., the Y-axis direction) and may be coupled to a corresponding first group of strings 1610 of memory cells 1612 at a first end (e.g., the upper end). The second selection gate 1622 may be formed in a substantially planar configuration and may be coupled to strings 1610 at a second opposite end (e.g., the lower end) of strings 1610 of memory cells 1612.

[0146] Data lines 1614 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the X-axis direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 1618 extends. Data lines 1614 may be coupled to a corresponding second group of strings 1610 at a first end (e.g., upper end) of the string 1610. The first group of strings 1610 coupled to the corresponding first select gate 1618 may share a specific string 1610 with the second group of strings 1610 coupled to the corresponding data lines 1614. Therefore, a specific string 1610 may be selected at the intersection of a specific first select gate 1618 and a specific data line 1614. Thus, the first select gate 1618 can be used to select memory cells 1612 of the string 1610 of memory cells 1612.

[0147] Conductive layers 1608 (e.g., word lines) may extend in a corresponding horizontal plane. Conductive layers 1608 may be stacked vertically such that each conductive layer 1608 is coupled to all strings 1610 of the memory cell 1612, and the strings 1610 of the memory cell 1612 extend vertically through the stack of conductive layers 1608 (e.g., stack structure 902, e.g., Figure 10, Figure 11 , Figure 14 Conductive layer 1608 may be coupled to or may form the control gate of memory cell 1612 to which conductive layer 1608 is coupled. Each conductive layer 1608 may be coupled to a memory cell 1612 of a specific string 1610 of memory cells 1612.

[0148] The first select gate 1618 and the second select gate 1622 are operable to select a specific string 1610 of memory cell 1612 between a specific data line 1614 and the source layer 1616. Therefore, a specific memory cell 1612 can be selected and electrically coupled to the data line 1614 by operating (e.g., by selecting) the appropriate first select gate 1618, second select gate 1622, and conductive stack layer 1608 coupled to the specific memory cell 1612.

[0149] The stepped structure 1604 can be configured to provide an electrical connection between the access line 1606 and the conductive layer 1608 via a vertical conductive contact 1624. In other words, a specific layer of the conductive layer 1608 can be selected via one of the access lines 1606 electrically connected to a corresponding conductive contact 1624, the conductive contact being electrically connected to a specific conductive layer 1608.

[0150] Data line 1614 can be electrically coupled to string 1610 of memory cell 1612 via conductive structure 1632. Embodiments of the electronic systems disclosed herein may utilize structures incorporating microelectronic devices (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 Microelectronic device structure 1400) and microelectronic device (e.g., microelectronic device 1600). For example, Figure 17 This is a block diagram of an electronic system 1700 according to an embodiment of the present disclosure. The electronic system 1700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or Tablet computers, e-books, navigation devices, etc. Electronic system 1700 includes at least one memory device 1702. Memory device 1702 may include, for example, microelectronic devices and / or structures described previously herein (e.g., Figure 16 Microelectronic devices 1600, Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14One or more embodiments of the microelectronic device structure 1400, for example having a structure formed according to the embodiments previously described herein.

[0151] The electronic system 1700 may further include at least one electronic signal processor device 1704 (generally referred to as a “microprocessor”). The processor device 1704 may optionally include embodiments of the microelectronic devices and / or microelectronic device architectures previously described herein (e.g., Figure 16 Microelectronic devices 1600, Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The microelectronic device architecture 1400 is described. The electronic system 1700 may further include one or more input devices 1706 for users to input information into the electronic system 1700, such as a mouse or other pointing device, keyboard, touchpad, buttons, and / or control panel. The electronic system 1700 may also include one or more output devices 1708 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 1706 and output device 1708 may include a single touchscreen device, which can be used to input information into the electronic system 1700 and output visual information to the user. The input device 1706 and output device 1708 may be electrically connected to one or more of the memory device 1702 and the electronic signal processor device 1704.

[0152] Therefore, an electronic system is disclosed, comprising an input device, an output device, a processor device, and a memory device. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device and includes at least one microelectronic device structure. The at least one microelectronic device structure includes a column array block laterally separated from each other by regions. The regions include a series of insulating support columns longitudinally alternating with a series of slit structures. The column array block includes columns extending vertically through a stacked structure. The stacked structure includes conductive structures vertically intersecting with the insulating structures. The columns include at least one channel material. The insulating support columns and the slit structures each extend vertically through the stacked structure in the regions separating the column array blocks.

[0153] refer to Figure 18 A block diagram of a processor-based system 1800 is shown. The processor-based system 1800 may include various microelectronic devices manufactured according to embodiments of this disclosure (e.g., Figure 16 Microelectronic devices 1600) and microelectronic device structures (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 The processor-based system 1800 can be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 1800 may include one or more processors 1802 (e.g., microprocessors) to control system functions and process requests within the processor-based system 1800. The processor 1802 and other sub-components of the processor-based system 1800 may include microelectronic devices manufactured according to embodiments of this disclosure (e.g., microprocessors). Figure 16 Microelectronic devices 1600) and microelectronic device structures (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 Microelectronic device structure 1400).

[0154] The processor-based system 1800 may include a power supply 1804 operatively connected to the processor 1802. For example, if the processor-based system 1800 is a portable system, the power supply 1804 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and / or a rechargeable battery. For example, the power supply 1804 may also include an AC adapter, allowing the processor-based system 1800 to be plugged into a wall outlet. For example, the power supply 1804 may also include a DC adapter, allowing the processor-based system 1800 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0155] Various other devices may be coupled to processor 1802 depending on the functions performed by processor-based system 1800. For example, user interface 1806 may be coupled to processor 1802. User interface 1806 may include one or more input devices, such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 1808 may also be coupled to processor 1802. Display 1808 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 1810 may also be coupled to processor 1802. RF subsystem or baseband processor 1810 may include antennas coupled to RF receivers and RF transmitters. Communication port 1812 or more may also be coupled to processor 1802. The communication port 1812 may be adapted to couple to one or more peripheral devices 1814 (e.g., modems, printers, computers, scanners, cameras) and / or networks (e.g., local area networks (LANs), remote LANs, corporate intranets, or the Internet).

[0156] Processor 1802 can control processor-based system 1800 by implementing software programs stored in memory (e.g., system memory 1816). For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, and / or media playback software. Memory (e.g., system memory 1816) is operatively coupled to processor 1802 to store and facilitate the execution of various programs. For example, processor 1802 may be coupled to system memory 1816, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and / or other known memory types. System memory 1816 may include volatile memory, non-volatile memory, or combinations thereof. System memory 1816 is typically large enough to dynamically store loaded application programs and data. In some embodiments, system memory 1816 may include the semiconductor devices described above (e.g., Figure 16 Microelectronic devices 1600) and structures (e.g., Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 Microelectronic device structure 1400 or a combination thereof.

[0157] Processor 1802 may also be coupled to non-volatile memory 1818, which does not imply that system memory 1816 is necessarily volatile. Non-volatile memory 1818 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory to be used in conjunction with system memory 1816. The size of non-volatile memory 1818 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Additionally, non-volatile memory 1818 may include mass storage (e.g., disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory). Non-volatile memory 1818 may include the microelectronic devices described above (e.g., Figure 16 Microelectronic devices 1600) and structures (e.g. Figure 10 Microelectronic device structure 1000, Figure 11 Microelectronic device structure 1100 and / or Figure 14 Microelectronic device structure 1400 or a combination thereof.

[0158] Non-limiting example embodiments may include the following, individually or in combination:

[0159] Example 1: A microelectronic device comprising: a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers; at least one slit region dividing the stacked structure into blocks, each block including an array of active pillars; and a horizontally alternating sequence of slit structure segments and support pillar structures along the at least one slit region, each of the slit structure segments and the support pillar structures extending vertically through the stacked structure.

[0160] Example 2: The microelectronic device according to Example 1, wherein for each layer of the insulating structure of the stacked structure, at least one portion extends laterally across the at least one slit region between a pair of blocks.

[0161] Example 3: A microelectronic device according to any one of Examples 1 and 2, wherein the maximum width of the support column structure is less than or equal to the maximum width of the slit structure segment.

[0162] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the support pillar structure extends to a lower depth within the microelectronic device compared to the depth to which the slit structure segment extends.

[0163] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the slit structure segment includes a seam.

[0164] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the conductive structure of the stacked structure is laterally recessed relative to the insulating structure of the stacked structure adjacent to the support pillar structure.

[0165] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein at the level of the stacked structure, the cross-sectional area of ​​one of the support pillar structures is larger than the cross-sectional area of ​​one of the active pillars of the active pillar array.

[0166] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein: the pillars in the active pillar array have a circular cross-sectional area; and the support pillar structure has a cross-sectional area other than the circular cross-sectional area.

[0167] Example 9: The microelectronic device according to Example 8, wherein the support pillar structure has a rectangular cross-sectional area.

[0168] Example 10: A microelectronic device according to any one of Examples 1, 3 to 5 and 7 to 9, wherein none of the insulating structures of the stacked structure extends laterally across the at least one slit region between a pair of blocks.

[0169] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein the sidewalls of the support pillar structure gradually narrow to the height of the stacked structure.

[0170] Example 12: A microelectronic device comprising: a pillar array block including pillars extending vertically through a stacked structure, the stacked structure including insulating structures alternating vertically with conductive structures, the pillars including at least one channel material; a series of support pillars extending vertically through the stacked structure along a region separating adjacent blocks in the pillar array block; and a series of slit structures extending vertically through the stacked structure in the region separating the adjacent blocks; each of the series of support pillars being horizontally inserted between a pair of slit structures in the series of slit structures.

[0171] Example 13: The microelectronic device according to Example 12 further includes a portion of the insulating structure spanning the region from one of the adjacent blocks to the other of the adjacent blocks.

[0172] Example 14: The microelectronic device according to Example 12, wherein each of the insulating structures in the stacked structure includes at least one portion that laterally spans the region.

[0173] Example 15: A microelectronic device according to any one of Examples 12 to 14, wherein none of the conductive structures in the stacked structure crosses the region.

[0174] Example 16: A method of forming a microelectronic device, the method comprising: forming a stacked structure including a vertically alternating sequence of insulating structures and other structures arranged in layers; forming an array of pillar openings extending through the stacked structure; forming a series of support pillar openings extending through the stacked structure in a region between the pillar opening arrays; substantially filling the support pillar openings with an additional insulating material to form an intermediate support pillar structure; forming pillars comprising at least one channel material in the pillar opening array to form a pillar array, adjacent arrays of the pillar array being separated by the region; forming a series of slits in the region between the adjacent arrays, each slit horizontally inserted between a pair of support pillar structures formed by the intermediate support pillar structure; and filling the series of slits with a non-conductive material to form a series of slit structure segments horizontally alternating with the support pillar structures.

[0175] Example 17: The method according to Example 16, wherein forming the series of slits includes: removing at least a portion of the intermediate support pillar structure to form the support pillar structure including the additional insulating material, and removing at least a portion of each level of the other structures in the region such that none of the other structures spans the region between the adjacent arrays.

[0176] Example 18: The method according to any of Examples 16 and 17 further includes, before substantially filling the support post opening, recessing the other structure relative to the insulating structure via the support post opening.

[0177] Example 19: The method according to any one of Examples 16 to 18, wherein forming the column opening array and forming the series of support column openings includes simultaneously forming the column opening array and the series of support column openings through the stacking structure.

[0178] Example 20: The method according to any one of Examples 16 to 19 further includes forming a hard mask to cover the array of column openings before substantially filling the column openings.

[0179] Example 21: The method according to Example 20, wherein the additional insulating material substantially fills the support post opening, including the support post opening, and the additional insulating material is formed on the hard mask.

[0180] Example 22: The method according to any one of Examples 16 to 21, wherein forming the stacked structure comprising the vertical alternating sequence of the insulating structure and the other structures comprises forming the vertical alternating sequence of the insulating structure and the sacrificial structure.

[0181] Example 23: The method according to Example 22 further includes, after forming the series of slits: substantially removing the sacrificial structure to leave a gap between the insulating structures; and forming a conductive structure in the gap between the insulating structures.

[0182] Example 24: The method according to any of Examples 16 and 17 and 19 to 23, wherein: forming the series of support post openings extending through the stacked structure includes etching through the stacked structure to define gradually narrowing sidewalls along the insulating structure and the other structures; and substantially filling the support post openings with the additional insulating material includes forming the additional insulating material along the gradually narrowing sidewalls of the insulating structure and the other structures.

[0183] Example 25: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: a column array block laterally separated from each other by regions, the regions including a series of insulating support columns longitudinally alternating with a series of slit structures; a pillar array block including columns extending vertically through a stacked structure, the stacked structure including insulating structures vertically intersecting with conductive structures, the columns including at least one channel material; and the insulating support columns and the slit structures, each extending vertically through the stacked structure in the regions separating the column array blocks.

[0184] While the disclosed structures, devices (e.g., apparatuses), systems, and methods are susceptible to various modifications and alternatives in their embodiments, specific embodiments have been illustrated by way of example in the drawings and described in detail herein. However, this disclosure is not intended to be limited to the specific forms disclosed. In fact, this disclosure covers all modifications, combinations, equivalents, variations, and alternatives that fall within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; At least one slit region that divides the stacked structure into blocks, each block comprising an array of active pillars; as well as Along the at least one slit region, a horizontal alternating sequence of slit structure segments and support column structures extends vertically through the stacked structure, each of the slit structure segments and the support column structure extending vertically through the stacked structure. The conductive structure of the stacked structure is laterally recessed relative to the insulating structure of the stacked structure, which is adjacent to the support column structure laterally.

2. The microelectronic device of claim 1, wherein for each layer of the insulating structure of the stacked structure, at least one portion extends laterally across the at least one slit region between a pair of said blocks.

3. The microelectronic device according to any one of claims 1 to 2, wherein the maximum width of the support pillar structure is less than or equal to the maximum width of the slit structure segment.

4. The microelectronic device according to any one of claims 1 to 2, wherein the support pillar structure extends to a lower depth within the microelectronic device compared to the depth to which the slit structure segment extends.

5. The microelectronic device according to any one of claims 1 to 2, wherein the slit structure segment includes a seam.

6. The microelectronic device according to any one of claims 1 to 2, wherein at the level of the stacked structure, the cross-sectional area of ​​one of the support pillar structures is larger than the cross-sectional area of ​​one of the active pillars of the active pillar array.

7. The microelectronic device according to any one of claims 1 to 2, wherein: The columns in the active column array have circular cross-sectional regions; and The support column structure has a cross-sectional area other than the circular cross-sectional area.

8. The microelectronic device according to claim 7, wherein the support pillar structure has a rectangular cross-sectional area.

9. The microelectronic device according to any one of claims 1 and 2, wherein the sidewalls of the support pillar structure gradually narrow to the height of the stacked structure.

10. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; At least one slit region that divides the stacked structure into blocks, each block comprising an array of active pillars; as well as Along the at least one slit region, a horizontal alternating sequence of slit structure segments and support column structures extends vertically through the stacked structure, each of the slit structure segments and the support column structure extending vertically through the stacked structure. In the stacked structure, none of the insulating structures extend laterally across the at least one slit area between the pair of blocks.

11. A microelectronic device comprising: A block of column array, the column array comprising columns extending vertically through a stacked structure, the stacked structure comprising an insulating structure alternating vertically with a conductive structure, the columns comprising at least one channel material; A series of support columns extend vertically through the stacked structure along a region that separates adjacent blocks in the block array of columns. as well as A series of slit structures extending vertically through the stacked structure in the area separating the adjacent blocks. Each of the series of support columns is horizontally inserted between a pair of slit structures in the series of slit structures. Each of the insulating structures in the stacked structure includes at least one portion that laterally spans the region, and None of the conductive structures in the stacked structure spans the region.

12. The microelectronic device of claim 11, further comprising a portion of the insulating structure spanning the region from one of the adjacent blocks to the other of the adjacent blocks.

13. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: The area comprises a series of insulating support columns that are laterally separated from each other, the area consisting of a series of slit structures that alternate longitudinally. The column array block includes columns extending vertically through a stacked structure, the stacked structure including insulating structures vertically intersecting with conductive structures, and each column including at least one channel material. The insulating support column and the slit structure each extend vertically through the stacked structure in the region that separates the column array blocks. The conductive structure of the stacked structure is laterally recessed relative to the insulating structure of the stacked structure, which is adjacent to the insulating support column laterally.

14. A method of forming a microelectronic device, the method comprising: A stacked structure is formed, the stacked structure comprising a vertically alternating sequence of insulating structures and other structures arranged in layers; Forming an array of column openings extending through the stacked structure; In the area between the column opening arrays, a series of support column openings extending through the stacked structure are formed; The openings of the support columns are essentially filled with additional insulating material to form an intermediate support column structure; A column array comprising at least one channel material is formed in the column opening array to form a column array, and adjacent columns of the column array are separated by the region; A series of slits are formed in the region between the adjacent arrays, each slit being horizontally inserted between a pair of support pillar structures formed by the intermediate support pillar structure; as well as The series of slits are filled with a non-conductive material to form a series of slit structure segments that alternate horizontally with the support column structure.

15. The method of claim 14, wherein forming the series of slits comprises: At least a portion of the intermediate support column structure is removed to form the support column structure including the additional insulating material; as well as Remove at least a portion of each level of the other structures in the region, such that none of the other structures spans the region between the adjacent arrays.

16. The method of claim 14, further comprising, before substantially filling the support post opening, recessing the other structure relative to the insulating structure via the support post opening.

17. The method of claim 14, wherein: Forming the series of support post openings extending through the stacked structure includes etching through the stacked structure to define gradually narrowing sidewalls along the insulating structure and the other structures; and The additional insulating material is used to substantially fill the opening of the support column, including forming the additional insulating material along the gradually narrowing sidewalls of the insulating structure and the other structures.

18. The method according to any one of claims 14 to 17, wherein forming the column opening array and forming the series of support column openings comprises simultaneously forming the column opening array and the series of support column openings through the stacking structure.

19. The method according to any one of claims 14 to 17, further comprising forming a hard mask to cover the array of pillar openings before substantially filling the pillar openings.

20. The method of claim 19, wherein substantially filling the support post opening with the additional insulating material includes the additional insulating material being formed on the hard mask.

21. The method according to any one of claims 14 to 17: The stacked structure that forms the vertical alternating sequence of the insulating structure and the other structures includes a vertical alternating sequence of the insulating structure and the sacrificial structure; and After forming the series of slits, the method further includes: Essentially, the sacrificial structure is removed to leave a gap between the insulating structures; as well as Conductive structures are formed in the gaps between the insulating structures.

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