Method for extracting drain-source resistance in field effect transistor
By measuring and fitting the flicker noise of field-effect transistors, this paper solves the problem of extracting source-drain resistance in existing technologies, and provides a new method that is suitable for accurate resistance extraction of single devices and is applicable to future nanoscale devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI JIAOTONG UNIV
- Filing Date
- 2023-04-18
- Publication Date
- 2026-07-21
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Figure CN116449103B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of field-effect transistors, and more particularly to a method for extracting the drain-source resistance in a field-effect transistor. Background Technology
[0002] like Figure 1 As shown, the field-effect transistor includes a source region 102, a drain region 103, a channel region, and a gate structure 104. The source region 102 and drain region 103 are formed in the semiconductor substrate 101 on both sides of the gate structure 104. The channel region is the area located between the source region 102 and drain region 103 and covered by the gate structure 104. The source region 102 is connected to the source electrode, which is composed of a front-side metal layer, through a corresponding contact hole at the top. The drain region 103 is connected to the drain electrode, which is composed of a front-side metal layer, through a corresponding contact hole at the top.
[0003] When a device is turned on, parasitic resistance exists. Figure 1 In this diagram, the total resistance is represented by Rtotal, the source resistance by Rs, the channel resistance by Rch, the drain resistance by Rd, and the source-drain resistance by Rsd. The series relationship of the total resistance is shown in the resistor corresponding to mark 107. The formula for the total resistance is shown in the formula corresponding to mark 108, that is, Rtotal = Rch + Rs + Rd, and Rsd is Rs + Rd.
[0004] The source resistance is the parasitic resistance formed between the source region 102 and the source electrode.
[0005] Channel resistance is the parasitic resistance formed in the channel region.
[0006] The leakage resistance is the parasitic resistance formed between the drain region 103 and the drain electrode.
[0007] Typically, once the doping structure of the source and drain regions of a device is determined, the source resistance and drain resistance remain unchanged.
[0008] As semiconductor technology nodes advance, the feature size of transistors gradually shrinks, the channel resistance of devices decreases, and the source-drain resistance increases. Figure 2 This is a graph showing how the resistance of a field-effect transistor changes with process technology nodes; curve 201 is the International Technology Roadmap for Semiconductors (ITRS) roadmap, which shows that the technology nodes will continue to shrink.
[0009] Curve 202 shows the channel resistance as the technology node shrinks; curve 203 shows the source-drain resistance as the technology node shrinks. It can be seen that below the 20nm node, as shown by the dashed circle 204, the source-drain resistance becomes the dominant factor in the total resistance, severely limiting device performance. Therefore, accurately extracting the source-drain resistance of transistors plays a guiding role in improving manufacturing processes. However, source-drain resistance cannot be directly obtained through testing and can only be extracted from other parameters; therefore, establishing a method for accurately extracting the source-drain resistance of field-effect transistors becomes crucial.
[0010] Existing methods for extracting drain-source contact resistance can be mainly divided into the following two categories: The first type requires a set of MOS devices with different channel lengths for electrical testing. The test results of each channel length device are linearly fitted and extrapolated to obtain the magnitude of the drain-source contact resistance.
[0011] The second type of technology requires only a single MOS device, and its core principle is based on the linear region current formula of the MOS device: (1) (2) in, The voltage at internal nodes d and s is the voltage applied across the drain and source. , According to formulas (1) and (2), after mathematical transformation, the IV data are globally fitted, or in two (V) GS V DS The measurement was performed under voltage bias conditions, and the source and drain resistance was determined by solving a series of equations.
[0012] The first type of technique requires a set of devices with different channel lengths to extract the series resistance. It cannot be used if the channel length of the device under test is uniform or limited. Furthermore, this type of method can only obtain the mean value of the series resistance, not the distribution information, which is crucial in nanoscale integrated circuits.
[0013] The main problem with the second type of technology is mobility. Will follow , Variations in mobility and series resistance collectively affect IV characteristics, and the extraction of drain-source series resistance is influenced by changes in mobility. Different methods in this category employ different approximate assumptions regarding mobility variation, but it is difficult to completely avoid this effect. Furthermore, as channel length decreases, transport properties shift from drift-diffusion to ballistic transport, making the physical meaning and magnitude of mobility more complex and increasing the difficulty of extracting drain-source series resistance.
[0014] Therefore, it is necessary to improve the existing technology to overcome the above-mentioned defects. Summary of the Invention
[0015] The purpose of this invention is to provide a method for extracting the drain-source resistance in a field-effect transistor, so as to solve the problems existing in the prior art.
[0016] The above-mentioned technical objective of the present invention is achieved through the following technical solution: A method for extracting the drain-source resistance in a field-effect transistor includes the following steps: 1) Input voltage, and measure the flicker noise of the field-effect transistor; 2) While keeping the input voltage greater than the threshold voltage, change the input voltage and perform noise tests to measure the flicker noise of the field-effect transistor under different input voltages; 3) Subtract the noise caused by RTN defects from the flicker noise measured in steps 1) and 2) to obtain the remaining flicker noise; 4) The remaining flicker noise includes channel region scattering noise and drain-source resistance noise; based on the relationship between the intensity of the remaining flicker noise and Vg, the data is fitted to obtain the drain-source resistance to be extracted.
[0017] Furthermore, the input voltage Vd ≤ 50mV is used to ensure that the field-effect transistor is in the linear region during noise testing.
[0018] Furthermore, the noise spectrum caused by the RTN defect can be described as follows: The remaining flicker noise spectrum conforms to the form 1 / f after subtracting the noise contained in the RTN defect from the flicker noise.
[0019] Furthermore, the scattering noise in the channel region is described by the Hooge Model as Equation (3); (3) in, Where is the Hooge coefficient and N is the number of anti-type free electrons, it can be expressed as formula (4); (4) From formulas (3) and (4), the scattering noise in the channel region can be expressed as formula (5); (5).
[0020] Furthermore, the drain-source resistance noise can be described by formula (6); (6).
[0021] Furthermore, the overall noise of the field-effect transistor in the linear region is expressed by formula (7);
[0022] The total resistance It consists of channel resistance and drain-source resistance. The value of channel resistance changes when Vg changes. By fitting the data using formula (7), we obtain... , , ; That is, the value of the drain-source resistance to be extracted.
[0023] In summary, the present invention has the following beneficial effects: 1. This invention is a novel method for extracting the drain-source contact resistance of MOS devices. The principle it is based on is different from existing technologies, and it provides a new solution for reference and comparison.
[0024] 2. The test scheme is simple and easy to operate. It does not require devices with multiple channel lengths. Resistance extraction can be completed with a single device, and the resistance distribution can be obtained.
[0025] 3. The principle formula upon which this invention is based does not include mobility and is not affected by changes in mobility, making it applicable to future devices with shorter channel lengths. 4. The noise testing process and fitting extraction method of the present invention are easy to integrate into the testing instrument and can realize the automatic extraction process. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the field-effect transistor described in this invention.
[0027] Figure 2 This is a graph showing how the resistance of the field-effect transistor described in this invention changes with process technology nodes.
[0028] Figure 3 A schematic diagram illustrating the separation of noise caused by RTN defects from total noise as described in this invention.
[0029] Figure 4 A schematic diagram of the fitting result of the data fitting described in this invention. Detailed Implementation
[0030] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to the figures and specific embodiments.
[0031] like Figure 3 and Figure 4As shown, the present invention proposes a method for extracting the drain-source resistance in a field-effect transistor, comprising the following steps: 1) Input voltage, and measure the flicker noise of the field-effect transistor; The input voltage Vd ≤ 50mV is used to ensure that the field-effect transistor is in the linear region during noise testing.
[0032] 2) While keeping the input voltage greater than the threshold voltage, change the input voltage and perform noise tests to measure the flicker noise of the field-effect transistor under different input voltages; 3) Subtract the noise caused by RTN defects from the flicker noise measured in steps 1) and 2) to obtain the remaining flicker noise; The noise spectrum caused by RTN defects can be described as follows: The remaining flicker noise spectrum conforms to the form 1 / f after subtracting the noise contained in the RTN defect from the flicker noise.
[0033] 4) The remaining flicker noise includes channel region scattering noise and drain-source resistance noise; based on the relationship between the intensity of the remaining flicker noise and Vg, the data is fitted to obtain the drain-source resistance to be extracted.
[0034] The scattering noise in the channel region is described by the Hooge Model as Equation (3); (3) in, Where is the Hooge coefficient and N is the number of anti-type free electrons, it can be expressed as formula (4); (4) From formulas (3) and (4), the scattering noise in the channel region can be expressed as formula (5); (5).
[0035] Furthermore, the drain-source resistance noise can be described by formula (6); (6).
[0036] Furthermore, the overall noise of the field-effect transistor in the linear region is expressed by formula (7);
[0037] The total resistance It consists of channel resistance and drain-source resistance. The value of channel resistance changes when Vg changes. By fitting the data using formula (7), we obtain... , , ; That is, the value of the drain-source resistance to be extracted.
[0038] This invention extracts resistance by measuring flicker noise.
[0039] The core principle is that the flicker noise in the channel region and the drain-source series resistance differs in magnitude and variation, and the two are combined into the overall noise through a certain resistance ratio. This invention utilizes the overall noise variation measured under different voltages to extract the magnitude of the drain-source series resistance.
[0040] In this document, the terms "upper," "lower," "front," "back," "left," "right," "top," "bottom," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used for the clarity of expressing the technical solution and for the convenience of description, and therefore should not be construed as limiting the present invention.
[0041] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.
[0042] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.
Claims
1. A method for extracting the drain-source resistance in a field-effect transistor, characterized in that, Includes the following steps: 1) The input voltage is the gate input voltage Vg applied to the gate of the field-effect transistor, and the flicker noise of the field-effect transistor is measured; 2) While keeping the gate input voltage greater than the threshold voltage, change the gate input voltage and perform noise tests to measure the flicker noise of the field-effect transistor under different gate input voltages; keep the drain input voltage Vd of the field-effect transistor ≤ 50mV so that the field-effect transistor is in the linear region during the noise test; 3) Subtract the noise caused by RTN defects from the flicker noise measured in steps 1) and 2) to obtain the remaining flicker noise; 4) The remaining flicker noise includes channel region scattering noise and drain-source resistance noise; Based on the relationship between the intensity of the remaining flicker noise and the gate input voltage Vg, the data is fitted to obtain the drain-source resistance to be extracted. The scattering noise in the channel region The Hooge Model is described by formula (3); (3) in, Where is the Hooge coefficient and N is the number of anti-type free electrons, it can be expressed as formula (4); (4) From formulas (3) and (4), the scattering noise in the channel region can be expressed as formula (5); (5) The drain source resistance noise It can be described as formula (6); (6) The field-effect transistor exhibits overall noise in the linear region. The expression is given by formula (7); (7) The total resistance The channel resistance is composed of the channel resistance and the drain-source resistance. The channel resistance changes as the gate input voltage Vg changes. By fitting the data using formula (7), we obtain... , , ; That is, the value of the drain-source resistance to be extracted.
2. The method for extracting the drain-source resistance in a field-effect transistor according to claim 1, characterized in that, The noise spectrum caused by RTN defects can be described as follows: The remaining flicker noise spectrum conforms to the form 1 / f after subtracting the noise contained in the RTN defect from the flicker noise.