Read-write control method and device based on uhs psram controller

Abstract

This invention discloses a read / write control method and apparatus based on a UHS PSRAM controller. The method is applied to a UHS PSRAM controller, with multiple hosts and UHS PSRAMs connected to the controller. The method includes: the UHS PSRAM controller receiving operation information sent by any host via a bus, the operation information including at least an operation command; the UHS PSRAM controller storing the operation information in a target storage space; and the UHS PSRAM controller, based on command reading conditions, sending information corresponding to each pending operation command read from the target storage space to the UHS PSRAM, thereby triggering the UHS PSRAM to execute a matching operation based on the information corresponding to each pending operation command. Therefore, implementing this invention can improve the efficiency and accuracy of issuing commands to the UHS PSRAM, thereby improving the efficiency of UHS PSRAM data read / write, which is beneficial for meeting the read / write data requirements of the UHS PSRAM and thus improving the working performance of the UHS PSRAM.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a read / write control method and apparatus based on a UHS PSRAM controller. Background Technology

[0002] Pseudo-static random access memory (PSRAM) is a type of memory that uses dynamic random access memory technology to achieve functions similar to static random access memory.

[0003] As chip applications become increasingly complex and bandwidth performance requirements rise, conventional PSRAM is insufficient in certain scenarios, necessitating the use of Ultra High Speed ​​(UHS) pseudo-static random access memory (UHS PSRAM) to enhance performance. However, in practical applications, the interface clock frequency of UHS PSRAM is significantly higher than that of PSRAM, and their read / write timings differ. Therefore, existing PSRAM read / write control schemes are not suitable for UHS PSRAM. Consequently, proposing a technical solution suitable for UHS PSRAM and capable of improving its read / write efficiency is of paramount importance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a read / write control method and device based on a UHS PSRAM controller, which can improve the read / write efficiency of UHS PSRAM and improve the working performance of UHS PSRAM.

[0005] To address the aforementioned technical problems, the first aspect of this invention discloses a read / write control method based on a UHS PSRAM controller. The method is applied to a UHS PSRAM controller, and multiple hosts and UHS PSRAMs are respectively connected to the UHS PSRAM controller. The method includes:

[0006] The UHS PSRAM controller receives operation information sent by any of the hosts via the bus. The operation information includes at least an operation command, and the operation command is of one type: a read command type and a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read the corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write the corresponding data into the UHS PSRAM.

[0007] The UHS PSRAM controller stores the operation information in the target storage space;

[0008] The UHS PSRAM controller sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command read conditions, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each pending operation command. The type of the pending operation command is one of the read command type and the write command type.

[0009] As an optional implementation, in the first aspect of the present invention, the UHS PSRAM controller, based on command read conditions, sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM, thereby triggering the UHS PSRAM to execute a matching operation based on the information corresponding to each pending operation command, including:

[0010] The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions;

[0011] The UHS PSRAM controller reads multiple operation commands to be executed from the target storage space in sequence, according to the pre-determined command read control conditions.

[0012] The UHS PSRAM controller determines the information corresponding to each of the operation commands to be executed based on the target type;

[0013] The UHS PSRAM controller sends information corresponding to each of the operation commands to be executed to the UHS PSRAM, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each operation command to be executed.

[0014] As an optional implementation, in the first aspect of the present invention, the target storage space includes a first storage space corresponding to the read command type and a second storage space corresponding to the write command type;

[0015] The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions, including:

[0016] The UHS PSRAM controller determines the read command type and the high-priority type among the write command types;

[0017] The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type; the number of first commands corresponding to the read command type is the number of operation commands to be executed in the first storage space, and the number of second commands corresponding to the write command type is the number of operation commands to be executed in the second storage space.

[0018] The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type, including:

[0019] When the number of pending operation commands corresponding to the high priority type is greater than zero, the UHS PSRAM controller determines the target type of the pending operation commands as the high priority type;

[0020] or,

[0021] When the number of pending operation commands corresponding to the high priority type is greater than zero, the UHS PSRAM controller determines whether the number of pending operation commands corresponding to the low priority type is greater than or equal to a preset number threshold. The priority of the low priority type is lower than the priority of the high priority type.

[0022] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is greater than or equal to the preset number threshold, the UHS PSRAM controller determines the target type of the operation commands to be executed as the secondary priority type;

[0023] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is less than the preset number threshold, the UHS PSRAM controller determines the target type of the operation commands to be executed as the high priority type;

[0024] When the number of pending operation commands corresponding to the high priority type is zero and the number of pending operation commands corresponding to the low priority type is greater than zero, the UHS PSRAM controller determines the target type of the pending operation command as the low priority type.

[0025] As an optional implementation, in the first aspect of the present invention, the operation commands stored in the target storage space have corresponding data operation addresses, and the data operation addresses are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation address.

[0026] The UHS PSRAM controller, based on pre-determined command read control conditions, sequentially reads multiple operation commands to be executed corresponding to the command read control conditions from the target storage space, including:

[0027] The UHS PSRAM controller determines the lookup address;

[0028] The UHS PSRAM controller searches the target storage space for an operation command that matches the search address, wherein the data operation address of the operation command that matches the search address is the same as the search address.

[0029] When an operation command matching the lookup address is found in the target storage space, the UHS PSRAM controller reads the operation command matching the lookup address from the target storage space.

[0030] The UHS PSRAM controller re-executes the operation of determining the lookup address until no matching operation command is found in the target memory space.

[0031] As an optional implementation, in the first aspect of the invention, the UHS PSRAM controller determines the lookup address, including:

[0032] When the UHS PSRAM controller determines the lookup address for the first time, the UHS PSRAM controller determines the data operation address of the target operation command as the lookup address. The target operation command is the target type's pending operation command that has been stored in the target storage space for the longest time.

[0033] When the UHS PSRAM controller determines the lookup address for the first time, it determines the current lookup address by summing the previously determined lookup address with the data length corresponding to the target type. The data length corresponding to the target type is used to represent the data length corresponding to each operation command of the target type.

[0034] As an optional implementation, in the first aspect of the present invention, the operation information stored in the first storage space includes an identifier corresponding to each read operation command, wherein the identifier corresponding to the read operation command is used to determine the correspondence between the read operation command and the data to be read corresponding to the read operation command;

[0035] The method further includes:

[0036] When the target type is the read command type, the UHS PSRAM controller receives at least one read operation data returned by the UHS PSRAM, and each read operation data is data read from the UHS PSRAM based on the corresponding operation command to be executed;

[0037] The UHS PSRAM controller determines the identifier corresponding to the read operation data, and the identifier corresponding to the read operation data is the identifier corresponding to the read operation command that matches the read operation data;

[0038] The UHS PSRAM controller returns the read operation data and the corresponding identifier to the corresponding host via the bus.

[0039] As an optional implementation, in the first aspect of the present invention, the method further includes:

[0040] The UHS PSRAM controller generates a refresh command and sends the refresh command to the UHS PSRAM to trigger the UHS PSRAM to execute the refresh operation corresponding to the refresh command.

[0041] A second aspect of the present invention discloses a read / write control device based on a UHS PSRAM controller. The device is applied to the UHS PSRAM controller, and multiple hosts and UHS PSRAMs are respectively connected to the UHS PSRAM controller. The device includes:

[0042] A receiving module is configured to receive operation information sent by any of the hosts via a bus. The operation information includes at least an operation command, and the operation command is of one type: a read command type and a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write corresponding data into the UHS PSRAM.

[0043] A storage module is used to store the operation information in the target storage space;

[0044] The sending module is used to send information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command reading conditions, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each pending operation command. The type of the pending operation command is one of the read command type and the write command type.

[0045] As an optional implementation, in a second aspect of the present invention, the sending module sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command reading conditions, so as to trigger the UHS PSRAM to execute a matching operation according to the information corresponding to each pending operation command. The specific method includes:

[0046] Based on the conditions determined by the command, determine the target type of the operation command to be executed;

[0047] According to the predetermined command reading control conditions, multiple operation commands to be executed corresponding to the command reading control conditions are sequentially read from the target storage space;

[0048] Based on the target type, determine the information corresponding to each of the operation commands to be executed;

[0049] The information corresponding to each of the operation commands to be executed is sent to the UHS PSRAM to trigger the UHS PSRAM to perform the matching operation according to the information corresponding to each operation command to be executed.

[0050] As an optional implementation, in a second aspect of the present invention, the target storage space includes a first storage space corresponding to the read command type and a second storage space corresponding to the write command type;

[0051] The specific methods by which the sending module determines the target type of the operation command to be executed based on the command determination conditions include:

[0052] Determine the read command type and the high-priority type among the write command types;

[0053] The target type of the operation command to be executed is determined based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type; the number of first commands corresponding to the read command type is the number of operation commands to be executed in the first storage space, and the number of second commands corresponding to the write command type is the number of operation commands to be executed in the second storage space.

[0054] The specific method by which the sending module determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type includes:

[0055] When the number of pending operation commands corresponding to the high priority type is greater than zero, the target type of the pending operation command is determined to be the high priority type;

[0056] or,

[0057] When the number of pending operation commands corresponding to the high priority type is greater than zero, it is determined whether the number of pending operation commands corresponding to the low priority type is greater than or equal to a preset number threshold. The priority of the low priority type is lower than the priority of the high priority type.

[0058] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is greater than or equal to the preset number threshold, the target type of the operation command to be executed is determined as the secondary priority type.

[0059] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is less than the preset number threshold, the target type of the operation commands to be executed is determined as the high priority type;

[0060] When the number of pending operation commands corresponding to the high priority type is zero and the number of pending operation commands corresponding to the low priority type is greater than zero, the target type of the pending operation command is determined to be the low priority type.

[0061] As an optional implementation, in the second aspect of the present invention, the operation commands stored in the target storage space have corresponding data operation addresses, and the data operation addresses are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation address.

[0062] The specific method by which the sending module sequentially reads multiple operation commands to be executed corresponding to the pre-determined command reading control conditions from the target storage space includes:

[0063] Determine the lookup address;

[0064] Based on the lookup address, search in the target storage space for an operation command to be executed that matches the lookup address, wherein the data operation address of the operation command to be executed that matches the lookup address is the same as the lookup address;

[0065] When an operation command matching the lookup address is found in the target storage space, the operation command matching the lookup address is read from the target storage space.

[0066] The operation of determining the lookup address is re-executed until no operation command matching the lookup address is found in the target storage space.

[0067] As an optional implementation, in the second aspect of the present invention, the specific method by which the sending module determines the lookup address includes:

[0068] When the sending module determines the lookup address for the first time, it determines the data operation address of the target operation command as the lookup address. The target operation command is the target type's pending operation command that has been stored in the target storage space for the longest time.

[0069] When the sending module determines the lookup address for the first time, it determines the current lookup address by the sum of the previously determined lookup address and the data length corresponding to the target type. The data length corresponding to the target type is used to represent the data length corresponding to each operation command of the target type.

[0070] As an optional implementation, in a second aspect of the present invention, the operation information stored in the first storage space includes an identifier corresponding to each read operation command, wherein the identifier corresponding to the read operation command is used to determine the correspondence between the read operation command and the data to be read corresponding to the read operation command;

[0071] The receiving module is further configured to receive at least one read operation data returned by the UHS PSRAM when the target type is the read command type, wherein each read operation data is data read from the UHS PSRAM based on the corresponding operation command to be executed;

[0072] The device further includes:

[0073] The determination module is used to determine the identifier corresponding to the read operation data, wherein the identifier corresponding to the read operation data is the identifier corresponding to the read operation command that matches the read operation data;

[0074] The return module is used to return the read operation data and the corresponding identifier to the corresponding host through the bus.

[0075] As an optional implementation, in a second aspect of the invention, the apparatus further includes:

[0076] The refresh module is used to generate refresh commands;

[0077] The sending module is further configured to send the refresh command to the UHS PSRAM to trigger the UHS PSRAM to execute the refresh operation corresponding to the refresh command.

[0078] A third aspect of the present invention discloses another read / write control device based on a UHS PSRAM controller, the device comprising:

[0079] Memory containing executable program code;

[0080] A processor coupled to the memory;

[0081] The processor calls the executable program code stored in the memory to execute the read / write control method based on the UHS PSRAM controller disclosed in the first aspect of the present invention.

[0082] The fourth aspect of the present invention discloses a computer storage medium storing computer instructions, which, when invoked, are used to execute the read / write control method based on a UHS PSRAM controller disclosed in the first aspect of the present invention.

[0083] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0084] In this embodiment of the invention, the method is applied to a UHS PSRAM controller, and multiple hosts and UHS PSRAMs are respectively connected to the UHS PSRAM controller. The method includes: the UHS PSRAM controller receiving operation information sent by any host through a bus, the operation information including at least an operation command, and the operation command type being one of a read command type and a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write corresponding data into the UHS PSRAM; the UHS PSRAM controller stores the operation information in a target storage space; the UHS PSRAM controller, according to the command read conditions, sends the information corresponding to each of the operation commands to be executed read from the target storage space to the UHS PSRAM, so as to trigger the UHS PSRAM to execute a matching operation according to the information corresponding to each operation command to be executed, wherein the type of the operation command to be executed is one of a read command type and a write command type. As can be seen, implementing this invention enables the storage of operation information in the target storage space after receiving operation information from the host, and the sending of information corresponding to the operation command to be executed from the target storage space to the UHS PSRAM according to the command reading conditions. This improves the efficiency and accuracy of sending commands to the UHS PSRAM, thereby improving the efficiency of reading and writing data in the UHS PSRAM, which is beneficial to meeting the reading and writing data requirements of the UHS PSRAM and thus improving the working performance of the UHS PSRAM. Attached Figure Description

[0085] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0086] Figure 1 This is a schematic diagram of the application architecture of a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0087] Figure 2 This is a schematic diagram of the functional structure of a UHS PSRAM controller, which is a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention.

[0088] Figure 3 This is a flowchart illustrating a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention.

[0089] Figure 4 This is a flowchart illustrating another read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention.

[0090] Figure 5 This is a timing diagram of a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0091] Figure 6 This is a timing diagram of another read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0092] Figure 7 This is a timing diagram of another read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0093] Figure 8 This is a timing diagram of another read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0094] Figure 9 This is a schematic diagram of a read / write control device based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0095] Figure 10 This is a schematic diagram of another read / write control device based on a UHS PSRAM controller disclosed in an embodiment of the present invention;

[0096] Figure 11 This is a schematic diagram of the structure of another read / write control device based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Detailed Implementation

[0097] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0098] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0099] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0100] This invention discloses a read / write control method and apparatus based on a UHS PSRAM controller. After receiving operation information from the host, the method stores the operation information in a target storage space and, according to command read conditions, sends the information corresponding to the operation command to be executed, retrieved from the target storage space, to the UHS PSRAM. This improves the efficiency and accuracy of issuing commands to the UHS PSRAM, thereby increasing the efficiency of UHS PSRAM read / write data and better meeting the read / write data requirements of the UHS PSRAM, ultimately improving its performance. Detailed descriptions follow.

[0101] To better understand the read / write control method and apparatus based on a UHS PSRAM controller described in this invention, the application architecture applicable to the read / write control method based on a UHS PSRAM controller is first described. The application architecture applicable to this method can be as follows: Figure 1 As shown, Figure 1 This is a schematic diagram of the application architecture applicable to the read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Figure 1As shown, this application architecture includes at least a UHS PSRAM controller. Furthermore, the application architecture may also include multiple hosts and / or UHS PSRAMs. Even further, each host can be connected to the UHS PSRAM controller via a bus, and the UHS PSRAM can be connected to the UHS PSRAM controller via a UHS PSRAM PHY module. Furthermore, based on... Figure 1 The application architecture shown illustrates that the internal functional structure of the UHS PSRAM controller can be as follows: Figure 2 As shown.

[0102] Furthermore, in such Figure 1 In the application architecture shown, the host can send commands to the UHS PSRAM controller via the bus; the UHS PSRAM controller stores the received commands in the internal storage space of the UHS PSRAM; when a read / write operation is required, the UHS PSRAM reads the command to be executed and the corresponding information from the storage space, and sends the command and the corresponding information to the UHS PSRAM through the UHSPSRAM PHY module to trigger the UHS PSRAM to execute the operation corresponding to the command.

[0103] It should be noted that, Figure 1 The illustrated application architecture diagram is merely to show one application architecture applicable to a read / write control method based on a UHS PSRAM controller, and is not intended to limit other application architectures applicable to the read / write control method and apparatus based on a UHS PSRAM controller. Furthermore, as... Figure 2 The UHS PSRAM controller shown is as follows Figures 9-11 The read / write control device based on the UHS PSRAM controller shown has the same function, only the module division and module command method are different.

[0104] The above provides an example of one of the application architectures applicable to the read / write control method and device based on the UHS PSRAM controller. The following section provides a detailed description of the read / write control method and device based on the UHS PSRAM controller.

[0105] Example 1

[0106] Please see Figure 3 , Figure 3 This is a flowchart illustrating a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Figure 3The described read / write control method based on a UHS PSRAM controller can be applied to a UHS PSRAM controller, where multiple hosts and UHS PSRAMs are connected to the UHS PSRAM controller. The UHS PSRAM controller may include, for example: Figure 2 The module described, Figure 2 The arrows in the diagram indicate the direction of command and / or data transmission, and the UHS PSRAM controller can be one component of the on-chip system. Figure 1 The described SOC (System on Chip) Figure 1 The arrows in the diagram indicate the direction of command and / or data transmission, which is not limited in this embodiment of the invention; this read / write control method based on a UHS PSRAM controller can also be applied to devices, terminals, or systems that need to read data from and / or write data to UHS PSRAM, which is not limited in this embodiment of the invention. Figure 3 As shown, the read / write control method based on the UHS PSRAM controller may include the following operations:

[0107] 101. The UHS PSRAM controller receives operation information sent by any host via the bus.

[0108] In this embodiment of the invention, the operation information includes at least an operation command, and the operation command type is either a read command type or a write command type. The read command type operation command instructs the UHS PSRAM controller to read corresponding data from the UHS PSRAM, and the write command type operation command instructs the UHS PSRAM controller to write corresponding data into the UHS PSRAM. When the operation command type is a write command type, the operation information may further include the data to be written corresponding to the write operation command.

[0109] 102. The UHS PSRAM controller stores the operation information in the target storage space.

[0110] In this embodiment of the invention, the target storage space may include one or more storage spaces. The storage space may be a storage space in CAM (Content Addressable Memory) and may be used to store commands; the storage space may also be a storage space in RAM (Random Access Memory) and may be used to store data; the storage space may also be other storage spaces that can be used to store commands and / or data and other operational information. This embodiment of the invention does not limit the scope of the storage space.

[0111] 103. According to the command reading conditions, the UHS PSRAM controller sends the information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM, so as to trigger the UHS PSRAM to perform the matching operation according to the information corresponding to each pending operation command.

[0112] In this embodiment of the invention, the type of the operation command to be executed is either a read command type or a write command type; the UHS PSRAM reads at least one operation command to be executed from the target storage space, and even if multiple operation commands to be executed are read, they are sent to the UHS PSRAM at once; the UHS PSRAM controller can send the information corresponding to the operation command to be executed to the UHS PSRAM according to a preset timing sequence, wherein the preset timing sequence can be the interface timing sequence of the UHS PSRAM, the interface timing sequence of the UHS PSRAM controller, or a timing sequence defined based on the timing sequences of both the UHS PSRAM and the UHS PSRAM, and this embodiment of the invention does not limit the specific timing sequence.

[0113] As can be seen, the method described in the embodiments of the present invention can store the operation information in the target storage space after receiving the operation information issued by the host, and send the information corresponding to the operation command to be executed read from the target storage space to the UHS PSRAM according to the command reading conditions. This can improve the efficiency and accuracy of issuing commands to the UHS PSRAM, thereby improving the efficiency of reading and writing data in the UHS PSRAM, which is conducive to meeting the reading and writing data requirements of the UHS PSRAM, and thus improving the working performance of the UHS PSRAM.

[0114] In an optional embodiment, prior to step 101, the method may further include the following operations:

[0115] After the UHS PSRAM controller and UHS PSRAM PHY module complete the initialization operation, the UHS PSRAM controller generates an initialization command according to the initialization requirements of the UHS PSRAM. The UHS PSRAM controller and UHS PSRAM are respectively connected to the UHS PSRAM PHY module.

[0116] The UHS PSRAM controller sends an initialization command to the UHS PSRAM to trigger the UHS PSRAM to execute the initialization operation corresponding to the initialization command.

[0117] It should be noted that the UHS PSRAM PHY module can be used for clock frequency conversion, digital-to-analog I / O interfaces, and deskew between different I / O interfaces. Deskew is used to align the data lines corresponding to high-speed interfaces, making the skew (clock offset) of different data lines as similar as possible, thereby reducing the probability of transmission errors during data sampling.

[0118] As can be seen, this optional embodiment can perform initialization operations on the UHS PSRAM before receiving operation information from the host and after the UHS PSRAM controller and UHS PSRAM PHY module have completed initialization operations, which can improve the reliability of the UHS PSRAM and help improve the accuracy of the UHS PSRAM in performing read and write operations.

[0119] In another alternative embodiment, the method may further include the following operations:

[0120] The UHS PSRAM controller generates a refresh command and sends the refresh command to the UHS PSRAM to trigger the UHS PSRAM to execute the refresh operation corresponding to the refresh command.

[0121] It should be noted that the UHS PSRAM controller can perform the operation of generating refresh commands before, after, or simultaneously with any step in this optional embodiment, and this embodiment of the invention does not impose any limitations. In addition, the UHS PSRAM controller can generate refresh commands according to the refresh requirements of the UHS PSRAM, wherein the refresh requirements may include the number of refreshes performed in the refresh window; the UHS PSRAM controller can also generate refresh commands according to a pre-set refresh command timing sequence; the UHS PSRAM controller can also set a timer to generate refresh commands periodically, and this embodiment of the invention does not impose any limitations.

[0122] As can be seen, this optional embodiment can generate refresh commands and instruct the UHS PSRAM to perform refresh operations. It can generate refresh commands suitable for the UHS PSRAM according to the clock interface frequency of the UHS PSRAM, which can reduce the probability of data loss in the UHS PSRAM, improve the reliability of the data stored in the UHS PSRAM, and help improve the data accuracy of the UHS PSRAM in performing read and write operations, thereby helping to meet the read and write data requirements of the UHS PSRAM.

[0123] Furthermore, in this embodiment of the invention, exemplarily, when the UHS PSRAM controller to which the read / write control method based on the UHS PSRAM controller can be applied includes, as follows: Figure 2The modules described are as follows: initialization module for initialization operations, refresh module for refresh operations, write transmission module for transmitting write operation requests and other write operation-related signals, write command module for storing write commands, write data module for storing write data, read transmission module for transmitting read operation requests and other read operation-related signals, read command module for storing read commands, read data module for storing read data corresponding to received read commands, command scheduling module for collecting requests from the initialization module, refresh module, write transmission module, and read transmission module and returning response signals to the corresponding modules according to the arbitration mechanism, and interface module for interacting with the UHS PSRAM PHY module.

[0124] The technical solution described in this embodiment can be:

[0125] After the UHS PSRAM controller completes initialization, the initialization module sends an initialization request to the command scheduling module. The command scheduling module returns a response signal to the initialization module according to the arbitration mechanism. After receiving the response signal corresponding to the initialization request, the initialization module sends an initialization command to the UHS PSRAM through the UHS PSRAM PHY module to instruct the UHS PSRAM to perform the initialization operation.

[0126] When the host sends a read operation command to the UHS PSRAM controller via the bus, the read command module of the UHS PSRAM controller receives the read operation command and stores it in the CAM in the read command module. Then, the read transfer module sends a read operation request to the command scheduling module. The command scheduling module returns a response signal corresponding to the read operation request to the read transfer module according to the arbitration mechanism. After receiving the response signal corresponding to the read operation request through the read transfer module, the read command module reads the read operation command to be executed from the CAM and sends the read operation command to be executed to the UHS PSRAM to instruct the UHS PSRAM to execute the read operation corresponding to the read operation command to be executed.

[0127] When the host sends a write operation command to the UHS PSRAM controller via the bus, the write command module of the UHS PSRAM controller receives the write operation command and stores it in the CAM in the write command module, and the write data module receives the data to be written corresponding to the write operation command and stores it in the RAM in the write data module. Then, the write transmission module sends a write operation request to the command scheduling module. The command scheduling module returns a response signal corresponding to the write operation request to the write transmission module according to the arbitration mechanism. After receiving the response signal through the write transmission module, the write command module reads the write operation command to be executed from the CAM and reads the corresponding data to be written from the RAM of the write data module. The write transmission module then sends the write operation command to be executed and the data to be written to the UHS PSRAM to instruct the UHS PSRAM to execute the write operation corresponding to the write operation command to be executed.

[0128] The refresh module of the UHS PSRAM controller sends a timed refresh request to the command scheduling module according to the refresh requirements of the UHS PSRAM. The command scheduling module returns a response signal to the refresh module according to the arbitration mechanism. After receiving the response signal corresponding to the refresh request, the refresh module sends the refresh command corresponding to the refresh request to the UHS PSRAM through the UHS PSRAM PHY module.

[0129] The timing diagram of the interface related to the UHS PSRAM controller and the refresh command is as follows: Figure 5 As shown, Figure 5 hdr_clk is the master clock of the UHS PSRAM controller; phy_ce_p0~phy_ce_p3 are chip select signals. After receiving these signals, the UHS PSRAM PHY module will perform a parallel-to-serial conversion operation to obtain the / CE signal and send the / CE signal to the UHS PSRAM; phy_address[31:0] is the address or command signal. After receiving these signals, the UHS PSRAM PHY module will perform a parallel-to-serial conversion operation to obtain the part of the DQ[7:0] signal that represents cmd and send the part of the DQ[7:0] signal that represents cmd to the UHS PSRAM chip.

[0130] Example 2

[0131] Please see Figure 4 , Figure 4 This is a flowchart illustrating a read / write control method based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Figure 4The described read / write control method based on a UHS PSRAM controller can be applied to a UHS PSRAM controller, where multiple hosts and UHS PSRAMs are connected to the UHS PSRAM controller. The UHS PSRAM controller may include, for example: Figure 2 The module described, Figure 2 The arrows in the diagram indicate the direction of command and / or data transmission, and the UHS PSRAM controller can be one component of the on-chip system. Figure 1 The described SOC (System on Chip) Figure 1 The arrows in the diagram indicate the direction of command and / or data transmission, which is not limited in this embodiment of the invention; this read / write control method based on a UHS PSRAM controller can also be applied to devices, terminals, or systems that need to read data from and / or write data to UHS PSRAM, which is not limited in this embodiment of the invention. Figure 4 As shown, the read / write control method based on the UHS PSRAM controller may include the following operations:

[0132] 201. The UHS PSRAM controller receives operation information sent by any host via the bus.

[0133] 202. The UHS PSRAM controller stores the operation information in the target storage space.

[0134] 203. The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions.

[0135] In this embodiment of the invention, the target type of the operation command to be executed is either a read command type or a write command type.

[0136] 204. The UHS PSRAM controller reads multiple operation commands corresponding to the command read control conditions sequentially from the target storage space according to the pre-determined command read control conditions.

[0137] 205. The UHS PSRAM controller determines the information corresponding to each operation command to be executed based on the target type.

[0138] In this embodiment of the invention, when the target type is a write command type, the information corresponding to the operation command to be executed includes at least the data to be written corresponding to the operation command to be executed, and the information corresponding to the operation command to be executed may also include the operation command to be executed; when the target type is a read command type, the information corresponding to the operation command to be executed includes the operation command to be executed.

[0139] 206. The UHS PSRAM controller sends the information corresponding to each operation command to be executed to the UHS PSRAM, so as to trigger the UHS PSRAM to perform the matching operation according to the information corresponding to each operation command to be executed.

[0140] In this embodiment of the invention, for other detailed descriptions of steps 201-202, please refer to the detailed description of steps 101-102 in Embodiment 1. These descriptions will not be repeated in this embodiment of the invention.

[0141] As can be seen, the method described in the embodiments of the present invention can, after receiving operation information issued by the host, store the operation information in the target storage space, and send the information corresponding to the operation command to be executed read from the target storage space to the UHS PSRAM according to the command reading conditions. This can improve the efficiency and accuracy of issuing commands to the UHS PSRAM, thereby improving the efficiency of reading and writing data in the UHS PSRAM, which is beneficial to meeting the read and write data requirements of the UHS PSRAM and thus improving the working performance of the UHS PSRAM. In addition, it can first determine the target type of the operation command to be executed, and then sequentially read multiple execution operation commands corresponding to the command reading control conditions from the target storage space. Then, according to the target type, the information corresponding to each operation command to be executed is determined, and the information corresponding to each operation command to be executed is sent to the UHS PSRAM. This can improve the accuracy of determining the information corresponding to the operation command to be executed sent to the UHS PSRAM, thereby improving the accuracy of issuing command-related information to the UHS PSRAM, which is beneficial to improving the efficiency and accuracy of the UHS PSRAM in performing read and write data operations.

[0142] In an optional embodiment, the target storage space includes a first storage space corresponding to the read command type and a second storage space corresponding to the write command type;

[0143] The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions, which may include the following operations:

[0144] The UHS PSRAM controller determines the type of read command and the highest priority type among the write command types.

[0145] The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type; the number of first commands corresponding to the read command type is the number of operation commands to be executed in the first storage space, and the number of second commands corresponding to the write command type is the number of operation commands to be executed in the second storage space.

[0146] The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type. This can include the following operations:

[0147] When the number of pending operation commands corresponding to a high-priority type is greater than zero, the UHS PSRAM controller will determine the target type of the pending operation commands as a high-priority type;

[0148] or,

[0149] When the number of pending operation commands corresponding to a high priority type is greater than zero, the UHS PSRAM controller determines whether the number of pending operation commands corresponding to a low priority type is greater than or equal to a preset threshold. The priority of the low priority type is lower than the priority of the high priority type.

[0150] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is greater than or equal to the preset number threshold, the UHS PSRAM controller will determine the target type of the operation commands to be executed as the secondary priority type;

[0151] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is less than the preset threshold, the UHSPSRAM controller will determine the target type of the operation commands to be executed as the high priority type.

[0152] When the number of pending operation commands corresponding to the high-priority type is zero and the number of pending operation commands corresponding to the low-priority type is greater than zero, the UHS PSRAM controller determines the target type of the pending operation command as the low-priority type.

[0153] It should be noted that priority can be used to indicate the degree of priority of the selected execution of this type. The UHS PSRAM controller can choose to read the operation command to be executed corresponding to the higher priority type first, and then read the operation command to be executed corresponding to the next lower priority type. The first storage space corresponding to the read command type and the second storage space corresponding to the write command type can both include the storage space in CAM and / or RAM, and can also include other storage spaces that can be used to store commands and / or data and other operation information. This embodiment of the invention does not limit this. Priority can be preset, for example: the priority of the read command type is preset to be higher than the priority of the write command type. Priority can also be dynamically changed, wherein the priority can be dynamically determined by the change in the number of operation commands to be executed corresponding to this type within a preset time period. For example: if the number of operation commands to be executed corresponding to the read command type is much greater than the number of operation commands to be executed corresponding to the write command type within a preset time period, then the priority of the read command type is higher than the priority of the write command type. Priority can also be determined based on the execution priority of each type of operation. Priority can also be determined based on the execution efficiency of the UHS PSRAM in executing the operation corresponding to this type. This embodiment of the invention does not limit this.

[0154] For example, when the UHS PSRAM controller determines that the high priority type is a read command type, if there are read operation commands to be executed in the first storage space, the target type of the operation command to be executed can be directly determined as the read command type. Alternatively, it can first determine whether the number of write operation commands to be executed in the second storage space is greater than or equal to a preset number threshold. If the number of write operation commands to be executed in the second storage space is greater than or equal to the preset number threshold, the target type is determined as the write command type; otherwise, the target type is determined as the read command type. If there are no read operation commands to be executed in the first storage space but there are write operation commands to be executed in the second storage space, the target type can be directly determined as the write command type.

[0155] As can be seen, this optional embodiment can determine the target type of the operation command to be executed based on the priority of the command type and the quantity corresponding to the command type. This can improve the accuracy and efficiency of determining the target type, thereby improving the efficiency of reading the operation command to be executed of the target type and improving the efficiency of UHS PSRAM executing the operation corresponding to the target type. Furthermore, if the quantity of high-priority operation commands to be executed is greater than zero, the target type can be directly determined as a high-priority type. Alternatively, if the quantity of low-priority operation commands to be executed is less than a threshold, the target type can be determined as a high-priority type. If the quantity of low-priority operation commands to be executed is greater than or equal to a threshold, the target type can be determined as a low-priority type. If the quantity of high-priority operation commands to be executed is zero and the quantity of low-priority operation commands to be executed is greater than zero, the target type can be determined as low-priority. This can further improve the accuracy of determining the target type and improve the efficiency of reading the operation command to be executed of the target type.

[0156] In this optional embodiment, optionally, the operation commands stored in the target storage space have corresponding data operation addresses, and the data operation addresses are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation address;

[0157] The UHS PSRAM controller reads multiple operation commands corresponding to the pre-determined command read control conditions sequentially from the target memory space, which may include the following operations:

[0158] The UHS PSRAM controller determines the lookup address;

[0159] The UHS PSRAM controller searches the target memory space for an operation command that matches the lookup address. The data operation address of the operation command that matches the lookup address is the same as the lookup address.

[0160] When an operation command matching the lookup address is found in the target memory space, the UHSPSRAM controller reads the operation command matching the lookup address from the target memory space.

[0161] The UHS PSRAM controller re-executes the operation of determining the lookup address until a command to be executed that does not match the lookup address is found in the target memory space.

[0162] The data operation address may include a byte address, a row address, or other addresses conforming to the UHS PSRAM storage address format; this embodiment of the invention does not impose any limitations. The lookup address is determined based on the data operation address stored in the target storage space.

[0163] It should be noted that if the target type is a write command type, when the UHS PSRAM controller reads the operation command to be executed from the target storage space, it can simultaneously read the data to be written corresponding to the operation command to be executed; the target storage space in this embodiment of the invention can be the storage space corresponding to the target type, or it can be the entire target storage space, and this embodiment of the invention does not limit it.

[0164] As can be seen, this optional embodiment can also search for an execution command that matches the search address in the target storage space based on the determined search address. If an execution command that matches the search address is found, the execution command is read out and the search address is redefined. Otherwise, the search process ends and the execution command with the correct address is read out. This adjusts the order in which the execution commands in the target storage space are read and executed, improving the efficiency of reading the execution commands and thus improving the efficiency of reading and writing data in the UHS PSRAM.

[0165] In this optional embodiment, the UHS PSRAM controller may further optionally determine the lookup address by including the following operations:

[0166] When the UHS PSRAM controller first determines the lookup address, the UHS PSRAM controller determines the data operation address of the target operation command as the lookup address. The target operation command is the target type of operation command to be executed that has been stored in the target memory space for the longest time.

[0167] When the UHS PSRAM controller determines the lookup address for the first time, it uses the sum of the previously determined lookup address and the data length corresponding to the target type as the current lookup address. The data length corresponding to the target type is used to represent the data length corresponding to each operation command of the target type.

[0168] The target storage space may also include at least one register group, which can be used to record target operation commands.

[0169] For example, suppose three read operation commands with byte addresses of 0, 96, and 32 are stored sequentially in the target storage space, and the data length corresponding to the read command type is 32 bytes. If the current target type is a read command type, the lookup address will first be determined to be 0. After the read operation command with byte address 0 is found in the target storage space and read, the lookup address will be updated to 0 + 32 = 32. After the read operation command with byte address 32 is found in the target storage space and read, the lookup address will be updated to 32 + 32 = 64. However, if the read operation command with byte address 64 is not found in the target storage space, the read command operation will stop.

[0170] As can be seen, this optional embodiment can also determine the data operation address of the target operation command as the search address when the search address is determined for the first time, and determine the current search address as the sum of the previous search address and the data length corresponding to the target type when the search address is not determined for the first time. This can improve the accuracy of determining the search address and improve the efficiency of reading multiple pending operation commands with consecutive data operation addresses, which is beneficial to improving the efficiency of reading data from or writing data to UHS PSRAM.

[0171] Furthermore, in this embodiment of the invention, taking the target type as a write command type as an example, the interface timing diagram of UHS PSRAM for a single write operation in the read / write control method based on the UHS PSRAM controller is as follows: Figure 6 As shown, Figure 6 In the diagram, CK and / CK are the differential clocks of the UHS PSRAM interface, / CE is the chip select signal, DDS and / DQS are the data sampling clocks, and DQ and DQM are the data signal and data mask signal, respectively. When the / CE signal is pulled low, cmd transmitted through the DQ signal is the write command and the corresponding write address. After WL cycles, data transmitted through the DQ and DQM signals is the write data and the corresponding write mask. When the / CE signal is pulled low, the above write data can be continuously written to the UHS PSRAM. The location of the write data in the UHS PSRAM is calculated by using the write address in cmd as the starting address, and incrementing the starting address after storing a specified length of data to obtain a new storage address. A single write operation can write a maximum of one line of data to the UHS PSRAM at a time.

[0172] The proof that this method can improve the write operation efficiency of UHS PSRAM can be as follows:

[0173] The efficiency of a single write operation is calculated using the formula tdata / (tWL+tdata+tCPHw), where, for example... Figure 6 As shown, tWL is the time from issuing the cmd command to starting data transmission, which is related to the clock frequency; tdata is the duration of data transmission; and tCPHw is the time from the completion of this data transmission to the UHS PSRAM receiving the next set of commands, which is a fixed duration. From the efficiency calculation formula above, it can be seen that the longer tdata, the higher the access efficiency. For example, when the UHS PSRAM interface clock cycle is 1.25ns (frequency 800MHz), tWL is 14 clock cycles, and tCPHw is 24 clock cycles; if tdata is 16 clock cycles, the efficiency is 16 / (14+16+24) = 29.6%; if tdata is 256 clock cycles, the efficiency is 256 / (14+256+24) = 87%. Therefore, the longer tdata, i.e., the more data is transmitted in a single operation, the more significant the improvement in write operation efficiency to the UHS PSRAM. For example, based on the above discussion, assuming that the maximum amount of data that can be written to a line of UHS PSRAM is 2048 bytes, and the amount of data corresponding to a write command issued by the bus is 32 bytes, the two write commands at address 0 and address 32 can be concatenated. Then, the UHS PSRAM controller issues these two write commands to the UHS PSRAM, that is, initiates a write operation starting at address 0. The data corresponding to these two commands can be written to the UHS PSRAM at once to improve the efficiency of a single write operation.

[0174] Similarly, this method can also improve the efficiency of read operations.

[0175] In this optional embodiment, the operation information stored in the first storage space may further include an identifier corresponding to each read operation command. The identifier corresponding to the read operation command is used to determine the correspondence between the read operation command and the data to be read corresponding to the read operation command.

[0176] The method may also include the following operations:

[0177] When the target type is a read command type, the UHS PSRAM controller receives at least one read operation data returned by the UHS PSRAM, and each read operation data is data read from the UHS PSRAM based on the corresponding operation command to be executed;

[0178] The UHS PSRAM controller determines the identifier corresponding to the read operation data. The identifier corresponding to the read operation data is the identifier corresponding to the read operation command that matches the read operation data.

[0179] The UHS PSRAM controller returns the read operation data and the corresponding identifier to the host via the bus.

[0180] It should be noted that, in this embodiment of the invention, if the target type is a read command type, when the UHS PSRAM controller reads the read operation command to be executed from the target storage space, it also reads the identifier corresponding to the read operation command to be executed.

[0181] In this embodiment, when the UHS PSRAM controller issues a read operation command to the UHS PSRAM, it may not issue the identifier corresponding to the read operation command to the UHS PSRAM. When the UHS PSRAM controller receives read operation data, it can determine the identifier corresponding to the read operation data according to a specified order. This specified order can be the order in which the UHS PSRAM controller reads the read operation command from the target storage space, the order in which the UHS PSRAM controller issues the read operation command to the UHS PSRAM, or a pre-set order of read identifiers. This embodiment does not impose any limitations on this order. The specified order can be recorded using a first-in-first-out queue, a stack, a queue, a linked list, or other storage structures. In other words, it can use a first-in-first-out queue, a stack, a queue, a linked list, or other storage structures to record the identifier corresponding to the read operation command in a specified order. This embodiment does not impose any limitations on this order. When the UHS PSRAM controller issues a read operation command to the UHS PSRAM, it may also issue the identifier corresponding to the read operation command to the UHS PSRAM. The PSRAM sends an identifier corresponding to the read operation command. The identifier corresponding to the read operation command can be received at the same time as the read operation data, so the identifier corresponding to the read operation data can be directly determined. This embodiment of the invention does not limit this.

[0182] As can be seen, this optional embodiment can also receive read operation data returned by UHS PSRAM when the target type is a read command type, and return the read operation data and the identifier corresponding to the read operation data to the corresponding host. This can match the read operation data with the read operation command one by one, improve the accuracy and reliability of the returned read operation data, and help improve the efficiency and accuracy of reading data from UHS PSRAM.

[0183] Furthermore, in this embodiment of the invention, exemplarily, when the UHS PSRAM controller to which the read / write control method based on the UHS PSRAM controller can be applied includes, as follows: Figure 2 When referring to the described module, the technical solution described in this embodiment can be:

[0184] Assuming that the current UHS PSRAM controller prioritizes read operations to improve read efficiency, that is, the higher priority type is the read command type, and the priority of the read command type is higher than the priority of the write command type;

[0185] Assume the UHS PSRAM controller receives four read commands and their corresponding identifiers (each read command corresponds to a 32-byte data length) from the bus. The byte addresses of the four read commands are 0, 64, 32, and 96, respectively. These four read commands and their corresponding identifiers are stored sequentially in the CAM of the read command module. When a read command is detected in the read command module, the read transfer module sends a read operation request to the command scheduling module. When idle or after completing an operation (read, write, or refresh), the command scheduling module checks whether the read transfer module, write transfer module, and refresh module have any requests. If there are no refresh or write requests at this time, but a read operation request exists, the command scheduling module returns a response signal to the read transfer module. After receiving the response signal, the read command module begins retrieving read commands from the CAM: since address 0 is the read command with the longest storage time, address 0 is used as the starting address and initial search address for this read operation. The identifier corresponding to address 0 is retrieved from the CAM and stored in the FIFO. Next, the search address is updated to 32. A read command at address 32 exists in the CAM; its corresponding identifier is retrieved and stored in the FIFO. Then, the search is performed on address 64 in the CAM. A read command at address 64 exists in the CAM; its corresponding identifier is retrieved and stored in the FIFO. Next, the search is performed on address 96 in the CAM. A read command at address 96 exists in the CAM; its corresponding identifier is retrieved and stored in the FIFO. Finally, the search is performed on address 128 in the CAM. Since the read command at address 128 does not exist, the search ends. Then, the read transfer module sends the read commands to the UHS PSRAM according to the timing defined with the UHS PSRAM PHY, based on the order in which the read commands were retrieved from the CAM, instructing the UHS PSRAM to read the data required by the above four read commands in a single read operation. When the read data module receives data returned by the UHS PSRAM, it sequentially retrieves the corresponding identifier for each data item from the FIFO and returns the data along with its corresponding identifier to the bus. After this read operation is completed, the read transfer module generates a transfer completion signal and sends it to the command scheduling module. Upon receiving the execution completion signal, the command scheduling module considers the transfer to be finished.

[0186] Assume the UHS PSRAM controller receives four write commands and corresponding write data (each write command corresponds to 32 bytes of data) from the bus. The byte addresses of the four write commands are 0, 64, 32, and 96, respectively. These four write commands are stored sequentially in the CAM of the write command module, and the corresponding write data is stored in the dual-port RAM of the write data module. Because the UHS PSRAM controller prioritizes read operations, the write transfer module can only send a write request to the command scheduling module when any of the following conditions are met: ① The number of write commands in the CAM of the write command module reaches a threshold; ② There are write commands in the write command module, and there are no read commands in the read command module. When the command scheduling module is idle or after completing an operation (one operation refers to one read operation, one write operation, or one refresh operation), it checks whether there are any requests from the read transfer module, write transfer module, and refresh module. If there is no request from the refresh module, but there is a request from the write transfer module, it returns a response signal to the write transfer module. After receiving the response signal, the write transfer module begins retrieving write commands from the CAM of the write command module and the corresponding data from the RAM of the write data module. Since address 0 is the write command with the longest storage time, it is used as the starting address and initial lookup address for this write operation. The lookup address is then updated to 32. A write command at address 32 exists in the CAM, and the corresponding data is retrieved. Next, the module searches for address 64 in the CAM. A write command at address 64 exists in the CAM, and the corresponding data is retrieved. Then, it searches for address 96 in the CAM. A write command at address 96 exists in the CAM, and the corresponding data is retrieved. Finally, it searches for address 128 in the CAM. Since the write command at address 128 does not exist, the search ends. Then, the write transfer module sends the write commands to the UHS PSRAM according to the timing defined with the UHS PSRAM PHY, based on the order in which the write commands were read from the CAM, instructing the UHS PSRAM to write the data corresponding to the above four write commands into the UHS PSRAM in a single write operation. After this write operation is completed, the write transfer module generates a transfer completion signal and sends it to the command scheduling module. The command scheduling module considers the transmission to be complete upon receiving the execution completion signal.

[0187] against Figure 2 For other exemplary descriptions, please refer to the section on Embodiment 1. Figure 2 The exemplary descriptions provided will not be repeated in the embodiments of the present invention.

[0188] For example, the timing diagram of the interface related to the write operation of the UHS PSRAM controller is as follows: Figure 7 As shown, the timing diagram of the interface related to the UHSPSRAM controller and read operation is as follows: Figure 8As shown, hdr_clk is the main clock of the UHS PSRAM controller; phy_ce_p0~phy_ce_p3 are chip select signals. After receiving these signals, the UHS PSRAM PHY module will perform a parallel-to-serial conversion operation to obtain the / CE signal and send the / CE signal to the UHS PSRAM; phy_address[31:0] is the address or command signal. After receiving these signals, the UHS PSRAM PHY module will perform a parallel-to-serial conversion operation to obtain the part representing cmd in the DQ[7:0] signal and send the part representing cmd in the DQ[7:0] signal to the UHS PSRAM; Phy_wrdata_valid_p0~Phy_wrdata_valid_p3 are data valid signals; Phy_wrdata_p0[15:0]~Phy_wrdata_p3[15:0] are data signals. After receiving this set of signals, the PHY module performs a parallel-to-serial conversion to obtain the data portion of the DQ[7:0] signal, and sends the data portion of the DQ[7:0] signal to the UHS PSRAM. Phy_wrdata_mask_p0~Phy_wrdata_masks_p3 are data signals. After receiving this set of signals, the UHS PSRAM PHY module performs a parallel-to-serial conversion to obtain the DQM signal, and sends the DQM signal to the UHS PSRAM. Phy_last_read_p0~Phy_last_read_p4 are read last signals. If the read last signal is sent to the UHS PSRAM PHY module, it indicates that the current read operation is about to end.

[0189] Example 3

[0190] Please see Figure 9 , Figure 9 This is a schematic diagram of a read / write control device based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Figure 9 The described read / write control device based on a UHS PSRAM controller can be applied to a UHS PSRAM controller, with multiple hosts and UHS PSRAMs respectively connected to the UHS PSRAM controller. The UHS PSRAM controller may include, for example: Figure 2 The module described, Figure 2 The arrows in the diagram indicate the direction of command and / or data transmission, and the UHS PSRAM controller can be one component of the on-chip system. Figure 1 The described SOC (System on Chip) Figure 1The arrows in the diagram indicate the direction of command and / or data transmission, which is not limited in this embodiment of the invention; this read / write control device based on a UHS PSRAM controller can also be applied to devices, terminals, or systems that need to read data from and / or write data to UHS PSRAM, which is not limited in this embodiment of the invention. Figure 9 As shown, the read / write control device based on the UHS PSRAM controller may include:

[0191] The receiving module 301 is used to receive operation information sent by any host through the bus. The operation information includes at least an operation command, and the operation command type is either a read command type or a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read the corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write the corresponding data into the UHS PSRAM.

[0192] Storage module 302 is used to store operation information in the target storage space;

[0193] The sending module 303 is used to send the information corresponding to each of the operation commands to be executed from the target storage space to the UHS PSRAM according to the command reading conditions, so as to trigger the UHS PSRAM to perform the matching operation according to the information corresponding to each operation command to be executed. The type of operation command to be executed is either a read command type or a write command type.

[0194] As can be seen, the apparatus described in the embodiments of the present invention can store the operation information in the target storage space after receiving the operation information issued by the host, and send the information corresponding to the operation command to be executed read from the target storage space to the UHS PSRAM according to the command reading conditions. This can improve the efficiency and accuracy of issuing commands to the UHS PSRAM, thereby improving the efficiency of reading and writing data in the UHS PSRAM, which is conducive to meeting the reading and writing data requirements of the UHS PSRAM, and thus improving the working performance of the UHS PSRAM.

[0195] In an optional embodiment, the sending module 303 sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command reading conditions, so as to trigger the UHS PSRAM to execute the matching operation according to the information corresponding to each pending operation command. The specific method may include:

[0196] Based on the conditions determined by the command, determine the target type of the operation command to be executed;

[0197] Based on the predetermined command read control conditions, multiple operation commands to be executed, corresponding to the command read control conditions, are sequentially read from the target storage space.

[0198] Based on the target type, determine the information corresponding to each operation command to be executed;

[0199] The information corresponding to each operation command to be executed is sent to the UHS PSRAM to trigger the UHS PSRAM to execute the matching operation based on the information corresponding to each operation command to be executed.

[0200] As can be seen, the apparatus described in this optional embodiment can first determine the target type of the operation command to be executed, and then sequentially read multiple execution operation commands corresponding to the command read control conditions from the target storage space. Then, based on the target type, it determines the information corresponding to each operation command to be executed, and then sends the information corresponding to each operation command to be executed to the UHS PSRAM. This can improve the accuracy of determining the information corresponding to the operation command to be executed sent to the UHS PSRAM, thereby improving the accuracy of issuing command corresponding information to the UHS PSRAM, which is beneficial to improving the efficiency and accuracy of the UHS PSRAM in performing read and write data operations.

[0201] In this optional embodiment, the target storage space may include a first storage space corresponding to the read command type and a second storage space corresponding to the write command type.

[0202] The specific methods by which the sending module 303 determines the target type of the operation command to be executed based on the command determination conditions may include:

[0203] Determine the highest priority type among the read command types and write command types;

[0204] The target type of the operation command to be executed is determined based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type; the number of first commands corresponding to the read command type is the number of operation commands to be executed in the first storage space, and the number of second commands corresponding to the write command type is the number of operation commands to be executed in the second storage space.

[0205] The specific method by which the sending module 303 determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type may include:

[0206] When the number of pending operation commands corresponding to a high-priority type is greater than zero, the target type of the pending operation commands is determined to be a high-priority type.

[0207] or,

[0208] When the number of pending operation commands corresponding to a high-priority type is greater than zero, it is determined whether the number of pending operation commands corresponding to a low-priority type is greater than or equal to a preset number threshold. The priority of the low-priority type is lower than the priority of the high-priority type.

[0209] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is greater than or equal to the preset number threshold, the target type of the operation commands to be executed is determined as the secondary priority type.

[0210] When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is less than the preset threshold, the target type of the operation commands to be executed is determined to be a high priority type.

[0211] When the number of pending operation commands corresponding to a high-priority type is zero and the number of pending operation commands corresponding to a low-priority type is greater than zero, the target type of the pending operation command is determined to be the low-priority type.

[0212] As can be seen, the apparatus described in this optional embodiment can also determine the target type of the operation command to be executed based on the priority of the command type and the quantity corresponding to the command type. This can improve the accuracy and efficiency of determining the target type, thereby improving the efficiency of reading the operation command to be executed of the target type and improving the efficiency of UHS PSRAM executing the operation corresponding to the target type. If the quantity of high-priority operation commands to be executed is greater than zero, the target type can be directly determined as a high-priority type. Alternatively, if the quantity of low-priority operation commands to be executed is less than a threshold, the target type can be determined as a high-priority type. If the quantity of low-priority operation commands to be executed is greater than or equal to a threshold, the target type can be determined as a low-priority type. If the quantity of high-priority operation commands to be executed is zero and the quantity of low-priority operation commands to be executed is greater than zero, the target type can be determined as low-priority. This can further improve the accuracy of determining the target type and improve the efficiency of reading the operation command to be executed of the target type.

[0213] In this optional embodiment, the operation commands stored in the target storage space may have corresponding data operation addresses, which are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation address.

[0214] The specific method by which the sending module 303 sequentially reads multiple operation commands corresponding to the command read control conditions from the target storage space according to the predetermined command read control conditions may include:

[0215] Determine the lookup address;

[0216] Based on the lookup address, search the target storage space for an operation command that matches the lookup address. The data operation address of the operation command that matches the lookup address is the same as the lookup address.

[0217] When an operation command matching the lookup address is found in the target storage space, the operation command matching the lookup address is read from the target storage space.

[0218] Repeat the operation to determine the lookup address until a command matching the lookup address is found in the target storage space.

[0219] As can be seen, the apparatus described in this optional embodiment can search for an operation command to be executed that matches the determined search address in the target storage space. If an operation command to be executed that matches the search address is found, the operation command to be executed is read and the search address is redefined. Otherwise, the process of searching for the command ends. The operation command to be executed that meets the address condition can be read, thereby adjusting the order in which the operation commands to be executed in the target storage space are read and executed, improving the efficiency of reading the operation commands to be executed, and thus improving the efficiency of reading and writing data in UHS PSRAM.

[0220] In this optional embodiment, the sending module 303 may further optionally determine the specific method for finding the address as follows:

[0221] When the sending module 303 determines the lookup address for the first time, it determines the data operation address of the target operation command as the lookup address. The target operation command is the target type of operation command to be executed that has been stored in the target storage space for the longest time.

[0222] When the sending module 303 determines the search address for the first time, it determines the current search address by the sum of the previously determined search address and the data length corresponding to the target type. The data length corresponding to the target type is used to represent the data length corresponding to each operation command of the target type.

[0223] As can be seen, the apparatus described in this optional embodiment can also determine the data operation address of the target operation command as the search address when the search address is determined for the first time, and determine the current search address as the sum of the previous search address and the data length corresponding to the target type when the search address is not determined for the first time. This can improve the accuracy of determining the search address and improve the efficiency of reading multiple pending operation commands with consecutive data operation addresses, which is beneficial to improving the efficiency of reading data from or writing data to UHS PSRAM.

[0224] In this optional embodiment, the operation information stored in the first storage space may further include an identifier corresponding to each read operation command. The identifier corresponding to the read operation command is used to determine the correspondence between the read operation command and the data to be read corresponding to the read operation command.

[0225] The receiving module 301 is also configured to receive at least one read operation data returned by the UHS PSRAM when the target type is a read command type, wherein each read operation data is data read from the UHS PSRAM based on the corresponding operation command to be executed;

[0226] like Figure 10 As shown, the device may further include:

[0227] The determination module 304 is used to determine the identifier corresponding to the read operation data. The identifier corresponding to the read operation data is the identifier corresponding to the read operation command that matches the read operation data.

[0228] The return module 305 is used to return the read operation data and the corresponding identifier to the corresponding host via the bus.

[0229] As can be seen, the apparatus described in this optional embodiment can receive read operation data returned by UHS PSRAM when the target type is a read command type, and return the read operation data and the identifier corresponding to the read operation data to the corresponding host. It can match the read operation data with the read operation command one by one, which improves the accuracy and reliability of the returned read operation data and helps to improve the efficiency and accuracy of reading data from UHS PSRAM.

[0230] In another alternative embodiment, such as Figure 10 As shown, the device may further include:

[0231] Refresh module 306 is used to generate refresh commands;

[0232] The sending module 303 is also used to send the refresh command to the UHS PSRAM to trigger the UHS PSRAM to execute the refresh operation corresponding to the refresh command.

[0233] As can be seen, the apparatus described in this optional embodiment can generate refresh commands and instruct the UHS PSRAM to perform refresh operations. It can generate refresh commands suitable for the UHS PSRAM according to the clock interface frequency of the UHS PSRAM, which can reduce the probability of data loss in the UHS PSRAM, improve the reliability of the data stored in the UHS PSRAM, and help improve the data accuracy of the UHS PSRAM in performing read and write operations, thereby helping to meet the read and write data requirements of the UHS PSRAM.

[0234] Example 4

[0235] Please see Figure 11 , Figure 11 This is a schematic diagram of another read / write control device based on a UHS PSRAM controller disclosed in an embodiment of the present invention. Figure 11 As shown, the read / write control device based on the UHS PSRAM controller may include:

[0236] Memory 401 storing executable program code;

[0237] Processor 402 coupled to memory 401;

[0238] The processor 402 calls the executable program code stored in the memory 401 to execute the steps in the read / write control method based on the UHS PSRAM controller described in Embodiment 1 or Embodiment 2 of the present invention.

[0239] Example 5

[0240] This invention discloses a computer storage medium storing computer instructions. When these computer instructions are invoked, they are used to execute the steps in the read / write control method based on a UHSPSRAM controller described in Embodiment 1 or Embodiment 2 of this invention.

[0241] Example 6

[0242] This invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform the steps in the read / write control method based on a UHS PSRAM controller described in Embodiment 1 or Embodiment 2.

[0243] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0244] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0245] Finally, it should be noted that the read / write control method and apparatus based on a UHS PSRAM controller disclosed in the embodiments of the present invention are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A read-write control method based on a UHS PSRAM controller, characterized by, The method is applied in a UHS PSRAM controller, and multiple hosts and UHS PSRAMs are respectively connected to the UHS PSRAM controller. The method includes: The UHS PSRAM controller receives operation information sent by any of the hosts via the bus. The operation information includes at least an operation command, and the operation command is of one type: a read command type and a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read the corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write the corresponding data into the UHS PSRAM. The UHS PSRAM controller stores the operation information in the target storage space; The UHS PSRAM controller sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command read conditions, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each pending operation command. The type of the pending operation command is one of the read command type and the write command type.

2. The UHS PSRAM controller-based read-write control method according to claim 1, wherein, The UHSPSRAM controller, based on command read conditions, sends information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM, thereby triggering the UHS PSRAM to execute a matching operation based on the information corresponding to each pending operation command, including: The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions; The UHS PSRAM controller reads multiple operation commands to be executed from the target storage space in sequence, according to the pre-determined command read control conditions. The UHS PSRAM controller determines the information corresponding to each of the operation commands to be executed based on the target type; The UHS PSRAM controller sends information corresponding to each operation command to be executed to the UHS PSRAM, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each operation command to be executed.

3. The read-write control method based on the UHS PSRAM controller according to claim 2, wherein, The target storage space includes a first storage space corresponding to the read command type and a second storage space corresponding to the write command type; The UHS PSRAM controller determines the target type of the operation command to be executed based on the command determination conditions, including: The UHS PSRAM controller determines the read command type and the high-priority type among the write command types; The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type; the number of first commands corresponding to the read command type is the number of operation commands to be executed in the first storage space, and the number of second commands corresponding to the write command type is the number of operation commands to be executed in the second storage space. The UHS PSRAM controller determines the target type of the operation command to be executed based on the high priority type, the number of first commands corresponding to the read command type, and the number of second commands corresponding to the write command type, including: When the number of pending operation commands corresponding to the high priority type is greater than zero, the UHS PSRAM controller determines the target type of the pending operation commands as the high priority type; or, When the number of pending operation commands corresponding to the high priority type is greater than zero, the UHS PSRAM controller determines whether the number of pending operation commands corresponding to the low priority type is greater than or equal to a preset number threshold. The priority of the low priority type is lower than the priority of the high priority type. When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is greater than or equal to the preset number threshold, the UHS PSRAM controller determines the target type of the operation commands to be executed as the secondary priority type; When it is determined that the number of operation commands to be executed corresponding to the secondary priority type is less than the preset number threshold, the UHS PSRAM controller determines the target type of the operation commands to be executed as the high priority type; When the number of pending operation commands corresponding to the high priority type is zero and the number of pending operation commands corresponding to the low priority type is greater than zero, the UHS PSRAM controller determines the target type of the pending operation command as the low priority type.

4. The read-write control method based on the UHS PSRAM controller according to claim 2, wherein, The operation commands stored in the target storage space have corresponding data operation addresses, and the data operation addresses are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation addresses. The UHS PSRAM controller, based on pre-determined command read control conditions, sequentially reads multiple operation commands to be executed corresponding to the command read control conditions from the target storage space, including: The UHS PSRAM controller determines the lookup address; The UHS PSRAM controller searches the target storage space for an operation command that matches the search address, wherein the data operation address of the operation command that matches the search address is the same as the search address. When an operation command matching the lookup address is found in the target storage space, the UHS PSRAM controller reads the operation command matching the lookup address from the target storage space. The UHS PSRAM controller re-executes the operation of determining the lookup address until no matching operation command is found in the target memory space.

5. The UHS PSRAM controller-based read-write control method according to claim 3, wherein, The operation commands stored in the target storage space have corresponding data operation addresses, and the data operation addresses are used to instruct the UHS PSRAM to read or write corresponding data in the storage space corresponding to the data operation addresses. The UHS PSRAM controller, based on pre-determined command read control conditions, sequentially reads multiple operation commands to be executed corresponding to the command read control conditions from the target storage space, including: The UHS PSRAM controller determines the lookup address; The UHS PSRAM controller searches the target storage space for an operation command that matches the search address, wherein the data operation address of the operation command that matches the search address is the same as the search address. When an operation command matching the lookup address is found in the target storage space, the UHS PSRAM controller reads the operation command matching the lookup address from the target storage space. The UHS PSRAM controller re-executes the operation of determining the lookup address until no matching operation command is found in the target memory space.

6. The read / write control method based on a UHS PSRAM controller according to claim 4 or 5, characterized in that, The UHS PSRAM controller determines the lookup address, including: When the UHS PSRAM controller determines the lookup address for the first time, the UHS PSRAM controller determines the data operation address of the target operation command as the lookup address. The target operation command is the target type's pending operation command that has been stored in the target storage space for the longest time. When the UHS PSRAM controller determines the lookup address for the first time, it determines the current lookup address by summing the previously determined lookup address with the data length corresponding to the target type. The data length corresponding to the target type is used to represent the data length corresponding to each operation command of the target type.

7. The UHS PSRAM controller-based read-write control method according to claim 5, wherein, The operation information stored in the first storage space includes an identifier corresponding to each read operation command. The identifier corresponding to the read operation command is used to determine the correspondence between the read operation command and the data to be read corresponding to the read operation command. The method further includes: When the target type is the read command type, the UHS PSRAM controller receives at least one read operation data returned by the UHS PSRAM, and each read operation data is data read from the UHS PSRAM based on the corresponding operation command to be executed; The UHS PSRAM controller determines the identifier corresponding to the read operation data, and the identifier corresponding to the read operation data is the identifier corresponding to the read operation command that matches the read operation data; The UHS PSRAM controller returns the read operation data and the corresponding identifier to the corresponding host via the bus.

8. The UHS PSRAM controller based read-write control method according to claim 1, 2, 3, 4, 5 or 7, wherein, The method further includes: The UHS PSRAM controller generates a refresh command and sends the refresh command to the UHS PSRAM to trigger the UHS PSRAM to execute the refresh operation corresponding to the refresh command.

9. A read-write control device based on a UHS PSRAM controller, characterized by, The device is applied to a UHS PSRAM controller, and multiple hosts and UHS PSRAMs are respectively connected to the UHS PSRAM controller. The device includes: A receiving module is configured to receive operation information sent by any of the hosts via a bus. The operation information includes at least an operation command, and the operation command is of one type: a read command type and a write command type. The read command type operation command is used to instruct the UHS PSRAM controller to read corresponding data from the UHS PSRAM, and the write command type operation command is used to instruct the UHS PSRAM controller to write corresponding data into the UHS PSRAM. A storage module is used to store the operation information in the target storage space; The sending module is used to send information corresponding to each of the pending operation commands read from the target storage space to the UHS PSRAM according to the command reading conditions, so as to trigger the UHS PSRAM to perform a matching operation according to the information corresponding to each pending operation command. The type of the pending operation command is one of the read command type and the write command type.

10. A read-write control device based on a UHS PSRAM controller, characterized by, The device includes: Memory containing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the read / write control method based on the UHS PSRAM controller as described in any one of claims 1-8.

11. A computer storage medium, characterized in that, The computer storage medium stores computer instructions, which, when invoked, are used to execute the read / write control method based on a UHS PSRAM controller as described in any one of claims 1-8.

Images