Data processing method based on memristor array, electronic device

Abstract

This disclosure provides at least one embodiment of a data processing method and electronic device based on a memristor array. The memristor array-based data processing method includes: acquiring a plurality of first analog signals; setting up a memristor array and writing data corresponding to a parameter matrix for data processing into the memristor array; inputting the plurality of first analog signals into multiple column signal input terminals of the set memristor array respectively; controlling the memristor array to perform data processing on the plurality of first analog signals; and obtaining multiple second analog signals after data processing at multiple row signal output terminals of the memristor array respectively. This memristor array-based data processing method maps the parameter matrix corresponding to complex domain matrix-vector multiplication to the memristor array, enabling the result of complex domain matrix-vector multiplication to be obtained in a single calculation, thereby reducing the area and power consumption overhead of the auxiliary operation circuitry surrounding the memristor array.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a data processing method and electronic device based on a memristor array. Background Technology

[0002] With the advancement of science and technology and the rapid development of information technology, people can collect a large amount of data through Internet of Things (IoT) sensing technology. It is necessary to perform low-power, high-efficiency analysis and processing on this large amount of data in order to quickly extract data features and information.

[0003] Memristors (such as resistive random access memory, phase-change memory, and bridged memory) are a novel type of micro / nanoelectronic device whose conductance can be adjusted by applying external stimuli. Neuromorphic computing based on memristors breaks through the von Neumann architecture of traditional computing devices, performing computation and storage in the same location, reducing data transfer time, and requiring higher energy efficiency, lower power consumption, and smaller area for computation. Utilizing physical laws to achieve analog computation based on memristor arrays has become a hot research area in recent years. Summary of the Invention

[0004] This disclosure provides at least one embodiment of a data processing method based on a memristor array, wherein the data processing includes matrix-vector multiplication operations in the complex domain, the memristor array includes multiple memristor cells arranged in an array and configured to perform multiplication and summation operations, and the data processing method includes: acquiring multiple first analog signals; setting the memristor array and writing data corresponding to the parameter matrix of the data processing into the memristor array, wherein the complex domain matrix includes a real part matrix and an imaginary part matrix, the parameter matrix includes the real part matrix, the imaginary part matrix, and an imaginary negative matrix obtained based on the imaginary part matrix, wherein the parameter elements in the imaginary negative matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the imaginary negative matrix is ​​the negative value of the corresponding parameter element in the imaginary part matrix; inputting the multiple first analog signals into multiple column signal input terminals of the set memristor array respectively, controlling the memristor array to operate to perform the data processing on the multiple first analog signals, and obtaining multiple second analog signals after performing the data processing at multiple row signal output terminals of the memristor array respectively.

[0005] For example, in a data processing method provided in at least one embodiment of this disclosure, the memristor array includes a first subarray, a second subarray, a third subarray, and a fourth subarray. Setting up the memristor array and writing data corresponding to the parameter matrix of the data processing into the memristor array includes: mapping multiple parameter elements in the real part matrix to the first subarray and the fourth subarray in the form of the real part matrix, mapping multiple parameter elements in the imaginary part matrix to the third subarray in the form of the imaginary part matrix, and mapping multiple parameter elements in the negative imaginary part matrix to the second subarray in the form of the negative imaginary part matrix. The first subarray and the second subarray are located in the same row of the memristor array but do not overlap in the row direction; the third subarray and the fourth subarray are located in the same row of the memristor array but do not overlap in the row direction; and the first subarray and the third subarray do not overlap in the column direction.

[0006] For example, in a data processing method provided in at least one embodiment of this disclosure, the first subarray and the third subarray are located in the same column of the memristor array, and the second subarray and the fourth subarray are located in the same column of the memristor array.

[0007] For example, in the data processing method provided in at least one embodiment of this disclosure, the memristor array includes at least 2N rows and 2M columns. The first subarray includes rows i to i+N-1 and columns j to j+M-1 of the memristor array. The second subarray includes rows i to i+N-1 and columns j+k+M-1 to j+k+2M-2 of the memristor array. The third subarray includes rows i+g+N-1 to i+g+2N-2 and columns j to j+M-1 of the memristor array. The fourth subarray includes rows i+g+N-1 to i+g+2N-2 and columns j+k+M-1 to j+k+2M-2 of the memristor array. Wherein, M, N, i, j, k, and g are positive integers.

[0008] For example, in a data processing method provided in at least one embodiment of this disclosure, the real part matrix includes multiple parameter elements arranged in an array of N rows and M columns. Mapping the multiple parameter elements in the real part matrix to the first subarray and the fourth subarray in the form of the real part matrix includes: mapping N parameter elements in the same row of the real part matrix to N memristor cells in the same row of the first subarray and N memristor cells in the same row of the fourth subarray; and mapping M parameter elements in the same column of the real part matrix to M memristor cells in the same column of the first subarray and M memristor cells in the same column of the fourth subarray.

[0009] For example, in a data processing method provided in at least one embodiment of this disclosure, each of the plurality of first analog signals includes a first real part analog signal and a first imaginary part analog signal. Obtaining the plurality of first analog signals includes: obtaining a vector in the complex field for the data processing, wherein the vector in the complex field includes a real part vector and an imaginary part vector; and encoding the real part vector and the imaginary part vector respectively to obtain a plurality of first real part analog signals and a plurality of first imaginary part analog signals.

[0010] For example, in a data processing method provided in at least one embodiment of this disclosure, inputting the plurality of first analog signals into the plurality of column signal input terminals of the configured memristor array includes: inputting the plurality of first real part analog signals into the column signal input terminals of the first subarray and the third subarray respectively; and inputting the plurality of first imaginary part analog signals into the column signal input terminals of the second subarray and the fourth subarray respectively.

[0011] For example, in the data processing method provided in at least one embodiment of this disclosure, each of the plurality of second analog signals includes a second real part analog signal and a second imaginary part analog signal. The first subarray and the second subarray share the same row signal output terminal, and the third subarray and the fourth subarray share the same row signal output terminal. The plurality of second analog signals after performing the data processing are obtained at the plurality of row signal output terminals of the memristor array, including: obtaining a plurality of second real part analog signals based on the current signal output from the row signal output terminal of the first subarray; and obtaining a plurality of second real part imaginary part signals based on the current signal output from the row signal output terminal of the second subarray.

[0012] For example, at least one embodiment of the data processing method provided in this disclosure further includes: performing analog-to-digital conversion on the plurality of second real part analog signals to obtain the real part operation result of the matrix-vector multiplication operation; and performing analog-to-digital conversion on the plurality of second imaginary part analog signals to obtain the imaginary part operation result of the matrix-vector multiplication operation.

[0013] For example, in the data processing method provided in at least one embodiment of this disclosure, the parameter matrix is ​​represented as follows:

[0014]

[0015] Among them, W real Let W be the real part matrix. img Let W be the imaginary part matrix. img Let be the negative imaginary part matrix.

[0016] For example, in a data processing method provided in at least one embodiment of this disclosure, the parameter matrix includes P rows and Q columns. The parameter element in the m-th row and n-th column of the parameter matrix is ​​jointly represented by the parameter element in the m-th row and n-th column of the first sub-matrix and the parameter element in the m-th row and n-th column of the second sub-matrix. m, n, P, and Q are positive integers. The first sub-matrix includes P rows of first parameter elements, and the second sub-matrix includes P rows of second parameter elements. The row and column positions of the P-th row of first parameter elements and the P-th row of second parameter elements correspond one-to-one. The first sub-matrix and the second sub-matrix are arranged in a first matrix form of 2P rows and Q columns. Setting up the memristor array and writing the data corresponding to the parameter matrix of the data processing into the memristor array includes: mapping the first sub-matrix and the second sub-matrix to the memristor array according to the first matrix form.

[0017] For example, in a data processing method provided in at least one embodiment of this disclosure, multiple second analog signals after performing the data processing are obtained at multiple row signal output terminals of the memristor array, including: determining at least one set of rows to be processed, wherein each set of the at least one set of rows to be processed includes a row of target memristor units corresponding to a row of the first parameter elements of the P rows, and a row of target memristor units corresponding to a row of the second parameter elements of the P rows corresponding to a row of the first parameter elements of the P rows; performing current preprocessing on the current signals of two of the multiple row signal output terminals corresponding to the two rows of target memristor units included in each set of the at least one set of rows to be processed, so as to obtain the multiple second analog signals corresponding to each set of the at least one set of rows to be processed.

[0018] For example, in a data processing method provided in at least one embodiment of this disclosure, the memristor array includes a first memristor array and a second memristor array. The parameter element in the u-th row and v-th column of the parameter matrix is ​​jointly represented by the parameter element in the u-th row and v-th column of the first sub-matrix and the parameter element in the u-th row and v-th column of the second sub-matrix, where u and v are positive integers. The first sub-matrix and the second sub-matrix both have the same matrix form as the parameter matrix. Setting the memristor array and writing the data corresponding to the parameter matrix of the data processing into the memristor array includes: mapping the first sub-matrix to the first memristor array in the form of the parameter matrix, and mapping the second sub-matrix to the second memristor array in the form of the parameter matrix.

[0019] For example, in a data processing method provided in at least one embodiment of this disclosure, multiple second analog signals after performing the data processing are obtained at multiple row signal output terminals of the memristor array, including: performing current preprocessing on the current signal of each of the multiple row signal output terminals in the first memristor array and the current signal of each of the corresponding multiple row signal output terminals in the second memristor array to obtain the multiple second analog signals.

[0020] For example, in the data processing method provided in at least one embodiment of this disclosure, the current preprocessing is current subtraction processing or current addition processing.

[0021] For example, in the data processing method provided in at least one embodiment of this disclosure, the data processing is a discrete Fourier transform, the matrix in the complex field is the coefficient matrix of the discrete Fourier transform, the real part matrix is ​​the real part of the coefficient matrix, and the imaginary part matrix is ​​the imaginary part of the coefficient matrix.

[0022] For example, at least one embodiment of this disclosure provides an electronic device, including: a memristor array configured to perform multiplication and summation operations; a signal acquisition device configured to acquire a plurality of first analog signals; and a control driving circuit, wherein the control driving circuit is configured to perform the following steps: setting the memristor array, writing data corresponding to the parameter matrix of the data processing into the memristor array, wherein the matrix in the complex field includes a real part matrix and an imaginary part matrix, the parameter matrix includes the real part matrix, the imaginary part matrix, and an imaginary negative matrix obtained based on the imaginary part matrix, wherein the parameter elements in the imaginary negative matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the imaginary negative matrix is ​​the negative value of the corresponding parameter element in the imaginary part matrix; inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array respectively, controlling the memristor array to operate to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array respectively.

[0023] For example, in an electronic device provided in at least one embodiment of this disclosure, the memristor array includes a first subarray, a second subarray, a third subarray, and a fourth subarray. When the control driving circuit executes the setting of the memristor array and writes data corresponding to the parameter matrix of the data processing into the memristor array, it includes performing the following steps: mapping multiple parameter elements in the real part matrix to the first subarray and the fourth subarray respectively in the form of the real part matrix; mapping multiple parameter elements in the imaginary part matrix to the third subarray in the form of the imaginary part matrix; and mapping multiple parameter elements in the negative imaginary part matrix to the second subarray in the form of the negative imaginary part matrix. The first subarray and the second subarray are located in the same row of the memristor array but do not overlap in the row direction; the third subarray and the fourth subarray are located in the same row of the memristor array but do not overlap in the row direction; and the first subarray and the third subarray do not overlap in the column direction. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0025] Figure 1 A method for implementing DFT based on memristor arrays is shown;

[0026] Figure 2 A schematic structure of a memristor array is shown;

[0027] Figure 3A A schematic diagram of a memristor unit with a 1T1R structure;

[0028] Figure 3B A schematic diagram of a memristor unit with a 2T2R structure;

[0029] Figure 4 A schematic flowchart illustrating a data processing method based on a memristor array, provided for at least one embodiment of this disclosure;

[0030] Figure 5 A schematic diagram illustrating the implementation principle of a memristor array, provided for at least one embodiment of this disclosure;

[0031] Figure 6 A schematic diagram of a memristor array for data processing provided for at least one embodiment of this disclosure;

[0032] Figure 7A A schematic diagram of a heatmap of real part matrix elements provided for at least one embodiment of this disclosure;

[0033] Figure 7B A schematic diagram of a heatmap of an imaginary matrix element provided for at least one embodiment of this disclosure;

[0034] Figure 7C A schematic diagram of a heatmap of parameter matrix elements provided in at least one embodiment of this disclosure;

[0035] Figure 8 A schematic diagram of a memristor array after writing a parameter matrix, provided for at least one embodiment of this disclosure;

[0036] Figure 9 A schematic diagram of another memristor array after writing a parameter matrix, provided for at least one embodiment of this disclosure;

[0037] Figure 10A A schematic diagram of a conductance mapping heatmap of a first submatrix provided for at least one embodiment of this disclosure;

[0038] Figure 10B A schematic diagram of a conductance mapping matrix heatmap of a second submatrix provided in at least one embodiment of this disclosure;

[0039] Figure 11A A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0040] Figure 11B A schematic diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0041] Figure 11CA schematic diagram of another electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0045] The Discrete Fourier Transform (DFT) is a commonly used signal processing algorithm that transforms a signal from the time domain to the frequency domain. The DFT can be defined by the following formula:

[0046]

[0047] In formula (1), x[a] is a complex number representing the time-domain sampling of the input signal; y[b] is a complex number representing the frequency-domain sampling of the output signal; N is a real number representing the length of the signal segment; and i is the imaginary unit.

[0048] For example, the above DFT calculation formula can be rewritten as:

[0049] y = Wx = y real +iy img =(W real x real -W img x img )+i(W real x img +W img x real ) Formula (2)

[0050] In formula (2), the output signal y = y real +iy img It is the frequency domain sampling vector of the signal, and the input signal is x = x real +ix img It is the time-domain sampled vector of the signal, W = W real +iW img W is the coefficient matrix of the discrete Fourier transform. real and W img These are the real part and the imaginary part of W, respectively.

[0051] For example, W real and W img This can be expressed by formulas (3) and (4) respectively:

[0052]

[0053]

[0054] In formulas (3) and (4), 2π00 represents 2×π×0×0=0, 2π(N-1)0 represents 2×π×(N-1)×0=0, 2π(N-1)(N-1) represents 2×π×(N-1)×(N-1), and so on.

[0055] Figure 1 A method for implementing DFT based on a memristor array is shown. For example... Figure 1 As shown, this scheme mainly utilizes the characteristic of memristors to perform vector-matrix multiplication, using the conductance matrices of two memristor arrays to map the real part W of the DFT matrix respectively. real And the imaginary part W img The real part Re(x) of the input signal (i.e., x in formula (2)) real ) and the imaginary part Im(x) (i.e., x in formula (2) img Re(W) can be obtained by representing each voltage pulse with the corresponding pulse and applying them to the array. + (i.e., W in formula (2)) real xreal ), Re(W) - (i.e., W in formula (2)) img x img ), Im(W) + (i.e., W in formula (2)) real x img ) and Im(W) - (i.e., W in formula (2)) img x real The four intermediate results (intermediate terms) are processed by operational amplifiers and other circuits outside the array to perform addition and subtraction functions, and finally the real part Re(X) of the DFT calculation result is obtained (i.e., y in formula (2)). real ) and the imaginary part Im(X) (i.e., y in formula (2) img This allows us to obtain the complete DFT calculation results.

[0056] In the aforementioned DFT implementation method based on memristor arrays, besides the memristor array itself performing vector-matrix multiplication, external auxiliary operational circuits are also required to perform addition and subtraction operations for each term. However, operational amplifiers and other auxiliary operational circuits incur significant area overhead. If each output corresponds to two operational amplifiers (one for W...),... real x real -W img x img Subtraction in W real x img + W img x real If the addition is used, then for an N (e.g., 64, 128) point DFT, 2×N (e.g., 128, 256) op-amps are needed, thus increasing the additional circuit area and computational power consumption overhead.

[0057] This disclosure provides at least one embodiment of a data processing method and electronic device based on a memristor array. The data processing method includes: acquiring a plurality of first analog signals; setting up a memristor array and writing data corresponding to a parameter matrix for data processing into the memristor array, wherein the complex-domain matrix includes a real part matrix and an imaginary part matrix, the parameter matrix includes a real part matrix, an imaginary part matrix, and a negative imaginary part matrix obtained based on the imaginary part matrix, wherein the parameter elements in the negative imaginary part matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the negative imaginary part matrix is ​​the negative value of the corresponding parameter element in the imaginary part matrix; inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array respectively, controlling the memristor array to perform data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after data processing at a plurality of row signal output terminals of the memristor array respectively.

[0058] This data processing method based on memristor arrays modifies the formula for complex domain matrix-vector multiplication to obtain the corresponding parameter matrix. By mapping this parameter matrix to the memristor array, the result of complex domain matrix-vector multiplication can be obtained in a single calculation, thereby reducing the area and power consumption of the auxiliary operation circuits around the memristor array.

[0059] At least one embodiment of this disclosure also provides an electronic device corresponding to the memristor array-based data processing method.

[0060] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0061] Figure 2 A schematic structure of a memristor array is shown, consisting of multiple memristor cells arranged in an r-row, s-column array, where r and s are positive integers. Each memristor cell includes a switching element and one or more memristors. Figure 1 In the middle, WL <1> WL <2> ...WL <r>These represent the word lines of the first row, second row, ..., rth row, respectively. The control electrode (e.g., the gate of a transistor) of the switching element in the memristor cell of each row is connected to the corresponding word line of that row; BL <1> BL <2> BL <s>These represent the bit lines of the first column, second column, ..., s-th column, respectively. The memristor in each column's memristor cell is connected to the corresponding bit line of that column; SL <1> SL <2> ……SL <r>These represent the source lines of the first, second, ..., rth rows, respectively. The source of the transistor in each row of memristor cells is connected to the corresponding source line of that row. According to Kirchhoff's laws, by setting the state of the memristor cells (e.g., resistance or conductance) and applying corresponding word line and bit line signals, the above memristor array can perform multiplication and accumulation calculations in parallel.

[0062] Figure 2 The memristor cells in the memristor array can have, for example, a 1T1R structure or a 2T2R structure. A 1T1R structure memristor cell includes one transistor and one memristor, while a 2T2R structure memristor cell includes two transistors and two memristors. It should be noted that this disclosure does not limit the structure of the memristor cells; other structures capable of implementing multiplication-accumulation-addition operations can also be used.

[0063] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors or field-effect transistors (e.g., MOS field-effect transistors) or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, in order to distinguish the two poles of the transistor other than the gate (i.e., the source and drain), one of them is directly described as the first pole, and the other as the second pole.

[0064] Figure 3A This is a schematic diagram of a 1T1R memristor unit. Figure 3A As shown, the memristor cell of the 1T1R structure includes a transistor M1 and a memristor R1.

[0065] The embodiments of this disclosure do not limit the type of transistor used. For example, when transistor M1 is an N-type transistor, its gate is connected to the word line WL. For example, transistor M1 is turned on when the word line WL inputs a high level. The first terminal of transistor M1 can be the source and is configured to be connected to the source line SL. For example, transistor M1 can receive a reset voltage through the source line SL. The second terminal of transistor M1 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of memristor R1. The first terminal (e.g., the positive terminal) of memristor R1 is connected to the bit line BL. For example, memristor R1 can receive a set voltage through the bit line BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line WL. For instance, transistor M1 is turned on when the word line WL inputs a low level. The first terminal of transistor M1 can be the drain and configured to be connected to the source line SL. For instance, transistor M1 can receive a reset voltage through the source line SL. The second terminal of transistor M1 can be the source and configured to be connected to the second terminal (e.g., the negative terminal) of memristor R1. The first terminal (e.g., the positive terminal) of memristor R1 is connected to the bit line BL. For instance, memristor R1 can receive a set voltage through the bit line BL. It should be noted that the memristor structure can also be implemented in other ways, such as the structure where the second terminal of memristor R1 is connected to the source line SL. The embodiments disclosed herein do not limit this.

[0066] The following embodiments are all illustrated using an N-type transistor as an example.

[0067] The word line terminal WL applies a voltage to the gate of transistor M1, thereby controlling its on or off state. When operating memristor R1, such as performing a set or reset operation, transistor M1 must first be turned on; that is, a turn-on voltage must be applied to the gate of transistor M1 through the word line terminal WL. After transistor M1 is turned on, for example, voltages can be applied to memristor R1 through the source line terminal SL and the bit line terminal BL to change its resistance state. For example, a set voltage can be applied through the bit line terminal BL to put memristor R1 in a low-resistance state; or a reset voltage can be applied through the source line terminal SL to put memristor R1 in a high-resistance state. For example, the resistance value in the high-resistance state is more than 100 times, or even more than 1000 times, the resistance value in the low-resistance state.

[0068] It should be noted that, in the embodiments of this disclosure, by simultaneously applying voltage to the word line terminal WL and the bit line terminal BL, the resistance value of memristor R1 can be made smaller and smaller, that is, memristor R1 changes from a high resistance state to a low resistance state. This operation of changing memristor R1 from a high resistance state to a low resistance state is called a set operation. Conversely, by simultaneously applying voltage to the word line terminal WL and the source line terminal SL, the resistance value of memristor R1 can be made larger and larger, that is, memristor R1 changes from a low resistance state to a high resistance state. This operation of changing memristor R1 from a low resistance state to a high resistance state is called a reset operation. For example, memristor R1 has a threshold voltage. When the input voltage amplitude is less than the threshold voltage of memristor R1, the resistance value (or conductance value) of memristor R1 will not change. In this case, calculations can be performed using the resistance value (or conductance value) of memristor R1 by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of memristor R1 can be changed by inputting a voltage greater than the threshold voltage.

[0069] Figure 3B This is a schematic diagram of a memristor cell with a 2T2R structure. (See diagram below.) Figure 3B As shown, the 2T2R structure memristor unit includes two transistors M1 and M2 and two memristors R1 and R2. The following explanation takes the example where both transistors M1 and M2 are N-type transistors.

[0070] The gate of transistor M1 is connected to the word line terminal WL1. For example, when the word line terminal WL1 of M1 is high, transistor M1 is turned on. The gate of transistor M2 is connected to the word line terminal WL2. For example, when the word line terminal WL2 of M2 is high, transistor M2 is turned on. The first terminal of transistor M1 can be the source and is configured to be connected to the source line terminal SL. For example, transistor M1 can receive a reset voltage through the source line terminal SL. The first terminal of transistor M2 can be the source and is configured to be connected to the source line terminal SL. For example, transistor M2 can receive a reset voltage through the source line terminal SL. The first terminals of transistors M1 and M2 are connected together and connected to the source line terminal SL. The second terminal of transistor M1 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of memristor R1. The first terminal (e.g., the positive terminal) of memristor R1 is connected to the bit line terminal BL1. For example, memristor R1 can receive the set voltage through the bit line terminal BL1. The second terminal of transistor M2 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of memristor R2. The first terminal (e.g., the positive terminal) of memristor R2 is connected to the bit line terminal BL2. For example, memristor R2 can receive the set voltage through the bit line terminal BL2.

[0071] It should be noted that transistors M1 and M2 in the 2T2R memristor unit can also both be P-type transistors, which will not be elaborated here.

[0072] Figure 4 This is a schematic flowchart illustrating a data processing method based on a memristor array, provided for at least one embodiment of the present disclosure.

[0073] For example, such as Figure 4 As shown, the data processing method based on a memristor array provided in this embodiment includes steps S110 to S130. The memristor array includes multiple memristor units arranged in an array and configured to perform multiplication and summation operations (i.e., multiplication and summation operations, where the product of multiplications is accumulated to obtain the sum of the multiplication and summation results). For example, a schematic diagram of the memristor array is shown below. Figure 2 As shown, each memristor unit can be as follows: Figure 3A The 1T1R structure shown or as... Figure 3B The 2T2R structure is shown.

[0074] In step S110, multiple first analog signals are acquired.

[0075] In step S120, a memristor array is set up, and the data corresponding to the parameter matrix of data processing is written into the memristor array.

[0076] For example, a matrix in the complex field includes a real part matrix and an imaginary part matrix, and a parameter matrix includes a real part matrix, an imaginary part matrix, and an imaginary negative matrix obtained based on the imaginary part matrix.

[0077] For example, the parameter elements in the negative imaginary part matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the negative imaginary part matrix is ​​the negative of the corresponding parameter element in the imaginary part matrix. For instance, the negative imaginary part matrix is ​​obtained by taking the negative value of each parameter element in the imaginary part matrix.

[0078] In step S130, multiple first analog signals are input to multiple column signal input terminals of the configured memristor array to control the operation of the memristor array to perform data processing on the multiple first analog signals, and multiple second analog signals after data processing are obtained at multiple row signal output terminals of the memristor array.

[0079] For example, multiple first analog signals are input signals to be processed, and multiple second analog signals are output signals after data processing of the input signals.

[0080] For example, the first analog signal is an analog voltage signal, and the second analog signal is an analog current signal.

[0081] For example, each first analog signal may include a first real analog signal and a first imaginary analog signal, and each second analog signal may include a second real analog signal and a second imaginary analog signal.

[0082] For example, in some cases, the formula for calculating matrix-vector multiplication in the complex field can be expressed in the following form:

[0083] y t =W t x t Formula (5)

[0084]

[0085] y t =[y real ,y img ] T Formula (7)

[0086] x t =[x real ,x img ] T Formula (8)

[0087] For example, formula (5) above is the expression of the calculation formula for complex field matrix-vector multiplication; in formula (6) above, W t W is the parameter matrix used for data processing. real W is the real part matrix. img For the imaginary part matrix, -W img y is the imaginary negative matrix; in the above formula (7), y t This is the result of a matrix-vector multiplication operation, which includes the real part y. real The result of the operation of the imaginary part y img In the above formula (8), x t A vector in the complex field used for data processing, including the real part vector x. real and the imaginary part vector x img .

[0088] For example, in step S110, acquiring the plurality of first analog signals may include: acquiring a vector x in the complex domain for data processing. t , where the vector x in the complex field t Including the real part vector x real and the imaginary part vector x img ; for the real part vector x respectively real and the imaginary part vector x img Encoding processing is performed to obtain multiple first real part analog signals and multiple first imaginary part analog signals.

[0089] For example, the vector x in the complex field is processed through encoding. t Encode it into a voltage pulse vector, that is, the real part vector x. real and the imaginary part vector x img Each parameter element in the vector is encoded into a corresponding voltage pulse, thereby obtaining the real part vector x. real The first real part of the analog signal and the imaginary part vector x corresponding to each parameter element in the equation. real The first imaginary part of the analog signal corresponding to each parameter element.

[0090] For example, the encoding process includes digital-to-analog conversion. During the encoding process, the number of pulses can be used to encode the parameter elements, or the pulse amplitude can be used to encode the parameter elements. This disclosure does not limit the specific process of the encoding process.

[0091] For example, a vector x in the complex field used for data processing t It can be a digital signal of length N, i.e., the real part vector x. real The real part of the digital signal and the imaginary part vector x img This is the imaginary part of the digital signal.

[0092] For example, the digital signal can be a pre-stored digital signal; or it can be a digital signal acquired in real time. The digital signal is then converted from digital to analog to obtain multiple first analog signals.

[0093] For example, a memristor array may include a first subarray, a second subarray, a third subarray, and a fourth subarray.

[0094] For example, step S120 may include: mapping multiple parameter elements in the real part matrix to the first subarray and the fourth subarray in the form of the real part matrix, mapping multiple parameter elements in the imaginary part matrix to the third subarray in the form of the imaginary part matrix, and mapping multiple parameter elements in the negative imaginary part matrix to the second subarray in the form of the negative imaginary part matrix, wherein the first subarray and the second subarray are located in the same row of the memristor array but do not overlap in the row direction, the third subarray and the fourth subarray are located in the same row of the memristor array but do not overlap in the row direction, and the first subarray and the third subarray do not overlap in the column direction.

[0095] For example, the first and third subarrays are located in the same column of the memristor array, and the second and fourth subarrays are located in the same column of the memristor array.

[0096] For example, in some embodiments, the first subarray and the third subarray are located in different columns of the memristor array, and the second subarray and the fourth subarray are located in different columns of the memristor array. For example, memristor array G t It can be represented as G t = [G1,G2,O3,O4; O1,O2,G3,G4], where G1 is the first subarray, G2 is the second subarray, G3 is the third subarray, and G4 is the fourth subarray. The memristors in O1, O2, O3, and O4 are in their unmapped initial state. For example, when the memristor is in its unmapped initial state, the memristor conductance is close to 0.

[0097] Figure 5 This is a schematic diagram illustrating the implementation principle of a memristor array, provided for at least one embodiment of this disclosure.

[0098] For example, such as Figure 5 As shown, based on the forms of formulas (5) to (8), complex field matrix-vector multiplication can be implemented by a memristor array, that is, W is represented by a memristor array. real -W img W real and W img The parameter matrix W is composed of t .

[0099] For example, the real part vector x real The corresponding multiple first real part analog signals are input to W in the memristor array real and W img In the middle, the imaginary part vector x img The corresponding multiple first imaginary part analog signals are input into the memristor array in the -W img and W real Thus, the result of the real part operation, y, is obtained. real The result of the operation of the imaginary part y img .

[0100] This method directly represents the imaginary negative matrix -W using a portion of the memristor array. img Furthermore, by directly performing multiplication and addition calculations on the memristor array using Kirchhoff's current law, the overhead of operational amplifiers and other processing circuits that perform addition and subtraction on intermediate results outside the memristor array is reduced. This allows all the results of matrix-vector multiplication in the complex field to be obtained in a single operation, improving computational efficiency, reducing circuit overhead, and saving circuit area.

[0101] Figure 6 This is a schematic diagram of a memristor array for data processing, provided for at least one embodiment of the present disclosure.

[0102] For example, such as Figure 6 As shown, the memristor array consists of at least 2N rows and 2M columns, where M and N are both positive integers.

[0103] For example, such as Figure 6 As shown, the memristor array may include a first subarray, a second subarray, a third subarray, and a fourth subarray.

[0104] For example, such as Figure 6 As shown, SL SL<i+1> ……SL<i+N-1> These represent the source lines of row i, row i+1, ..., row i+N-1, respectively. The sources of the transistors in the first and second subarrays are connected to the source lines of row i, row i+1, ..., row i+N-1; SL<i+g+N-1> SL<i+g+N> ……SL<i+g+2N-2> These represent the source lines of rows i+g+N-1, i+g+N, ..., i+g+2N-2, respectively. The sources of the transistors in the third and fourth subarrays are connected to the source lines of rows i+g+N-1, i+g+N, ..., i+g+2N-2.

[0105] For example, BL <j>BL<j+1> BL<j+M-1> These represent the bit lines of column j, column j+1, ..., column j+M-1, respectively. The memristors in the memristor cells of the first and third subarrays are connected to the bit lines of column j, column j+1, ..., column j+M-1; BL<j+k+M-1> BL<j+k+M> BL<j+k+2M-2> These represent the bit lines of columns j+k+M-1, j+k+M, ..., j+k+2M-2, respectively. The memristors in the memristor cells of the second and fourth subarrays are connected to the bit lines of columns j+k+M-1, j+k+M, ..., j+k+2M-2. Here, i, j, k, and g are positive integers.

[0106] For example, the first subarray and the second subarray can be located in the same row of the memristor array but do not overlap in the row direction. For example, the first subarray includes the i-th row to the (i+N-1)-th row and the j-th column to the (j+M-1)-th column of the memristor array, that is, the first subarray G1 = [G ij …G i(j+M-1) ;…;G (i+N-1)j …G (i+N-1)(j+M-1) The second subarray comprises rows i to i+N-1 and columns j+k+M-1 to j+k+2M-2 of the memristor array, i.e., the second subarray G2 = [G i(j+k+M-1) …G i(j+k+2M-2) ;…;G (i+N-1)(j+k+M-1) …G (i+N-1)(j+k+2M-2) ].

[0107] For example, the third and fourth subarrays can be located in the same row of the memristor array but do not overlap in the row direction, and the first and third subarrays do not overlap in the column direction. For example, the third subarray includes rows i+g+N-1 to i+g+2N-2 and columns j to j+M-1 of the memristor array, i.e., the third subarray G3 = [G (i+g+N-1)j …G (i+g+N-1)(j+M-1) ;…;G (i+g+2N-2)j …G (i+g+2N-2)(j+M-1) The fourth subarray comprises rows i+g+N-1 to i+g+2N-2 and columns j+k+M-1 to j+k+2M-2 of the memristor array, i.e., the fourth subarray G4 = [G (i+g+N-1)(j+k+M-1) …G (i+g+N-1)(j+k+2M-2) ;…;G (i+g+2N-2)(j+k+M-1) …G (i+g+2N-2)(j+k+2M-2) ].

[0108] It should be noted that, for example, the DFT in formula (1) has a signal segment length of N. According to formulas (3), (4), and (6), the parameter matrix W corresponding to this DFT for data processing is... t It consists of 2N rows and 2N columns. Therefore, the parameter matrix W corresponding to this DFT is... t For example after mapping Figure 6 The memristor array shown also consists of 2N rows and 2N columns, where M equals N. M and N are positive integers.

[0109] For example, the real part matrix includes multiple parameter elements arranged in an array of N rows and M columns. Mapping these multiple parameter elements in the real part matrix to the first and fourth subarrays in the form of the real part matrix includes: mapping the N parameter elements in the same row of the real part matrix to N memristor cells in the same row of the first subarray and N memristor cells in the same row of the fourth subarray; and mapping the M parameter elements in the same column of the real part matrix to M memristor cells in the same column of the first subarray and M memristor cells in the same column of the fourth subarray.

[0110] For example, the imaginary part matrix includes multiple parameter elements arranged in an array of N rows and M columns. Mapping the multiple parameter elements in the imaginary part matrix to the third subarray in the form of the imaginary part matrix includes: mapping the N parameter elements in the same row of the imaginary part matrix to N memristor cells in the same row of the third subarray, and mapping the M parameter elements in the same column of the imaginary part matrix to M memristor cells in the same column of the third subarray.

[0111] For example, the imaginary negative matrix includes multiple parameter elements arranged in an array of N rows and M columns. Mapping the parameter elements in the imaginary negative matrix to the second subarray in the form of the imaginary negative matrix includes: mapping the N parameter elements in the same row of the imaginary negative matrix to N memristor cells in the same row of the second subarray, and mapping the M parameter elements in the same column of the imaginary negative matrix to M memristor cells in the same column of the second subarray.

[0112] For example, each memristor unit can be a 1T1R structure, such as... Figure 3A As shown, each memristor unit includes one memristor, and the conductance value of the memristor represents the corresponding parameter element.

[0113] For example, each memristor unit can be a 2T2R structure, such as... Figure 3B As shown, each memristor unit includes two memristors, and the conductance values ​​of the two memristors can be used to realize the negative values ​​of the parameter elements. Thus, more complex data processing can be achieved by using multiple memristor units.

[0114] For example, in step S130, inputting multiple first analog signals into multiple column signal input terminals of the configured memristor array includes: inputting multiple first real part analog signals into the column signal input terminals of the first subarray and the third subarray; and inputting multiple first imaginary part analog signals into the column signal input terminals of the second subarray and the fourth subarray.

[0115] For example, the first subarray and the third subarray share the same column signal input terminal and jointly receive signals based on the real part vector x. real Multiple analog signals with the first real part are obtained. For example, the second and fourth subarrays share the same column signal input terminals and jointly receive signals based on the imaginary part vector x. img The resulting multiple analog signals with the first imaginary part.

[0116] For example, the first subarray and the third subarray can also not share the same column signal input terminals, and multiple first real part analog signals can be input into the first subarray and the third subarray respectively through different column signal input terminals. Similarly, the second subarray and the fourth subarray can also not share the same column signal input terminals, and multiple first real part analog signals can be input into the second subarray and the fourth subarray respectively through different column signal input terminals.

[0117] For step S130, for example, multiple first analog signals can be applied to multiple column signal input terminals of the configured memristor array, while an enable signal is applied to multiple signal control terminals of the memristor array, multiple current signals of multiple row signal output terminals of the memristor array are detected and acquired, and multiple second analog signals are obtained based on the multiple current signals.

[0118] For example, such as Figure 6 As shown, the first real part analog signal V is input to multiple column signal input terminals of the bit lines in the j-th column, the (j+1)-th column, ..., the (j+M-1)-th column. j V j+1 ...V j+M-1 The first imaginary part analog signal V is input to multiple column signal input terminals of the bit lines in columns j+k+M-1, j+k+M, ..., j+k+2M-2. j+k+M-1 V j+k+M ...V j+k+2M-2 After calculation and processing by the memristor cells in the first, second, third, and fourth subarrays, the second real part analog signal I is output at the row signal output terminal of the source lines in the i-th row, i+1-th row...i+N-1-th row. i I i+1 ...I i+N-1 The second imaginary part analog signal I is output at the row signal output terminal of the source line in row i+g+N-1, row i+g+N, ..., row i+g+2N-2. i+g+N-1 I i+g+N ...I i+g+2N-2 .

[0119] For example, in step S130, obtaining multiple second analog signals after data processing at multiple row signal output terminals of the memristor array may include: obtaining multiple second real part analog signals based on the current signals output from the row signal output terminals of the first subarray; and obtaining multiple second real part imaginary part signals based on the current signals output from the row signal output terminals of the second subarray.

[0120] For example, the data processing method based on a memristor array provided in at least one embodiment of this disclosure may further include: performing analog-to-digital conversion processing on a plurality of second analog signals to convert the plurality of second analog signals into a plurality of digital signals for subsequent processing.

[0121] For example, multiple analog signals with second real parts can be processed by analog-to-digital conversion to obtain the real part operation result of matrix-vector multiplication in the complex field, that is, the real part operation result y in formula (7). real ; Perform analog-to-digital conversion on multiple second imaginary part analog signals to obtain the imaginary part operation result of matrix-vector multiplication in the complex field, that is, the imaginary part operation result y in formula (7). img .

[0122] The following section uses matrix-vector multiplication in the complex field as an example of discrete Fourier transform to describe and illustrate the mapping relationship between the parameter matrix and the memristor.

[0123] Figure 7A A schematic diagram of a heatmap of a real part matrix provided for at least one embodiment of this disclosure;

[0124] Figure 7B A schematic diagram of a heatmap of an imaginary part matrix provided for at least one embodiment of this disclosure; Figure 7C This is a schematic diagram of a heat map of a parameter matrix provided in at least one embodiment of the present disclosure.

[0125] For example, such as Figure 7A , Figure 7B and Figure 7C The horizontal and vertical axes in the heatmap shown represent the length of the signal segment. Each point, determined by the horizontal and vertical axes, represents the parameter element at the corresponding position in the matrix. The rectangular gradient color bar on the right side of the figure represents the value of the parameter element at different positions in the cloud map. Different values ​​correspond to different grayscale values, ranging from -1 to 1.

[0126] For example, the matrix in the complex field can be the coefficient matrix of the Discrete Fourier Transform. Refer to formulas (1) to (4) for the definition and expression of the coefficient matrix. Taking a signal segment length N = 128 as an example, the real part matrix W of the DFT is calculated according to formulas (3) and (4). real And the imaginary part matrix W img Therefore, we can obtain the following: Figure 7A The real part matrix W is shown below. real Heatmaps, and such Figure 7B The image shows the imaginary part matrix W. img A heatmap. For example, the imaginary matrix W. img The negative imaginary part matrix -W is obtained by taking the negative value of each parameter element in the matrix. img The real part of the matrix W real The imaginary matrix W img And the imaginary negative matrix -W img The parameter matrix W of the DFT is obtained by arranging the parameters according to formula (6). t Therefore, we can obtain the following: Figure 7C The parameter matrix W is shown below. t Heat map.

[0127] For example, the value of a parameter element may be positive or negative. For example, each parameter element can be represented by the conductance values ​​of two memristors. For example, the difference between the conductance values ​​of two memristors can be used to represent a parameter element, or the sum of the conductance values ​​of two memristors can be used to represent a parameter element.

[0128] For example, a parameter matrix can be represented by both a first submatrix and a second submatrix. For instance, a parameter matrix may have P rows and Q columns, where the parameter element in the m-th row and n-th column is represented by the parameter element in the m-th row and n-th column of both the first and second submatrix, where m, n, P, and Q are positive integers. In other words, the parameter element in the m-th row and n-th column of the parameter matrix is ​​the sum or difference of the parameter elements in the m-th row and n-th column of both the first and second submatrix.

[0129] For example, the first submatrix includes P rows of first parameter elements, and the second submatrix includes P rows of second parameter elements. The row and column positions of the P rows of first parameter elements and P rows of second parameter elements correspond one-to-one. The first and second submatrixes are arranged in a first matrix form of 2P rows and Q columns. For example, the first and second submatrixes have the same matrix form as the aforementioned parameter matrices.

[0130] For example, step S120 may include mapping the first submatrix and the second submatrix to the memristor array in the form of a first matrix.

[0131] At this point, step S130, for example, obtaining multiple second analog signals after data processing at multiple row signal output terminals of the memristor array, may include: determining at least one set of rows to be processed, wherein each set of at least one set of rows to be processed includes a row of target memristor units corresponding to a row of first parameter elements in row P, and a row of target memristor units corresponding to a row of second parameter elements in row P corresponding to a row of first parameter elements in row P; performing current preprocessing on the current signals of two of the multiple row signal output terminals corresponding to the two rows of target memristor units included in each set of at least one set of rows to be processed, so as to obtain multiple second analog signals corresponding to each set of at least one set of rows to be processed.

[0132] For example, current preprocessing can be either current subtraction or current addition.

[0133] Figure 8 This is a schematic diagram of a memristor array after writing a parameter matrix, provided for at least one embodiment of this disclosure.

[0134] For example, Figure 8 V1 to V Q Each of the Q first analog signals is input to one of the Q column signal input terminals. Figure 8 I in 1+ to I P+ and I 1- to I P- These are 2P current signals output from 2P horizontal signal output terminals, and P second analog signals I1 to I2 are obtained based on these 2P current signals. P P and Q are positive integers.

[0135] For example, such as Figure 8 As shown, the parameter matrix W corresponds to the conductance matrix G0 = [G 11 … G 1Q ;…;G P1 …G PQ The first submatrix W1 corresponds to the conductance matrix G of the memristor. t+ =[G 11+ … G 1Q+ ;…;G P1+ …G PQ+ The second submatrix W2 corresponds to the conductance matrix G of the memristor. t- =[G 11- … G 1Q- ;…;G P1- …G PQ- G represents the conductance value of the memristor corresponding to the value of the parameter element. The conductance value G corresponding to the parameter element located in the m-th row and n-th column of the first submatrix W1 is... mn+ The conductance value G corresponding to the parameter element located in the m-th row and n-th column of the second submatrix W2 mn- Together, they represent the conductance value G corresponding to the parameter elements used in performing data processing. mn That is, the parameter matrix W used to perform data processing is represented by the first submatrix W1 and the corresponding second submatrix W2.

[0136] For example, each parameter element used to perform data processing can be represented by the difference between the parameter elements at the corresponding row and column positions in the first submatrix W1 and the second submatrix W2. Thus, the negative values ​​of the parameter elements can be achieved using the first submatrix and the corresponding second submatrix to perform richer and more complex data processing.

[0137] For example, arranging the first submatrix W1 and the second submatrix W2 into a first matrix W0 of 2P rows and Q columns, that is, W0 mapped to the conductance matrix G on the memristor. t =[G 11+ …G 1Q+ ;…;G P1+ …G PQ+ G 11- …G 1Q- ;…;G P1- …G PQ- ].

[0138] For example, in step S120, the first submatrix W1 and the second submatrix W2 are mapped into the memristor array in the form of the first matrix W0. For example, the first submatrix W1 is mapped as follows: Figure 8 The memristor subarray A shown has its second submatrix W2 mapped as follows: Figure 8 The memristor subarray B is shown. Memristor subarray A and memristor subarray B are as follows... Figure 8 The area marked with a thick black solid line is shown in the image. The specific mapping process has been described previously and will not be repeated here.

[0139] For example, in step S130, Figure 8 The set of rows to be processed corresponding to the memristor array shown includes: a row of target memristor cells (G) located in the m-th row (e.g., the m-th row of the memristor array) in the memristor subarray A. m1+ G m2+ …G mQ+ ), and a target memristor cell (G) located in the m-th row (e.g., the P+m-th row of the memristor array) of the memristor subarray B. m1- G m2- …G mQ- For example, the current signal I at the row signal output terminal of the m-th row in a memristor array. m+ and the current signal I at the row signal output terminal of row P+m. m- Current preprocessing is performed to obtain the second analog signal I. m And so on, obtaining P second analog signals after data processing in the above manner.

[0140] For example, the current preprocessing described above is a current subtraction process. In other examples, the current preprocessing can also be a current addition process.

[0141] It should be noted that, Figure 8 The mapping shown is merely illustrative. For example, the first and second submatrices can also be mapped to the memristor array row by row, and this disclosure does not limit this. For instance, the first row of parameter elements of the first submatrix is ​​mapped to the first row of the memristor array, the first row of parameter elements of the second submatrix is ​​mapped to the second row of the memristor array, the second row of parameter elements of the first submatrix is ​​mapped to the third row of the memristor array, the second row of parameter elements of the second submatrix is ​​mapped to the fourth row of the memristor array, and so on.

[0142] For example, two corresponding first and second memristor arrays can be used, and the current signal at the corresponding row signal output terminal can be preprocessed to obtain a second analog signal, so as to realize the negative value of the parameter element and perform richer and more complex data processing.

[0143] For example, the memristor array includes a first memristor array and a second memristor array. The parameter element in the u-th row and v-th column of the parameter matrix is ​​jointly represented by the parameter element in the u-th row and v-th column of the first submatrix and the parameter element in the u-th row and v-th column of the second submatrix, where u and v are positive integers. Both the first submatrix and the second submatrix have the same matrix form as the parameter matrix.

[0144] For example, step S120 may include: mapping the first submatrix to the first memristor array in the form of a parameter matrix, and mapping the second submatrix to the second memristor array in the form of a parameter matrix.

[0145] At this point, for step S130, for example, multiple second analog signals after data processing are obtained at multiple row signal output terminals of the memristor array, including: performing current preprocessing on the current signal of each of the multiple row signal output terminals in the first memristor array and the current signal of each of the corresponding multiple row signal output terminals in the second memristor array to obtain multiple second analog signals.

[0146] For example, current preprocessing can be either current subtraction or current addition.

[0147] Figure 9 This is a schematic diagram of another memristor array after writing a parameter matrix, provided in at least one embodiment of this disclosure. This embodiment can be compared with... Figure 9 The illustrated embodiment achieves the same data processing.

[0148] Figure 9 The memristor array shown includes a first memristor array and a second memristor array. Each memristor array has independent control circuitry, such as independent column signal input terminals, to respectively input Q first analog signals V1 to V2. Q And an independent line signal output terminal to output current signal I. 1+ To current signal I P+ and current signal I 1- To current signal I P- .For example, Figure 9 I1 to I P This represents P second analog signals after data processing.

[0149] For example, the parameter matrix comprises P rows and Q columns. The parameter element in the u-th row and v-th column of the parameter matrix is ​​jointly represented by the parameter element in the u-th row and v-th column of the first submatrix and the parameter element in the u-th row and v-th column of the second submatrix, where u and v are positive integers. Both the first and second submatrixes have the same matrix form as the parameter matrix. That is, the first submatrix is ​​P rows and Q columns, and the second submatrix is ​​also P rows and Q columns. The parameter elements at corresponding row and column positions in the first and second submatrixes jointly represent a parameter element for performing the data processing. For example, each parameter element used to perform data processing is represented by the sum or difference of the parameter elements at corresponding row and column positions in the first submatrix W1 and the second submatrix W2.

[0150] For example, the parameter matrix W corresponds to the conductance matrix G0 = [G 11 …G 1Q ;…;G P1 …G PQ The first submatrix W1 corresponds to the conductance matrix G of the memristor. t+ =[G 11+ …G 1Q+ ;…;G P1+ …G PQ+ The second submatrix W2 corresponds to the conductance matrix G of the memristor. t- =[G 11- …G 1Q- ;…;G P1- …G PQ- The conductance value G corresponding to the parameter element located in the u-th row and v-th column of the first submatrix W1. uv+ The conductance value G corresponding to the parameter element located in the u-th row and v-th column of the second submatrix W2 uv- Together, they represent the conductance value G corresponding to the parameter elements used in performing data processing. uv That is, the parameter matrix W used to perform data processing is represented by the first submatrix W1 and the corresponding second submatrix W2.

[0151] For example, each parameter element used to perform data processing can be represented by the difference between the parameter elements at the corresponding row and column positions in the first submatrix W1 and the second submatrix W2. Thus, the negative values ​​of the parameter elements can be achieved using the first submatrix and the corresponding second submatrix to perform richer and more complex data processing.

[0152] For example, such as Figure 9 As shown, in step S120, the first submatrix is ​​mapped onto the first memristor array in the form of a parameter matrix, and the second submatrix is ​​mapped onto the second memristor array in the form of a parameter matrix. The specific mapping process is as described above and will not be repeated here.

[0153] For example, according to step S130, the current signal I at the row signal output terminal of the u-th row in the first memristor array is... u+ The current signal I at the row signal output terminal of the u-th row in the second memristor array u- Current preprocessing is performed to obtain the second analog signal I. u And so on, obtaining P second analog signals after data processing in the above manner.

[0154] For example, the current preprocessing described above is a current subtraction process. In other examples, the current preprocessing can also be a current addition process.

[0155] For example, taking data processing as the Discrete Fourier Transform as an example, refer to... Figures 7A-7C Obtain the parameter matrix W t , the parameter matrix W t The parameter elements used to perform data processing are represented by the difference between the parameter elements at corresponding row and column positions in the first and second submatrices.

[0156] Figure 10A A schematic diagram of a conductance mapping heatmap of a first submatrix provided for at least one embodiment of this disclosure; Figure 10B This is a schematic diagram of a conductance mapping matrix heatmap of a second submatrix provided in at least one embodiment of the present disclosure.

[0157] For example, such as Figure 10A and Figure 10B As shown, the parameter matrix W t Mapped to a memristor array, the lowest memristor conductance G used during mapping. min =2µS, highest memristor conductance G max = 20µS, where µS represents the unit of electrical conductance.

[0158] like Figure 10A As shown, the first submatrix W1 is mapped to the first memristor array in the manner described in step S120. For example, the corresponding memristors are programmed to the corresponding conductance states according to the first submatrix W1; such as... Figure 10B As shown, the second submatrix W2 is mapped to the memristor array in the manner described in step S120. For example, the corresponding memristors are programmed to their respective conductance states according to the second submatrix W2. Parameter matrix W t The parameter elements are represented by the parameter elements at the corresponding row and column positions of the first submatrix mapped to the first memristor array and the second submatrix mapped to the second memristor array.

[0159] This data processing method based on memristor arrays can achieve all the results of matrix-vector multiplication operations in the complex field in a single calculation (or one calculation cycle) by negating and integrating the real and imaginary parts of the matrix in the complex field. This greatly reduces the area and power consumption of the peripheral circuits used to implement functions such as addition and subtraction in traditional schemes, thereby reducing power consumption and improving calculation speed.

[0160] Corresponding to the above-described data processing method based on memristor arrays, at least one embodiment of this disclosure also provides an electronic device. Figure 11A This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0161] like Figure 11A As shown, the electronic device 100 includes a memristor array 101, a signal acquisition device 102, and a control drive circuit 103. The memristor array 101 is configured to perform multiplication and summation operations to perform the data processing described above. The signal acquisition device 102 is configured to acquire a plurality of first analog signals. The control drive circuit 103 is configured to execute steps S120 to S130.

[0162] For example, memristor array 101 can employ Figure 2 The memristor array shown comprises multiple memristor cells arranged in an array of r rows and s columns. For example, each memristor cell includes a memristor, and each memristor includes a first terminal and a second terminal. The memristor can be set to an initial state and can also be set (positioned) to a position with a certain resistance value. When the memristor is in the initial state, its resistance value is much greater than its resistance when in the position. For example, each memristor cell also includes a switching element, which includes a control terminal, a first terminal, and a second terminal. The first terminal of the memristor is electrically connected to the first terminal of the switching element.

[0163] For example, a memristor array also includes r word lines, r source lines, and s bit lines. The r word lines correspond to r rows, and each word line is electrically connected to the control terminal of each switching element in a row of memristor cells; the r source lines correspond to r rows, and each source line is electrically connected to the second terminal of each switching element in a row of memristor cells; the s bit lines correspond to s columns, and each bit line is electrically connected to the second terminal of each memristor in a column of memristor cells.

[0164] For example, the signal acquisition device 102 includes a digital signal acquisition circuit and a digital-to-analog conversion circuit. For example, the digital signal acquisition circuit is configured to acquire multiple initial digital signals; the digital-to-analog conversion circuit is configured to perform digital-to-analog conversion processing on the multiple initial digital signals to obtain multiple first analog signals respectively.

[0165] For example, the control drive circuit 103 may include a source line drive circuit, a word line drive circuit, and a bit line drive circuit. The source line drive circuit is configured to detect a plurality of second analog signals and perform an initialization operation on the memristor array; the word line drive circuit is configured to apply enable signals to a plurality of signal control terminals of the memristor array and perform an initialization operation on the memristor array; the bit line drive circuit is configured to apply input signals to a plurality of column signal input terminals and perform an initialization operation on the memristor array, wherein the input signals include at least a plurality of first analog signals.

[0166] For example, the control drive circuit 103 can apply input signals to multiple column signal input terminals of the memristor array through the bit line drive circuit, apply enable signals to multiple signal control terminals of the memristor array through the word line drive circuit, and finally process the current signals of multiple row signal output terminals of the set memristor array through the source line drive circuit to obtain multiple second analog signals.

[0167] For example, the electronic device 100 may further include a data output circuit, wherein the data output circuit is configured to convert a plurality of second analog signals into digital signals, so as to convert the plurality of second analog signals into a plurality of digital signals for subsequent processing.

[0168] It should be noted that for a detailed explanation of acquiring multiple first analog signals through the signal acquisition device 102, please refer to the above-described embodiment of the data processing method based on memristor array. Figure 4 The description of step S110 is shown; the control drive circuit 103 is used to implement... Figure 4 For a detailed explanation of steps S120 to S130, and the control drive circuit 103, please refer to the above-described embodiment of the data processing method based on memristor array. Figure 4 The relevant descriptions of steps S120 to S130 are shown below. Furthermore, the electronic device can achieve similar technical effects to the aforementioned memristor array-based data processing method, which will not be elaborated upon here.

[0169] Figure 11B This is a schematic diagram of an electronic device provided for at least one embodiment of the present disclosure. For example, as shown in FIG11B, the electronic device includes a signal acquisition device, a word line driving circuit, a bit line driving circuit, a source line driving circuit, a memristor array, and a data output circuit.

[0170] For example, the signal acquisition device is configured to convert a digital signal into a plurality of first analog signals via a DAC (Digital to Analog converter) for input to a plurality of column signal inputs of a memristor array during data processing.

[0171] For example, the matrix used for matrix-vector multiplication in the complex field is M rows and N columns, where M and N are positive integers. The memristor array includes at least 2N source lines, 2N word lines, and 2M bit lines, as well as multiple memristor cells arranged in a 2N row and 2M column array (e.g., corresponding to...). Figure 6 (A memristor array with 2N rows and 2M columns). For example, each memristor cell is a 1T1R structure. The parameter matrix used for data processing is mapped to the memristor array. The specific process is as described in step S120, and will not be repeated here.

[0172] For example, the data processing process achieved through word line driving circuits, bit line driving circuits, and source line driving circuits is as described above and will not be repeated here.

[0173] For example, a word line driver circuit includes multiple multiplexers (Muxes) for switching word line input voltages, a bit line driver circuit includes multiple multiplexers for switching bit line input voltages, and a source line driver circuit also includes multiple multiplexers for switching source line input voltages.

[0174] For example, a memristor array includes an operating mode and a computation mode. When the memristor array is in operating mode, the memristor cells are in an initialization state, and the values ​​of the parameter elements in the parameter matrix can be written into the memristor array. For example, the source line input voltage, bit line input voltage, and word line input voltage of the memristor can be switched to the corresponding preset voltage range through a multiplexer.

[0175] For example, through Figure 11B The control signal WL_sw[1:2N] of the multiplexer in the word line driver circuit switches the word line input voltage to the corresponding voltage range. For example, when setting the memristor, the word line input voltage is set to 2V (volts); when resetting the memristor, the word line input voltage is set to 5V. The word line input voltage can be... Figure 11B The voltage signal V_WL[1:2N] is obtained.

[0176] For example, through Figure 11B The control signal SL_sw[1:2N] of the multiplexer in the source line drive circuit switches the source line input voltage to the corresponding voltage range. For example, when setting the memristor, the word line input voltage is set to 0V; when resetting the memristor, the source line input voltage is set to 2V. The source line input voltage can be... Figure 11B The voltage signal V_SL[1:2N] is obtained.

[0177] For example, through Figure 11B The control signal BL_sw[1:2M] of the multiplexer in the bit line drive circuit switches the bit line input voltage to the corresponding voltage range. For example, when setting the memristor, the bit line input voltage is set to 2V; when resetting the memristor, the bit line input voltage is set to 0V. The source line input voltage can be... Figure 11B The DAC is obtained from the middle.

[0178] When the memristor array is in compute mode, the memristors in the array are in a conductive state that can be used for computation. The bit line input voltage at the column signal input terminal does not change the conductance of the memristors, allowing data processing to be completed by performing multiplication and summation operations through the memristor array. For example, through... Figure 11B The control signal WL_sw[1:2N] of the multiplexer in the word line driver circuit switches the word line input voltage to the corresponding voltage range. For example, when an enable signal is applied, the word line input voltage of the corresponding row is set to 5V; when no enable signal is applied, the word line input voltage of the corresponding row is set to 0V. For example, the GND signal is turned on. Figure 11B The control signal SL_sw[1:2N] of the multiplexer in the source line drive circuit switches the source line input voltage to the corresponding voltage range, for example, setting the source line input voltage to 0V, so that the current signals of multiple row signal output terminals can flow into the data output circuit. Figure 11B The control signal BL_sw[1:2M] of the multiplexer in the bit line drive circuit switches the bit line input voltage to the corresponding voltage range, for example, setting the bit line input voltage to 0.1V-0.3V, thereby utilizing the multiplication and summation characteristics of the memristor array to complete data processing.

[0179] For example, the data output circuit includes multiple ADCs (Analog to Digital converters) that can convert the current signals from multiple row signal outputs into digital signals for subsequent processing.

[0180] Figure 11C This is a schematic diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0181] Figure 11C The electronic device shown is Figure 11B The electronic devices shown have the same structure, including signal acquisition devices, word line driving circuits, bit line driving circuits, source line driving circuits, memristor arrays, and data output circuits.

[0182] For example, a memristor array includes 2N source lines, 4N word lines, and 4M bit lines, as well as multiple memristor cells arranged in a 2N row and 2M column array (e.g., corresponding to...). Figure 6 (A memristor array with 2N rows and 2M columns). For example, each memristor cell has a 2T2R structure. The parameter matrix used for data processing is mapped multiple times to different subarrays in the memristor array. The specific process is as described in step S120, and will not be repeated here.

[0183] It should be noted that the memristor array may also include 2N source lines, 2N word lines, and 4M bit lines, as well as multiple memristor cells arranged in a 2N row and 2M column array. Since the enable signal is applied to multiple signal control terminals of the memristor array simultaneously during step S130, each word line can simultaneously control two memristors in each row of memristor cells.

[0184] The descriptions of the signal acquisition device, control drive circuit, and data output circuit have been described above and will not be repeated here.

[0185] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0186] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0187] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0188] The following points need to be clarified regarding this disclosure:

[0189] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0190] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0191] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / j> < / r> < / s> < / r>

Claims

1. A data processing method based on a memristor array, wherein, The data processing includes matrix-vector multiplication operations in the complex field, and the memristor array includes multiple memristor cells arranged in an array and configured to perform multiplication and summation operations. The data processing method includes: Acquire multiple first analog signals; The memristor array is configured, and data corresponding to the parameter matrix of the data processing is written into the memristor array. The matrix in the complex field includes a real part matrix and an imaginary part matrix. The parameter matrix includes the real part matrix, the imaginary part matrix, and an imaginary negative matrix obtained based on the imaginary part matrix. The parameter elements in the imaginary negative matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the imaginary negative matrix is ​​the negative value of the corresponding parameter element in the imaginary part matrix. The plurality of first analog signals are respectively input to the plurality of column signal input terminals of the configured memristor array to control the operation of the memristor array to perform the data processing on the plurality of first analog signals, and the plurality of second analog signals after the data processing are respectively obtained at the plurality of row signal output terminals of the memristor array.

2. The data processing method according to claim 1, wherein, The memristor array includes a first subarray, a second subarray, a third subarray, and a fourth subarray. Setting up the memristor array and writing data corresponding to the parameter matrix of the data processing into the memristor array includes: Multiple parameter elements in the real part matrix are mapped to the first subarray and the fourth subarray according to the form of the real part matrix, respectively; multiple parameter elements in the imaginary part matrix are mapped to the third subarray according to the form of the imaginary part matrix; and multiple parameter elements in the negative imaginary part matrix are mapped to the second subarray according to the form of the negative imaginary part matrix. The first subarray and the second subarray are located in the same row of the memristor array but do not overlap in the row direction; the third subarray and the fourth subarray are located in the same row of the memristor array but do not overlap in the row direction; and the first subarray and the third subarray do not overlap in the column direction.

3. The data processing method according to claim 2, wherein, The first subarray and the third subarray are located in the same column of the memristor array, and the second subarray and the fourth subarray are located in the same column of the memristor array.

4. The data processing method according to claim 2, wherein, The memristor array comprises at least 2N rows and 2M columns. The first subarray includes rows i to i+N-1 and columns j to j+M-1 of the memristor array. The second subarray includes rows i to i+N-1 and columns j+k+M-1 to j+k+2*M-2 of the memristor array. The third subarray includes rows i+g+N-1 to i+g+2N-2 and columns j to j+M-1 of the memristor array. The fourth subarray includes rows i+g+N-1 to i+g+2N-2 and columns j+k+M-1 to j+k+2*M-2 of the memristor array. Where M, N, i, j, k, and g are positive integers.

5. The data processing method according to claim 2, wherein, The real part matrix comprises multiple parametric elements arranged in an array of N rows and M columns. Mapping multiple parameter elements in the real part matrix to the first subarray and the fourth subarray according to the form of the real part matrix, including: The N parameter elements in the real part matrix located in the same row are respectively mapped to the N memristor cells in the same row of the first subarray and the N memristor cells in the same row of the fourth subarray. The M parameter elements in the same column of the real part matrix are respectively mapped to the M memristor cells in the same column of the first subarray and the M memristor cells in the same column of the fourth subarray. Where M and N are positive integers.

6. The data processing method according to claim 2, wherein, Each of the plurality of first analog signals includes a first real part analog signal and a first imaginary part analog signal. Acquiring the plurality of first analog signals includes: Obtain a vector of the complex field for the data processing, wherein the vector of the complex field includes a real part vector and an imaginary part vector; The real part vector and the imaginary part vector are encoded respectively to obtain multiple first real part analog signals and multiple first imaginary part analog signals.

7. The data processing method according to claim 6, wherein, The plurality of first analog signals are respectively input to the plurality of column signal input terminals of the configured memristor array, including: The plurality of first real part analog signals are respectively input to the column signal input terminals of the first subarray and the third subarray; The plurality of first imaginary part analog signals are respectively input to the column signal input terminals of the second subarray and the fourth subarray.

8. The data processing method according to claim 2, wherein, Each of the plurality of second analog signals includes a second real part analog signal and a second imaginary part analog signal. The first subarray and the second subarray share the same row signal output terminal, and the third subarray and the fourth subarray share the same row signal output terminal. Multiple second analog signals, resulting from the data processing, are obtained at the multiple row signal output terminals of the memristor array, including: Multiple second real part analog signals are obtained based on the current signal output from the row signal output terminal of the first subarray; Multiple second real and imaginary part signals are obtained based on the current signal output from the row signal output terminal of the third subarray.

9. The data processing method according to claim 8, further comprising: The plurality of second real part analog signals are subjected to analog-to-digital conversion to obtain the real part operation result of the matrix-vector multiplication operation; The multiple second imaginary part analog signals are subjected to analog-to-digital conversion to obtain the imaginary part operation result of the matrix-vector multiplication operation.

10. The data processing method according to claim 1, wherein, The parameter matrix is ​​represented as follows: Among them, W real Let W be the real part matrix. img Let W be the imaginary part matrix. img Let be the negative imaginary part matrix.

11. The data processing method according to any one of claims 1-10, wherein, The parameter matrix comprises P rows and Q columns. The parameter element in the m-th row and n-th column of the parameter matrix is ​​jointly represented by the parameter element in the m-th row and n-th column of the first sub-matrix and the parameter element in the m-th row and n-th column of the second sub-matrix. m, n, P, and Q are positive integers. The first submatrix includes P rows of first parameter elements, and the second submatrix includes P rows of second parameter elements, wherein the row and column positions of the P rows of first parameter elements and the P rows of second parameter elements correspond one-to-one. The first submatrix and the second submatrix are arranged in a first matrix form of 2P rows and Q columns. Setting up the memristor array and writing data corresponding to the parameter matrix of the data processing into the memristor array includes: The first submatrix and the second submatrix are mapped to the memristor array in the form of the first matrix.

12. The data processing method according to claim 11, wherein, Multiple second analog signals, resulting from the data processing, are obtained at the multiple row signal output terminals of the memristor array, including: Determine at least one set of rows to be processed, wherein each set of at least one set of rows to be processed includes a row of target memristor units corresponding to a row of the first parameter elements of the P rows, and a row of target memristor units corresponding to a row of the second parameter elements of the P rows corresponding to a row of the first parameter elements of the P rows. The current signals of two of the multiple row signal output terminals corresponding to the two target memristor units in each of the at least one set of rows to be processed are preprocessed to obtain the multiple second analog signals corresponding to each of the at least one set of rows to be processed.

13. The data processing method according to any one of claims 1-10, wherein, The memristor array includes a first memristor array and a second memristor array. The parameter element in the u-th row and v-th column of the parameter matrix is ​​jointly represented by the parameter element in the u-th row and v-th column of the first sub-matrix and the parameter element in the u-th row and v-th column of the second sub-matrix, where u and v are positive integers. Both the first submatrix and the second submatrix have the same matrix form as the parameter matrix. Setting up the memristor array and writing data corresponding to the parameter matrix of the data processing into the memristor array includes: mapping the first sub-matrix onto the first memristor array in the form of the parameter matrix. The second submatrix is ​​mapped onto the second memristor array in the form of the parameter matrix.

14. The data processing method according to claim 13, wherein, Multiple second analog signals, resulting from the data processing, are obtained at the multiple row signal output terminals of the memristor array, including: The current signals of each of the plurality of row signal output terminals in the first memristor array and the current signals of each of the corresponding plurality of row signal output terminals in the second memristor array are subjected to current preprocessing to obtain the plurality of second analog signals.

15. The data processing method according to claim 12 or 14, wherein, The current preprocessing is either current subtraction or current addition.

16. The data processing method according to any one of claims 1-10, wherein, The data processing is a Discrete Fourier Transform, and the matrix in the complex field is the coefficient matrix of the Discrete Fourier Transform. The real part matrix is ​​the real part of the coefficient matrix, and the imaginary part matrix is ​​the imaginary part of the coefficient matrix.

17. An electronic device comprising: A memristor array configured to perform multiplication and summation operations; A signal acquisition device, configured to acquire multiple first analog signals; A control drive circuit, wherein the control drive circuit is configured to perform the following steps: The memristor array is configured, and data corresponding to the parameter matrix of the data processing is written into the memristor array. The data processing includes matrix-vector multiplication in the complex field. The matrix in the complex field includes a real part matrix and an imaginary part matrix. The parameter matrix includes the real part matrix, the imaginary part matrix, and an imaginary negative matrix obtained based on the imaginary part matrix. The parameter elements in the imaginary negative matrix correspond one-to-one with the parameter elements in the imaginary part matrix, and each parameter element in the imaginary negative matrix is ​​the negative value of the corresponding parameter element in the imaginary part matrix. The plurality of first analog signals are respectively input to the plurality of column signal input terminals of the configured memristor array to control the operation of the memristor array to perform the data processing on the plurality of first analog signals, and the plurality of second analog signals after the data processing are respectively obtained at the plurality of row signal output terminals of the memristor array.

18. The electronic device according to claim 17, wherein, The memristor array includes a first subarray, a second subarray, a third subarray, and a fourth subarray. When the control drive circuit executes the setting of the memristor array and writes data corresponding to the parameter matrix of the data processing into the memristor array, it includes performing the following steps: Multiple parameter elements in the real part matrix are mapped to the first subarray and the fourth subarray according to the form of the real part matrix, respectively; multiple parameter elements in the imaginary part matrix are mapped to the third subarray according to the form of the imaginary part matrix; and multiple parameter elements in the negative imaginary part matrix are mapped to the second subarray according to the form of the negative imaginary part matrix. The first subarray and the second subarray are located in the same row of the memristor array but do not overlap in the row direction; the third subarray and the fourth subarray are located in the same row of the memristor array but do not overlap in the row direction; and the first subarray and the third subarray do not overlap in the column direction.

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