Device simulation method and apparatus

Abstract

The device simulation method and device provided by the embodiments of the present disclosure, the method comprises: establishing a simulation model of a to-be-tested device, the to-be-tested device comprising a first resistance and a parasitic resistance, the parasitic resistance comprising a second resistance and a contact resistance, wherein the first resistance is a bulk resistance of the to-be-tested device, the second resistance is a terminal resistance, and the contact resistance is an equivalent resistance of a contact plug on the to-be-tested device; determining resistance temperature coefficients corresponding to the first resistance, the second resistance and the contact resistance and adding them to the simulation model; and performing SPICE device simulation according to the simulation model. The embodiments of the present disclosure divide the resistance of the to-be-tested device into a bulk resistance and a parasitic resistance, and split the parasitic resistance into a terminal resistance and a contact resistance, calculate the resistance values of the resistances according to test results, and calculate the resistance temperature coefficients corresponding to the resistances, so that the simulation model of the to-be-tested device can be accurately established, and the simulation accuracy of the to-be-tested device can be effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a device simulation method and apparatus. Background Technology

[0002] In the semiconductor industry, modeling and simulation techniques are frequently used to extract parameters from components in semiconductor integrated circuits and simulate their electrical performance, providing corresponding process models for subsequent circuit simulations. For example, resistors, as one of the most basic components in semiconductor integrated circuits, are typically modeled using a general-purpose analog circuit simulator (Simulation Program with Integrated Circuit Emphasis, or SPICE) to simulate their electrical performance under various environmental parameters, including changes in resistance value due to temperature, size, and operating voltage.

[0003] Resistors typically employ a two-terminal structure, requiring contact holes and metal leads to connect them effectively to other circuits. However, current resistor testing methods suffer from parasitic resistance due to the contact holes and metal leads, and the influence of ambient temperature on resistance values. This makes it difficult to establish accurate simulation models, impacting the simulation accuracy of subsequent circuits. Summary of the Invention

[0004] This disclosure provides a device simulation method and apparatus that can improve the simulation accuracy of devices.

[0005] In some embodiments, a device simulation method is provided, including:

[0006] A simulation model of the device under test is established. The device under test includes a first resistance and a parasitic resistance. The parasitic resistance includes a second resistance and a contact resistance. The first resistance is the bulk resistance of the device under test. The second resistance is the terminal resistance of the device under test. The contact resistance is the equivalent resistance of the contact plug on the device under test.

[0007] Determine the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and add the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor to the simulation model;

[0008] Based on the simulation model, perform simulation of general analog circuit simulator devices.

[0009] In one feasible implementation, establishing a simulation model of the device under test includes:

[0010] Determine multiple sampling temperatures T1, T2, ..., Tn;

[0011] Determine the functional relationship between the resistance of the device under test and a first length at each sampling temperature, where the first length is the length of the device under test on the layout;

[0012] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the resistance of the parasitic resistance are determined at each sampling temperature.

[0013] The resistance value of the contact resistance is determined based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature.

[0014] In one feasible implementation, determining the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes:

[0015] At each sampling temperature, the resistance of the device under test is measured at different first lengths corresponding to the same width, where the width is the width of the device under test on the layout.

[0016] Plotting the first length as the X-axis and the resistance value as the Y-axis and performing linear fitting, the first function curve corresponding to the resistance value of the device under test and the first length in a preset rectangular coordinate system is determined at each sampling temperature.

[0017] In one feasible implementation, determining the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the parasitic resistance at each sampling temperature based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes:

[0018] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor is determined at each sampling temperature.

[0019] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the resistance value of the parasitic resistance at each sampling temperature is determined, wherein the resistance value of the parasitic resistance is independent of the first length;

[0020] The sheet resistance of the second resistor is determined based on the sheet resistance of the first resistor at each sampling temperature.

[0021] In one feasible implementation, determining the sheet resistance of the first resistor at each sampling temperature based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes:

[0022] Based on the slope K(Ti) of the function curve L(Ti) corresponding to the resistance of the device under test and the first length in a preset rectangular coordinate system at the sampling temperature Ti, calculate the sheet resistance Rs_pure(Ti) of the first resistor at the sampling temperature Ti:

[0023] Rs_pure(Ti)=K(Ti)*W

[0024] Where W represents the width of the device under test on the layout, and Ti∈(T1, T2, ..., Tn).

[0025] In one feasible implementation, determining the parasitic resistance value at each sampling temperature based on the functional relationship between the resistance value of the device under test and the first length at each sampling temperature includes:

[0026] Based on the intercept B(Ti) of the function curve L(Ti) corresponding to the resistance of the device under test and the first length in a preset rectangular coordinate system at the sampling temperature Ti, the parasitic resistance Rext(Ti) ​​at the sampling temperature Ti is calculated:

[0027] Rext(Ti)=B(Ti) / 2

[0028] Where Ti∈(T1, T2, ..., Tn).

[0029] In one feasible implementation, determining the sheet resistance of the second resistor at each sampling temperature based on the sheet resistance of the first resistor at each sampling temperature includes:

[0030] The sheet resistance Rs_pure(Ti) of the first resistor at sampling temperature Ti is determined as the sheet resistance Rs_end(Ti) of the second resistor at sampling temperature Ti;

[0031] Where Ti∈(T1, T2, ..., Tn).

[0032] In one feasible implementation, determining the contact resistance value at each sampling temperature based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature includes:

[0033] The contact resistance Rlicon(Ti) at the sampling temperature Ti is calculated as follows:

[0034] Rlicon(Ti)=Rext(Ti)–Rs_end(Ti)*L_end / W

[0035] Where Rext(Ti) ​​represents the parasitic resistance at sampling temperature Ti, Rs_end(Ti) represents the sheet resistance of the second resistor at sampling temperature Ti, L_end represents the length of the contact terminal of the device under test on the layout, W represents the width of the device under test on the layout, and Ti∈(T1, T2, ..., Tn).

[0036] In one feasible implementation, when the number N of the contact plugs on one contact terminal of the device under test is greater than or equal to 2, the resistance Rlicon'(Ti) of a single contact plug at the sampling temperature Ti is:

[0037] Rlicon'(Ti)=Rlicon(Ti)*N

[0038] In one feasible implementation, the temperature coefficient of resistance corresponding to the first resistor is determined in the following manner:

[0039] Based on the sheet resistances Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(Tn) of the first resistor at each sampling temperature T1, T2, ..., Tn, a second function curve of the temperature coefficient of resistance of the first resistor versus ambient temperature is determined by plotting the difference between the sampling temperature Ti and the reference sampling temperature Tj as the X-axis and the quotient of the sheet resistance Rs_pure(Ti) of the first resistor at sampling temperature Ti and the sheet resistance Rs_pure(Tj) of the first resistor at the reference sampling temperature Tj as the Y-axis, and performing linear fitting.

[0040] Based on the second function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the first resistor is determined.

[0041] In one feasible implementation, determining the temperature coefficient of resistance corresponding to the first resistor based on the second function curve and the ambient temperature to be measured includes:

[0042] The temperature coefficient of resistance TC_Rpure(t) corresponding to the first resistor is calculated as follows:

[0043] TC_Rpure(t)=K1*(t-Tj)+C1

[0044] Where K1 is the slope of the second function curve, t represents the ambient temperature to be measured, and C1 represents the intercept of the second function curve.

[0045] In one feasible implementation, the temperature coefficient of resistance of the first resistor is the same as the temperature coefficient of resistance of the second resistor.

[0046] In one feasible implementation, the temperature coefficient of resistance corresponding to the contact resistance is determined as follows:

[0047] Based on the resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(Tn) of the contact resistor at each sampling temperature T1, T2, ..., Tn, a graph is plotted with the difference between the sampling temperature Ti and the reference sampling temperature Tj as the X-axis, and the quotient of the resistance Rlicon(Ti) of the contact resistor at the sampling temperature Ti and the resistance Rlicon(Tj) of the contact resistor at the reference sampling temperature Tj as the Y-axis. Linear fitting is then performed to determine the third function curve of the temperature coefficient of resistance of the contact resistor versus the ambient temperature, where Tj∈(T1, T2, ..., Tn).

[0048] Based on the third function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the contact resistance is determined.

[0049] In one feasible implementation, determining the temperature coefficient of resistance corresponding to the contact resistance based on the third function curve and the ambient temperature to be measured includes:

[0050] The temperature coefficient of resistance TC_Rlicon(t) corresponding to the contact resistance is calculated as follows:

[0051] TC_Rlicon(t)=K2*(t-Tj)+C2

[0052] Wherein, K2 is the slope of the third function curve, t represents the ambient temperature to be measured, and C2 is the intercept of the third function curve.

[0053] In some embodiments, a device simulation apparatus is provided, the apparatus comprising:

[0054] The processing module is used to establish a simulation model of the device under test (DUT). The DUT includes a first resistance and a parasitic resistance. The parasitic resistance includes a second resistance and a contact resistance. The first resistance is the bulk resistance of the DUT, the second resistance is the terminal resistance of the DUT, and the contact resistance is the equivalent resistance of the contact plug on the DUT.

[0055] The calculation module is used to determine the resistance temperature coefficients corresponding to the first resistor, the second resistor, and the contact resistor, and add the resistance temperature coefficients corresponding to the first resistor, the second resistor, and the contact resistor to the simulation model;

[0056] The simulation module is used to perform simulation of general analog circuit simulator devices based on the simulation model.

[0057] In one feasible implementation, the processing module is specifically used for:

[0058] Determine multiple sampling temperatures T1, T2, ..., Tn;

[0059] Determine the functional relationship between the resistance of the device under test and a first length at each sampling temperature, where the first length is the length of the device under test on the layout;

[0060] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the resistance of the parasitic resistance are determined at each sampling temperature.

[0061] The resistance value of the contact resistance is determined based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature.

[0062] In one feasible implementation, the processing module is specifically used for:

[0063] At each sampling temperature, the resistance of the device under test is measured at different first lengths corresponding to the same width, where the width is the width of the device under test on the layout.

[0064] Plotting the first length as the X-axis and the resistance value as the Y-axis and performing linear fitting, the first function curve corresponding to the resistance value of the device under test and the first length in a preset rectangular coordinate system is determined at each sampling temperature.

[0065] In one feasible implementation, the processing module is specifically used for:

[0066] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor is determined at each sampling temperature.

[0067] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the resistance value of the parasitic resistance at each sampling temperature is determined, wherein the resistance value of the parasitic resistance is independent of the first length;

[0068] The sheet resistance of the second resistor is determined based on the sheet resistance of the first resistor at each sampling temperature.

[0069] In one feasible implementation, the processing module is specifically used for:

[0070] Based on the slope K(Ti) of the function curve L(Ti) corresponding to the resistance of the device under test and the first length in a preset rectangular coordinate system at the sampling temperature Ti, calculate the sheet resistance Rs_pure(Ti) of the first resistor at the sampling temperature Ti:

[0071] Rs_pure(Ti)=K(Ti)*W

[0072] Where W represents the width of the device under test on the layout, and Ti∈(T1, T2, ..., Tn).

[0073] In one feasible implementation, the processing module is specifically used for:

[0074] Based on the intercept B(Ti) of the function curve L(Ti) corresponding to the resistance of the device under test and the first length in a preset rectangular coordinate system at the sampling temperature Ti, the parasitic resistance Rext(Ti) ​​at the sampling temperature Ti is calculated:

[0075] Rext(Ti)=B(Ti) / 2

[0076] Where Ti∈(T1, T2, ..., Tn).

[0077] In one feasible implementation, the processing module is specifically used for:

[0078] The sheet resistance Rs_pure(Ti) of the first resistor at sampling temperature Ti is determined as the sheet resistance Rs_end(Ti) of the second resistor at sampling temperature Ti;

[0079] Where Ti∈(T1, T2, ..., Tn).

[0080] In one feasible implementation, the processing module is specifically used for:

[0081] The contact resistance Rlicon(Ti) at the sampling temperature Ti is calculated as follows:

[0082] Rlicon(Ti)=Rext(Ti)–Rs_end(Ti)*L_end / W

[0083] Where Rext(Ti) ​​represents the parasitic resistance at sampling temperature Ti, Rs_end(Ti) represents the sheet resistance of the second resistor at sampling temperature Ti, L_end represents the length of the contact terminal of the device under test on the layout, W represents the width of the device under test on the layout, and Ti∈(T1, T2, ..., Tn).

[0084] In one feasible implementation, when the number N of the contact plugs on one contact terminal of the device under test is greater than or equal to 2, the resistance Rlicon'(Ti) of a single contact plug at the sampling temperature Ti is:

[0085] Rlicon'(Ti)=Rlicon(Ti)*N

[0086] In one feasible implementation, the computing module is specifically used for:

[0087] The temperature coefficient of resistance corresponding to the first resistor shall be determined in the following manner:

[0088] Based on the sheet resistances Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(Tn) of the first resistor at each sampling temperature T1, T2, ..., Tn, a second function curve of the temperature coefficient of resistance of the first resistor versus ambient temperature is determined by plotting the difference between the sampling temperature Ti and the reference sampling temperature Tj as the X-axis and the quotient of the sheet resistance Rs_pure(Ti) of the first resistor at sampling temperature Ti and the sheet resistance Rs_pure(Tj) of the first resistor at the reference sampling temperature Tj as the Y-axis, and performing linear fitting.

[0089] Based on the second function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the first resistor is determined.

[0090] In one feasible implementation, the computing module is specifically used for:

[0091] The temperature coefficient of resistance TC_Rpure(t) corresponding to the first resistor is calculated as follows:

[0092] TC_Rpure(t)=K1*(t-Tj)+C1

[0093] Where K1 is the slope of the second function curve, t represents the ambient temperature to be measured, and C1 represents the intercept of the second function curve.

[0094] In one feasible implementation, the temperature coefficient of resistance of the first resistor is the same as the temperature coefficient of resistance of the second resistor.

[0095] In one feasible implementation, the computing module is specifically used for:

[0096] The temperature coefficient of resistance corresponding to the contact resistance is determined as follows:

[0097] Based on the resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(Tn) of the contact resistor at each sampling temperature T1, T2, ..., Tn, a graph is plotted with the difference between the sampling temperature Ti and the reference sampling temperature Tj as the X-axis, and the quotient of the resistance Rlicon(Ti) of the contact resistor at the sampling temperature Ti and the resistance Rlicon(Tj) of the contact resistor at the reference sampling temperature Tj as the Y-axis. Linear fitting is then performed to determine the third function curve of the temperature coefficient of resistance of the contact resistor versus the ambient temperature, where Tj∈(T1, T2, ..., Tn).

[0098] Based on the third function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the contact resistance is determined.

[0099] In one feasible implementation, the computing module is specifically used for:

[0100] The temperature coefficient of resistance TC_Rlicon(t) corresponding to the contact resistance is calculated as follows:

[0101] TC_Rlicon(t)=K2*(t-Tj)+C2

[0102] Wherein, K2 is the slope of the third function curve, t represents the ambient temperature to be measured, and C2 is the intercept of the third function curve.

[0103] In some embodiments, an electronic device is provided, including: at least one processor and a memory;

[0104] The memory stores computer-executed instructions;

[0105] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the device simulation method provided in the above embodiments.

[0106] In some embodiments, a computer-readable storage medium is provided, which stores computer-executable instructions. When a processor executes the computer-executable instructions, it implements the device simulation method provided in the above embodiments.

[0107] The device simulation method and apparatus provided in this disclosure divide the resistance of the device under test into bulk resistance and parasitic resistance, and further divide the parasitic resistance into terminal resistance and contact resistance. Based on the test results, the resistance values ​​of the bulk resistance, terminal resistance and contact resistance are analyzed and calculated. At the same time, the resistance temperature coefficients corresponding to the bulk resistance, terminal resistance and contact resistance are calculated, and the calculation results are added to the simulation model. In this way, the simulation model of the device under test can be accurately established, and the simulation accuracy of the device under test can be effectively improved. Attached Figure Description

[0108] Figure 1 This is a schematic diagram of a longitudinal section of a device under test provided in an embodiment of this disclosure. Figure 1 ;

[0109] Figure 2 This is a schematic diagram of a device under test provided in an embodiment of this disclosure. Figure 1 ;

[0110] Figure 3 This is a flowchart illustrating a device simulation method provided in an embodiment of this disclosure;

[0111] Figure 4 This is a schematic diagram of a longitudinal section of a device under test provided in an embodiment of this disclosure. Figure 2 ;

[0112] Figure 5 This is a schematic diagram of the equivalent resistance of a device under test provided in an embodiment of this disclosure;

[0113] Figure 6 This is a schematic diagram of a device under test provided in an embodiment of this disclosure. Figure 2 ;

[0114] Figure 7 This is a schematic diagram of a sub-process of a device simulation method provided in an embodiment of this disclosure;

[0115] Figure 8 This is a schematic diagram of the function curve between the resistance value of the device under test and the first length in an embodiment of this disclosure;

[0116] Figure 9 This is a schematic diagram of the function curves between the resistance of the device under test and the first length at different sampling temperatures in this embodiment of the present disclosure;

[0117] Figure 10 This is a schematic diagram of the length of the contact terminal of a device under test (DUT) provided in an embodiment of this disclosure on a layout. Figure 1 ;

[0118] Figure 11 This is a schematic diagram of the length of the contact terminal of a device under test (DUT) provided in an embodiment of this disclosure on a layout. Figure 2 ;

[0119] Figure 12 This is a schematic diagram of the function curve between the temperature coefficient of resistance of the first resistor and the ambient temperature in an embodiment of this disclosure;

[0120] Figure 13 This is a schematic diagram of the function curve of the temperature coefficient of resistance of the contact resistance versus ambient temperature in an embodiment of this disclosure.

[0121] Figure 14 This is a schematic diagram of the program modules of a device simulation apparatus provided in an embodiment of this disclosure;

[0122] Figure 15 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0123] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or more exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation on its own.

[0124] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0125] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0126] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0127] As used in this disclosure, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0128] With the development of technology, circuit optimization design has become an important stage in the integrated circuit design process. The purpose of circuit optimization is to improve the electrical performance of the circuit. The final actual electrical performance of the circuit depends not only on the device parameter values, but also on the parasitic effects of the devices themselves, the parasitic effects between devices, the parasitic effects of the interconnects themselves, the parasitic effects between interconnects, and the parasitic effects between interconnects and devices. Among these, the parasitic effects between adjacent interconnects are particularly critical. From the perspective of circuit optimization theory, in order to obtain accurate circuit optimization results, it is necessary to accurately consider the parasitic effects between the interconnects of the various devices in the designed circuit, including the parasitic resistance between the interconnects.

[0129] Resistors, as one of the most basic components in semiconductor integrated circuits, come in many types. These include silicide resistors such as N+ polysilicide resistors, P+ polysilicide resistors, N+ diffusion silicide resistors, and P+ diffusion silicide resistors; and non-silicide resistors such as N+ polysilicide resistors, P+ polysilicide resistors, N+ diffusion unsilicide resistors, and P+ diffusion unsilicide resistors. N+ / P+ indicates the type of doped ions in the resistor. If it is N+ type, the doped ions are N-type, such as phosphorus or arsenic atoms; if it is P+ type, the doped ions are P-type, such as boron or gallium atoms.

[0130] To predict the performance and reliability of a resistor in its environment, it is necessary to model and simulate the resistor. That is, for the various components supported by the circuit simulation program, there must be a corresponding electrical model to describe the electrical performance of the device under test.

[0131] In modeling and simulation technology, the corresponding software program usually extracts data for these resistors separately based on the test data of semiconductor integrated circuits, and establishes a corresponding resistor simulation model. These simulation models are not related to each other. By inputting the name of the corresponding simulation model, it can be used to simulate the performance of this type of resistor under various environmental parameters.

[0132] Optionally, the software program mentioned above can be SPICE (Simulation Program with Integrated Circuit Emphasis). SPICE is a language and simulator software for circuit description and simulation, which can be used to check the integrity of circuit connections and functions, as well as to predict circuit behavior. In SPICE models, macro models are typically used to fit resistors, and custom parameters can be freely added to fit various characteristics of the resistor.

[0133] In some embodiments, the resistor is generally a two-terminal structure, with the two ends connected by a contact hole structure and metal leads to facilitate effective connection of the resistor in other circuits.

[0134] To better understand the embodiments of this disclosure, an N+ diffusion resistor is used as an example, with reference to... Figure 1 , Figure 1 This is a schematic diagram of a longitudinal section of a device under test provided in an embodiment of this disclosure. Figure 1 .exist Figure 1 In the above-mentioned resistor device structure, there are: a P-type substrate 100 (P-substrate, abbreviated as Psub), a P-well structure 200 (abbreviated as PWell), a shallow trench isolation structure 300 (shallow trench isolation, abbreviated as STI), an N+ injection region, several contact plugs 400 located at both ends, and metal leads 500.

[0135] Among them, the contact plug 400 is located above the N+ injection region and forms ohmic contact with the N+ injection region.

[0136] In traditional resistance simulation techniques, whether it is a siliconized resistor or a non-siliconized resistor, the extracted simulation model generally mainly includes the bulk resistance (or pure resistance).

[0137] In some implementations, when the above-mentioned resistor is used as the device under test, the sheet resistance value Rs_ndiff is typically determined in the following way:

[0138] Rs_ndiff = R_total / (L / W)

[0139] Where R_total represents the resistance of the device under test, L represents the length of the device under test on the layout, and W represents the width of the device under test on the layout.

[0140] To better understand this embodiment, we will still use the N+ diffusion resistor as an example, referring to... Figure 2 , Figure 2 This is a schematic diagram of a device under test provided in an embodiment of this disclosure. Figure 1 .exist Figure 2 In this diagram, L represents the length of the device under test (DUT) on the layout, and W represents the width of the DUT on the layout. L and W are in the same unit, typically in micrometers (µm). 400 represents the contact plugs located at both ends.

[0141] However, the accuracy of circuit simulation depends not only on the device model but also directly on whether the given model parameter values ​​can accurately reflect the electrical characteristics of the components. Parasitic resistance is generated by contact plugs, metal leads, and other elements in the resistor structure, and this parasitic resistance cannot be subtracted during measurement. Furthermore, ambient temperature also affects the resistance value. Therefore, if the simulation model fails to accurately incorporate parasitic resistance and the influence of ambient temperature on the resistance value, the simulation accuracy will be reduced.

[0142] To address the above technical problems, this disclosure provides a device simulation method. The method divides the resistance of the device under test (DUT) into bulk resistance and parasitic resistance, further subdividing the parasitic resistance into terminal resistance and contact resistance. Based on test results, the resistance values ​​of the bulk resistance, terminal resistance, and contact resistance, as well as their corresponding temperature coefficients of resistance, are analyzed and calculated. This allows for the establishment of a simulation model of the DUT, effectively improving the simulation accuracy. Specific implementation details can be found in the following embodiments.

[0143] The device simulation method provided in this disclosure can be applied to various types of simulation equipment, such as computers, industrial testing machines, and mobile terminals. This disclosure does not impose any limitations.

[0144] Reference Figure 3 , Figure 3 This is a flowchart illustrating a device simulation method provided in an embodiment of the present disclosure. In one feasible implementation, the method includes:

[0145] S301. Establish a simulation model of the device under test (DUT). The DUT includes a first resistor and a parasitic resistance. The parasitic resistance includes a second resistor and a contact resistance. The first resistor is the bulk resistance of the DUT, the second resistor is the terminal resistance of the DUT, and the contact resistance is the equivalent resistance of the contact plug on the DUT.

[0146] In some embodiments, the device under test can be a resistor.

[0147] Optionally, the above resistors can be N+ silicide polysilicon resistors, P+ silicide polysilicon resistors, N+ silicide diffusion resistors, P+ silicide diffusion resistors, etc., or they can be N+ non-silicide polysilicon resistors, P+ non-silicide polysilicon resistors, N+ non-silicide diffusion resistors, P+ non-silicide diffusion resistors, etc.

[0148] In addition, the resistors mentioned above can also be thermistors, photoresistors, varistors, etc., and no limitation is made in the embodiments disclosed herein.

[0149] To better understand the embodiments of this disclosure, an N+ diffusion resistor is used as an example, with reference to... Figure 4 , Figure 4 This is a schematic diagram of a longitudinal section of a device under test provided in an embodiment of this disclosure. Figure 2 .exist Figure 4 In the above-mentioned device under test, the device under test includes: a P-type substrate 100 (P-substrate, abbreviated as Psub), a P-well structure 200 (abbreviated as PWell), a shallow trench isolation structure 300 (shallow trench isolation, abbreviated as STI), an N+ injection region, several contact plugs 400 located at both ends, and metal leads 500.

[0150] Among them, the contact plug 400 is located above the N+ injection region and forms ohmic contact with the N+ injection region.

[0151] In this embodiment, the contact end portion formed by connecting the two ends of the above resistor with contact plugs and metal leads will generate fixed terminal resistance and contact resistance respectively.

[0152] In this embodiment, when establishing a simulation model of the resistor, the working principle of the resistor can be used as a basis, starting from the physical equation of the resistor, to obtain the simulation model and model parameters.

[0153] In one feasible implementation, the resistance of the device under test can be divided into a first resistance Rpure (or bulk resistance) and a parasitic resistance. At the same time, the parasitic resistance can be further divided into a second resistance Rend and a contact resistance Rlicon.

[0154] Volume resistance can be understood as the ratio of the DC voltage between the two contact terminals of a resistor to the current flowing through it, and its unit is ohms.

[0155] Wherein, the second resistor Rend is the terminal resistance of the device under test, and the contact resistance Rlicon is the equivalent resistance of the contact plug 400 on the device under test.

[0156] It is understandable that, since resistors are generally passive symmetrical structures, the two second resistors Rend have the same resistance value, and the two contact resistors Rlicon also have the same resistance value.

[0157] To better understand this embodiment, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the equivalent resistance of a device under test provided in an embodiment of this disclosure. Figure 5 In the above-mentioned device under test, the equivalent resistance includes the first resistance Rpure and the parasitic resistance Rext, i.e., Rtotal = Rpure + 2 * Rext. The parasitic resistance Rext can be further divided into the contact resistance Rlicon and the second resistance Rend, i.e.:

[0158] Rext=Rend+Rlicon=Rend+Rlicon' / N

[0159] Where N represents the number of the aforementioned contact plugs on one contact terminal of the device under test, and N is an integer greater than or equal to 1. For example... Figure 6 As shown, Figure 6 This is a schematic diagram of a device under test provided in an embodiment of this disclosure. Figure 2 When a device under test has two contact plugs on one contact end, it is equivalent to two contact resistors connected in parallel. The contact resistance becomes smaller, and the equivalent resistance is equal to Rlicon' / N.

[0160] In this embodiment, after determining the above simulation model, the resistance values ​​of the contact resistance Rlicon and the second resistance Rend are calculated using a preset calculation method and added to the simulation model of the device under test.

[0161] S302. Determine the temperature coefficients of resistance for the first resistor, the second resistor, and the contact resistor, and add them to the simulation model.

[0162] Among them, the resistance of a metal has a linear relationship with its temperature in the range near room temperature. Therefore, the temperature coefficient of resistance can be used to characterize the relationship between the resistance of a metal and its temperature.

[0163] In this embodiment, assuming that under the current ambient temperature under test, the temperature coefficient of resistance of the first resistor Rpure is TC_Rpure, the temperature coefficient of resistance of the second resistor Rend is TC_Rend, and the temperature coefficient of resistance of the contact resistor Rlicon is TC_Rlicon, then the equivalent resistance Rtotal of the device under test can be expressed as:

[0164] Rtotal=Rpure*TC_Rpure+2*(Rend*TC_Rend+Rlicon*TC_Rlicon)

[0165] S303. Based on the above simulation model, perform SPICE device simulation.

[0166] In this embodiment of the disclosure, after establishing a simulation model of the device under test and determining the parameters in the simulation model, SPICE device simulation is performed based on the simulation model to obtain the simulation results of the device under test.

[0167] Optionally, the calculated resistance values ​​of the first resistor Rpure, contact resistance Rlicon, and second resistor Rend, as well as the corresponding temperature coefficients of resistance Rpure, contact resistance Rlicon, and second resistor Rend, can be added to the sub-circuit model in the SPICE model for simulation. When simulating the resistance values ​​of devices under test of different sizes, the simulation model calculates Rpure, Rend, and Rlicon to obtain the resistance values ​​of the devices under test of the corresponding sizes, thereby reducing the error of the simulation results.

[0168] In the SPICE model, a macro model is typically used to fit the resistor. The macro model allows for the addition of custom parameters to fit various characteristics of the resistor, such as its characteristics under different temperatures and operating voltages.

[0169] For example, nonlinear DC analysis, nonlinear transient analysis, and linear AC analysis can be performed on the circuit. The simulation content is not limited in the embodiments of this disclosure.

[0170] The device simulation method provided in this disclosure divides the resistance of the device under test into bulk resistance and parasitic resistance, and further divides the parasitic resistance into terminal resistance and contact resistance. By analyzing and calculating the test results, the resistance values ​​of the bulk resistance, terminal resistance and contact resistance, as well as the resistance temperature coefficients corresponding to the bulk resistance, terminal resistance and contact resistance, can be obtained. This can accurately establish a simulation model of the device under test, thereby effectively improving the simulation accuracy of the device under test.

[0171] Based on the content described in the above embodiments, referring to Figure 7 , Figure 7 This is a schematic diagram of a sub-process of a device simulation method provided in an embodiment of this disclosure. In some embodiments, the process of establishing a simulation model of the device under test includes:

[0172] S701, Determine multiple sampling temperatures T1, T2, ..., T n .

[0173] In this embodiment of the disclosure, multiple temperature values ​​can be randomly selected as sampling temperatures within a commonly used test temperature range.

[0174] For example, in some embodiments, 25°C, 50°C, and 98°C can be selected as sampling temperatures T1, T2, and T3, respectively.

[0175] S702. Determine the functional relationship between the resistance of the device under test and the first length at each sampling temperature, wherein the first length is the length of the device under test on the layout.

[0176] In this embodiment of the disclosure, the resistance value Rtotal of the device under test is the sum of the resistance value of the first resistor Rpure and the parasitic resistance Rext, that is:

[0177] Rtotal = Rpure + 2Rext

[0178] The resistance value of the first resistor Rpure can be determined in the following way:

[0179] Rpure = Rs_pure * (L / W)

[0180] Where Rs_pure represents the sheet resistance of the first resistor Rpure; W is the width of the device under test on the layout, and L is the length of the device under test on the layout.

[0181] Among them, sheet resistance, also known as film resistance, is the resistance of a square semiconductor thin layer in the direction of current flow, and its unit is ohm / square, or simply ohm / sq.

[0182] In one feasible implementation, the resistance value Rtotal of the device under test and the first length L can be represented by a functional expression, namely:

[0183] Rtotal = Rs_pure * (L / W) + 2Rext

[0184] As can be seen from the above function expression, the resistance value Rtotal of the device under test is related to the width W and length L of the device under test on the layout, while the parasitic resistance Rext is not related to the width W and length L of the device under test on the layout.

[0185] In this embodiment of the disclosure, it can be determined that at the sampling temperature T i Below, the resistance value Rtotal(T) of the device under test i The functional relationship between ) and the first length L is:

[0186] Rtotal(T i =Rs_pure(T i )*(L / W)+2Rext

[0187] Among them, T i ∈(T1, T2, ..., T) n ), Rs_pure(T i ) indicates that at the sampling temperature T i Below, the first resistor is the sheet resistor of Rpure.

[0188] S703. Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, determine the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the parasitic resistance at each sampling temperature.

[0189] In one feasible implementation, the resistance of the device under test can be measured at each sampling temperature for the same width W but different first lengths L. Then, based on the multiple measurement results, the sheet resistance and parasitic resistance of the first resistor can be calculated at each sampling temperature.

[0190] For example, in one feasible implementation, the test environment temperature can be adjusted to the sampling temperature T1 first, and then the resistance of the device under test (DUT) can be detected when the DUT has the same width W but different first lengths L. Based on multiple measurement results, the sheet resistance Rs_pure(T1) and parasitic resistance Rext(T1) of the first resistor at the sampling temperature T1 can be calculated. Then, the test environment temperature can be adjusted to the sampling temperature T2, and the resistance of the DUT can be detected when the DUT has the same width W but different first lengths L. Based on multiple measurement results, the sheet resistance Rs_pure(T2) and parasitic resistance Rext(T2) of the first resistor at the sampling temperature T2 can be calculated. ... and so on, so that the sheet resistance and parasitic resistance of the first resistor at each sampling temperature can be determined.

[0191] Since the contact terminals of the device under test are in contact with the two ends of the first resistor Rpure, the square semiconductor thin layer appearing in the current direction is of the same structure. Therefore, the first resistor Rpure can be sampled at temperature T. i The sheet resistor Rs_pure(T) i The second resistor, Rend, is determined to be at the sampling temperature T. i The sheet resistor Rs_end(T) i ).

[0192] S704. Determine the contact resistance value based on the sheet resistance and parasitic resistance values ​​of the second resistor at each sampling temperature.

[0193] In one feasible implementation, after determining the sheet resistance of the second resistor Rend at each sampling temperature, the resistance value of the second resistor at each sampling temperature can be calculated based on the sheet resistance of the second resistor at each sampling temperature, the length of the contact of the device under test on the layout, and the width of the device under test on the layout.

[0194] In this embodiment, the parasitic resistance Rext is split into the second resistance Rend and the contact resistance Rlicon. Therefore, after determining the resistance values ​​of the parasitic resistance Rext and the second resistance Rend at each sampling temperature, the resistance value of the contact resistance Rlicon at each sampling temperature can be calculated based on the resistance values ​​of the parasitic resistance Rext and the second resistance Rend at each sampling temperature.

[0195] Based on the content described in the above embodiments, in some embodiments, when determining the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sampling temperature T is first determined. i Below, the resistance value Rtotal(T) of the device under test i The functional expression between ) and the first length L is:

[0196] Rtotal(T i =Rs_pure(T i )*(L / W)+2Rext

[0197] Among them, Rs_pure(T i ) indicates that at the sampling temperature T i The first resistor Rpure is the sheet resistance, W is the width of the device under test on the layout, and Rext represents the parasitic resistance.

[0198] As can be seen from the above function expression, at the same temperature, the resistance Rtotal of the device under test is related to the width W and length L of the device under test on the layout, while the parasitic resistance Rext is not related to the width W and length L of the device under test on the layout.

[0199] In one feasible implementation, the sampling temperature T can be... i Below, measurements were taken of the device under test at the same width W but different lengths L. x The resistance value Rtotal(L) at that time x ), and with length L x For the X-axis, the resistance value is Rtotal(L) x Plot the graph on the Y-axis and perform linear fitting to determine the sampling temperature T. i Below, the function curve of the resistance Rtotal of the device under test versus the first length L in the rectangular coordinate system.

[0200] The function curve can be used to determine the sampling temperature T. i Below, the functional relationship between the resistance Rtotal of the device under test and the first length L is defined.

[0201] To better understand the embodiments of this disclosure, please refer to... Figure 8 , Figure 8 This is a schematic diagram of the function curve between the resistance value of the device under test and the first length in an embodiment of this disclosure.

[0202] In one feasible implementation, the width of the device under test (DUT) on the layout is fixed at W0, and the length L of the DUT on the layout is set to L1, L2, L3, and L4, where the values ​​of L1, L2, L3, and L4 are all different and increase sequentially.

[0203] Maintaining the test environment temperature T as the sampling temperature T1, the resistance of the device under test (DUT) is measured when the width is W0 and the length is L1, L2, L3, and L4, respectively. In some embodiments, it is assumed that the resistance measured when using width W0 and length L1 is Rtotal(L1), the resistance measured when using width W0 and length L2 is Rtotal(L2), the resistance measured when using width W0 and length L3 is Rtotal(L3), and the resistance measured when using width W0 and length L4 is Rtotal(L4). A rectangular coordinate system is then established with the first length L as the X-axis and the resistance Rtotal as the Y-axis. Points are plotted in this rectangular coordinate system based on the resistance measured when the DUT uses different lengths, and linear fitting is performed to determine the function curve of the resistance Rtotal of the DUT versus the first length L in the rectangular coordinate system.

[0204] In this process, the resistance value Rtotal and the first length L are taken as the observed quantities. The optimal estimate of the parameter Rs_pure(T1) / W is sought through linear fitting, that is, the optimal theoretical curve Rtotal(T1)=Rs_pure(T1)*L / W+2Rext is sought.

[0205] like Figure 8 As shown, after linear fitting, Rtotal(T1) = 641.14*L + 493.41, from which we can conclude:

[0206] Rs_pure(T1) / W=641.14; 2Rext=493.41

[0207] The linear fitting method described above can establish data relationships (mathematical models) based on given discrete data points, and find a series of tiny straight line segments to connect these interpolation points into a curve. As long as the interval between the interpolation points is chosen properly, a smooth function curve can be formed, which can be represented by a function or parametric equation.

[0208] Optionally, curve fitting can be performed using the least squares method or MATLAB software. This embodiment does not limit the specific curve fitting method.

[0209] Using the same method, the function curve of the resistance of the device under test versus the first length in a preset rectangular coordinate system can be obtained at any sampling temperature.

[0210] To better understand the embodiments of this disclosure, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the function curves between the resistance of the device under test and the first length at different sampling temperatures in this embodiment of the present disclosure.

[0211] In one feasible implementation, after determining the function curve between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the parasitic resistance at each sampling temperature can be determined based on the function relationship.

[0212] For example, it can be first based on the sampling temperature T i Below, the resistance value Rtotal(T) of the device under test i The functional relationship between the first resistor Rpure and the first length L determines the sheet resistance Rs_pure(T) of the first resistor Rpure. i ), and the parasitic resistance value Rext(T) i Then, based on the sheet resistance Rs_pure(T) of the first resistor Rpure, i Determine the sheet resistance Rs_end(T) of the second resistor. i ).

[0213] Among them, T i ∈(T1, T2, ..., T) n ).

[0214] In one feasible implementation, the resistance value Rtotal(T) of the device under test can be determined first. i The slope K(T) of the functional relationship between ) and the first length L i ) and intercept B(T i ), due to the resistance Rtotal(T) of the device under test i The functional relationship between ) and the first length L is:

[0215] Rtotal(T i =Rs_pure(T i )*L / W+2Rext(T i )

[0216] Therefore, we can conclude that:

[0217] K(T i =Rs_pure(T i ) / W

[0218] B(T i ) = 2Rext(T i )

[0219] Further calculations yield the following:

[0220] Rs_pure(T i )=K(T i )*W

[0221] Rext(T i )=B(T i ) / 2

[0222] Where W is the width of the device under test on the layout.

[0223] For example, refer to Figure 9 At sampling temperature T1, curve fitting was performed on the measured resistance values ​​of multiple devices under test (DUTs) with W = 0.33 μm. The resulting function curve between the resistance value Rtotal(T1) of the DUT and the first length L was determined as follows:

[0224] Rtotal(T1) = 641.14 * L + 493.41

[0225] Therefore, the slope K(T1) of the above function curve can be determined to be 641.14, and the intercept B(T) is... i The value is 493.41.

[0226] Further calculations yield the following:

[0227] Rs_pure(T1)=K(T1)*W=641.14*0.33≈211.6(ohm / sq)

[0228] Rext(T1)=B(T1) / 2=493.41 / 2≈246.7(ohm)

[0229] Similarly, based on the sampling temperature T2, and using Rtotal(T2) = 663.76*L + 494.46, we can determine that:

[0230] Rs_pure(T2)=K(T2)*W=663.76*0.33≈219.0(ohm / sq)

[0231] Rext(T2)=B(T2) / 2=494.46 / 2≈247.2(ohm)

[0232] Similarly, based on the sampling temperature T3, and using Rtotal(T3) = 705.32 * L + 497.18, we can determine that:

[0233] Rs_pure(T3)=K(T3)*W=705.32*0.33≈232.8(ohm / sq)

[0234] Rext(T3)=B(T3) / 2=497.18 / 2≈248.6(ohm)

[0235] In one feasible implementation, since the contact terminals of the device under test are in contact with the two ends of the first resistor Rpure, the square semiconductor thin layer presented in the current direction is of the same structure. Therefore, the first resistor Rpure can be sampled at temperature T. i The sheet resistor Rs_pure(T) i The second resistor, Rend, is determined to be at the sampling temperature T. i The sheet resistor Rs_end(T) i ),Right now:

[0236] Rs_end(T i =Rs_pure(T i )

[0237] In one feasible implementation, after determining the second resistance Rend at the sampling temperature T i The sheet resistor Rs_end(T) i Then, through further calculations, the second resistance Rend at the sampling temperature T can be determined. i The resistance value below is:

[0238] Rend(T i =Rs_end(T i )*L_end / W

[0239] Where L_end represents the length of the contact end of the device under test on the layout, and W represents the width of the device under test on the layout.

[0240] In one feasible implementation, the length L_end of the contact terminal of the device under test on the layout and the second resistor can both be used as simulation parameters. Therefore, the length L_end of the contact terminal of the device under test on the layout can be customized, and no limitation is made in this embodiment.

[0241] In one feasible implementation, the length L_end of the contact end of the device under test on the layout can also be the length between one side of the contact end of the device under test and one side of the device under test on the layout.

[0242] To better understand this embodiment, an N+ diffusion resistor is used as an example, referring to... Figure 10 , Figure 10 This is a schematic diagram of the length of the contact terminal of a device under test (DUT) provided in an embodiment of this disclosure on a layout. Figure 1 .exist Figure 10 In this context, the length between one side of the inner side of the contact end of the device under test (DUT) and one side of the DUT on the outer side of the layout can be used as the length L_end of the contact end of the DUT on the layout.

[0243] In another feasible implementation, the length L_end of the contact end of the device under test on the layout can be the length between the two sides of the contact end of the device under test.

[0244] To better understand the embodiments of this disclosure, the N+ diffusion resistor is still used as an example in these embodiments, referring to... Figure 11 , Figure 11 This is a schematic diagram of the length of the contact terminal of a device under test (DUT) provided in an embodiment of this disclosure on a layout. Figure 2 .exist Figure 11 In this context, the length between the inner side of the contact end of the device under test (DUT) and the outer side of the contact end of the DUT can be used as the length L_end of the contact end of the DUT on the layout.

[0245] In one feasible implementation, after determining the resistance of the second resistor Rend and the parasitic resistance Rext at each sampling temperature, the resistance of the contact resistor Rlicon at each sampling temperature can be calculated based on the resistance of the second resistor Rend and the parasitic resistance Rext at each sampling temperature.

[0246] In one feasible implementation, due to the sampling temperature T i Below, Rext(T) i =Rend(T) i )+Rlicon(T i Therefore, it can be calculated that:

[0247] Rlicon(T i ) = Rext(T i )-Rend(T i ) = Rext(T i )-Rs_end(T i )*L_end / W

[0248] When the number N of contact plugs on one contact terminal of the device under test is greater than or equal to 2, at the sampling temperature T i Below, the resistance of a single contact plug is:

[0249] Rlicon'(T i ) = Rlicon(T i )*N

[0250] The device simulation method provided in this embodiment divides the equivalent resistance of the device under test (DUT) into bulk resistance and parasitic resistance, and further decomposes the parasitic resistance into terminal resistance and contact resistance. When establishing the simulation model of the DUT, the terminal resistance and contact resistance can be calculated separately using a preset algorithm based on the function curve between the resistance value of the DUT and the length of the DUT on the layout. During simulation, the terminal resistance and contact resistance are added to the SPICE model, which can reduce the error of the simulation results and improve the simulation accuracy of the DUT.

[0251] Based on the content described in the above embodiments, after determining each sampling temperature T1, T2, ..., T... n Below, the sheet resistances of the first resistor, pure, are Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(T... n After that, the sampling temperature T can be used. i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T. i The first sheet resistance Rs_pure(T) i ) and reference sampling temperature T j The first sheet resistor Rs_pure(T) j Plotting the quotient of ) on the Y-axis and performing linear fitting, the temperature coefficient of resistance TC_Rpure(T) of the first resistor pure is determined. i ) and sampling temperature T i The function curve.

[0252] Among them, T i T j ∈(T1, T2, ..., T) n ).

[0253] To better understand the embodiments of this disclosure, please refer to... Figure 12 , Figure 12 This is a schematic diagram of the function curve of the temperature coefficient of resistance of the first resistor versus ambient temperature in an embodiment of this disclosure.

[0254] Assume T1 = 25℃, T2 = 50℃, T3 = 80℃, T4 = 98℃; Rs_pure(T1) = 211.6, Rs_pure(T2) = 219.0, Rs_pure(T3) = 228.9, Rs_pure(T4) = 232.8; the reference sampling temperature T j =T1=25℃.

[0255] With T i -T1 is the X-axis, and Rs_pure(T i Plotting ) / Rs_pure(T1) on the Y-axis and performing linear fitting, the temperature coefficient of resistance TC_Rpure(T) of the first resistor pure is determined. i ) and sampling temperature T i The function curve is:

[0256] TC_Rpure(T i )=0.0014*(T i -25)+1

[0257] After determining the temperature coefficient of resistance TC_Rpure(T) of the first resistor pure i ) and sampling temperature T i After obtaining the function curve, the function curve of the temperature coefficient of resistance TC_Rpure(t) of the first resistor pure versus the ambient temperature t can be determined as follows:

[0258] TC_Rpure(t) = 0.0014 * (tT) j )+1

[0259] The temperature coefficient of resistance of the first resistor, pure, can be calculated from this function curve at any ambient temperature.

[0260] In one feasible implementation, since the contact terminals of the device under test are in contact with the two ends of the first resistor Rpure, the square semiconductor thin layer presented in the current direction has the same structure. Therefore, the temperature coefficient of resistance of the first resistor Rpure at ambient temperature t can be determined as the temperature coefficient of resistance of the second resistor Rend at ambient temperature t, that is:

[0261] TC_Rend(t) = TC_Rpure(t)

[0262] Based on the content described in the above embodiments, after determining each sampling temperature T1, T2, ..., T... n Below, the contact resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(T) are... n After that, the sampling temperature T can be used. i Compared with the reference sampling temperature Tj The difference is taken as the X-axis, with the sampling temperature T. i The resistance of the lower contact resistance Rlicon(T) i ) and reference sampling temperature T j The resistance of the lower contact resistance Rlicon(T) j Plot the quotient of ) on the Y-axis and perform linear fitting to determine the temperature coefficient of resistance Rlicon, TC_Rlicon(T). i ) and sampling temperature T i The function curve.

[0263] Among them, T i T j ∈(T1, T2, ..., T) n ).

[0264] To better understand the embodiments of this disclosure, please refer to... Figure 13 , Figure 13 This is a schematic diagram of the function curve of the temperature coefficient of resistance of the contact resistance versus the ambient temperature in an embodiment of this disclosure.

[0265] Assume T1 = 25℃, T2 = 50℃, T3 = 80℃, T4 = 98℃; Rlicon(T1) = 182.6, Rlicon(T2) = 180.9, Rlicon(T3) = 178.9, Rlicon(T4) = 178.1; the reference sampling temperature T j =T1=25℃.

[0266] With T i -T1 is the X-axis, and Rlicon(T) is the X-axis. i Plotting Rlicon(T1) on the Y-axis and performing linear fitting, the temperature coefficient of resistance Rlicon, TC_Rlicon(T), is determined. i ) and sampling temperature T i The function curve is:

[0267] TC_Rlicon(T i ) = -0.0004*(T i -25)+1

[0268] After determining the temperature coefficient of resistance Rlicon, TC_Rlicon(T) i ) and sampling temperature T i After obtaining the function curve, the function curve of the temperature coefficient of resistance Rlicon, TC_Rlicon(t), versus the ambient temperature t can be determined as follows:

[0269] TC_Rlicon(t)=-0.0004*(t-Tj)+1

[0270] The temperature coefficient of resistance of the contact resistance Rlicon at any ambient temperature can be calculated from this function curve.

[0271] The device simulation apparatus provided in this embodiment divides the resistance of the device under test into bulk resistance and parasitic resistance when establishing a simulation model of the device under test. The parasitic resistance is further divided into terminal resistance and contact resistance. Based on the test results, the resistance values ​​of the bulk resistance, terminal resistance and contact resistance are analyzed and calculated. The resistance temperature coefficients corresponding to the bulk resistance, terminal resistance and contact resistance are also calculated. This allows for the accurate establishment of a simulation model of the device under test, thereby effectively improving the simulation accuracy of the device under test.

[0272] Based on the content described in the above embodiments, this disclosure also provides a device simulation apparatus. (Refer to...) Figure 14 , Figure 14 This is a schematic diagram of the program modules of a device simulation apparatus provided in an embodiment of the present disclosure. In one feasible implementation, the device simulation apparatus includes:

[0273] The processing module 1401 is used to establish a simulation model of the device under test, which includes a first resistor and a parasitic resistance, the parasitic resistance including a second resistor and a contact resistance; wherein, the first resistor is the bulk resistance of the device under test, the second resistor is the terminal resistance of the device under test, and the contact resistance is the equivalent resistance of the contact plug on the device under test.

[0274] The calculation module 1402 is used to determine the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and to add the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor to the simulation model.

[0275] Simulation module 1403 is used to perform SPICE device simulation based on the above simulation model.

[0276] The device simulation apparatus provided in this embodiment divides the resistance of the device under test into bulk resistance and parasitic resistance when establishing a simulation model of the device under test. The parasitic resistance is further divided into terminal resistance and contact resistance. The resistance values ​​of the bulk resistance, terminal resistance and contact resistance are analyzed and calculated based on the test results. The resistance temperature coefficients corresponding to the bulk resistance, terminal resistance and contact resistance are also calculated. This allows for the accurate establishment of a simulation model of the device under test, thereby effectively improving the simulation accuracy of the device under test.

[0277] In one feasible implementation, the processing module 1401 is specifically used for:

[0278] Determine multiple sampling temperatures T1, T2, ..., T n ;

[0279] Determine the functional relationship between the resistance of the device under test and a first length at each sampling temperature, where the first length is the length of the device under test on the layout;

[0280] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the resistance of the parasitic resistance are determined at each sampling temperature.

[0281] The resistance value of the contact resistance is determined based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature.

[0282] In one feasible implementation, the processing module 1401 is specifically used for:

[0283] At each sampling temperature, the resistance of the device under test is measured at different first lengths corresponding to the same width, where the width is the width of the device under test on the layout.

[0284] Plotting the first length as the X-axis and the resistance value as the Y-axis and performing linear fitting, the first function curve corresponding to the resistance value of the device under test and the first length in a preset rectangular coordinate system is determined at each sampling temperature.

[0285] In one feasible implementation, the processing module 1401 is specifically used for:

[0286] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor is determined at each sampling temperature.

[0287] Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the resistance value of the parasitic resistance at each sampling temperature is determined, wherein the resistance value of the parasitic resistance is independent of the first length;

[0288] The sheet resistance of the second resistor is determined based on the sheet resistance of the first resistor at each sampling temperature.

[0289] In one feasible implementation, the processing module 1401 is specifically used for:

[0290] Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The slope K(T) i), calculate at the sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ):

[0291] Rs_pure(T i )=K(T i )*W

[0292] Where W represents the width of the device under test on the layout, and T i ∈(T1, T2, ..., T) n ).

[0293] In one feasible implementation, the processing module 1401 is specifically used for:

[0294] Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The intercept B(T) i ), calculate at the sampling temperature T i The parasitic resistance value Rext(T) described below i ):

[0295] Rext(T i )=B(T i ) / 2

[0296] Among them, T i ∈(T1, T2, ..., T) n ).

[0297] In one feasible implementation, the processing module 1401 is specifically used for:

[0298] At sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ) is determined to be T at the sampling temperature i The sheet resistance Rs_end(T) of the second resistor i );

[0299] Among them, T i ∈(T1, T2, ..., T) n ).

[0300] In one feasible implementation, the processing module 1401 is specifically used for:

[0301] Calculate T at the sampling temperature as follows: i Below, the resistance value of the contact resistor is Rlicon(T) i ):

[0302] Rlicon(T i ) = Rext(T i )–Rs_end(T i )*L_end / W

[0303] Among them, Rext(T) i ) indicates that at the sampling temperature T i The parasitic resistance value described below, Rs_end(T i ) indicates that at the sampling temperature T i The second resistor is a sheet resistance, where L_end represents the length of the contact terminal of the device under test on the layout, W represents the width of the device under test on the layout, and T... i ∈(T1, T2, ..., T) n ).

[0304] In one feasible implementation, when the number N of the contact plugs on one contact terminal of the device under test is greater than or equal to 2, at the sampling temperature T i The resistance value of the next single contact plug is Rlicon'(T) i )for:

[0305] Rlicon'(T i ) = Rlicon(T i )*N

[0306] In one feasible implementation, the computing module 1402 is specifically used for:

[0307] The temperature coefficient of resistance corresponding to the first resistor shall be determined in the following manner:

[0308] Based on the sampling temperatures T1, T2, ..., T... n Below, the sheet resistances of the first resistor are Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(T... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T. i The sheet resistance Rs_pure(T) of the first resistor i ) and the reference sampling temperature T j The sheet resistance Rs_pure(T) of the first resistor j Plotting the quotient of ) on the Y-axis and performing linear fitting, we determine the second function curve of the temperature coefficient of resistance of the first resistor versus the ambient temperature, where T j ∈(T1, T2, ..., T) n );

[0309] Based on the second function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the first resistor is determined.

[0310] In one feasible implementation, the calculation module 1402 is specifically used to: calculate the temperature coefficient of resistance TC_Rpure(t) corresponding to the first resistor in the following manner:

[0311] TC_Rpure(t)=K1*(tT j )+C1

[0312] Where K1 is the slope of the second function curve, t represents the ambient temperature to be measured, and C1 represents the intercept of the second function curve.

[0313] In one feasible implementation, the calculation module 1402 is specifically configured to determine the temperature coefficient of resistance corresponding to the contact resistance in the following manner:

[0314] Based on the sampling temperatures T1, T2, ..., T... n Below, the contact resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(T) are... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T as the reference. i The contact resistance described below is Rlicon(T) i ) and the reference sampling temperature T j The contact resistance described below is Rlicon(T) j Plotting the quotient of ) on the Y-axis and performing linear fitting, the third function curve of the temperature coefficient of resistance of the contact resistance versus ambient temperature is determined, where T j ∈(T1, T2, ..., T) n );

[0315] Based on the third function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the contact resistance is determined.

[0316] In one feasible implementation, the calculation module 1402 is specifically configured to calculate the temperature coefficient of resistance TC_Rlicon(t) corresponding to the contact resistance in the following manner:

[0317] TC_Rlicon(t)=K2*(tT j )+C2

[0318] Wherein, K2 is the slope of the third function curve, t represents the ambient temperature to be measured, and C2 is the intercept of the third function curve.

[0319] It should be noted that the specific execution of the processing module 1401, calculation module 1402, and simulation module 1403 described in the above embodiments can be found in each step of the device simulation method described in the above embodiments, and will not be repeated here.

[0320] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory to implement each step in the device simulation method described in the above embodiments, and the specific details can be referred to the description in the above embodiments, which will not be repeated here.

[0321] To better understand the embodiments of this disclosure, please refer to... Figure 15 , Figure 15 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0322] like Figure 15 As shown, the electronic device 15 of this embodiment includes: a processor 1501 and a memory 1502; wherein:

[0323] Memory 1502 is used to store instructions executed by the computer;

[0324] The processor 1501 is used to execute computer execution instructions stored in the memory, and can implement each step of the device simulation method as described in the above embodiments. For details, please refer to the description in the above embodiments, which will not be repeated here.

[0325] Alternatively, the memory 1502 can be either standalone or integrated with the processor 1501.

[0326] When the memory 1502 is set up independently, the device also includes a bus 1503 for connecting the memory 1502 and the processor 1501.

[0327] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, each step in the device simulation method described in the above embodiments can be implemented. For details, please refer to the description in the above embodiments, which will not be repeated here.

[0328] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer program product, including a computer program. When the computer program is executed by a processor, it can implement each step of the device simulation method described in the above embodiments. For details, please refer to the description in the above embodiments, which will not be repeated here.

[0329] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0330] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0331] Furthermore, in each embodiment of this disclosure, the functional modules can be integrated into a single processing unit, or each module can exist physically separately, or two or more modules can be integrated into a single unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0332] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods described in each embodiment of this disclosure.

[0333] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the disclosed method can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0334] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0335] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0336] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0337] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0338] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0339] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A device simulation method, characterized in that, include: A simulation model of the device under test (DUT) is established. The DUT is a resistive device, comprising a first resistor and a parasitic resistance. The parasitic resistance comprises a second resistor and a contact resistance. The first resistor is the bulk resistance of the DUT, the second resistor is the terminal resistance of the DUT, and the contact resistance is the equivalent resistance of the contact plug on the DUT. The resistance value of the DUT is related to the resistance value of the first resistor and the parasitic resistance, and the resistance value of the contact resistance is related to the resistance value of the second resistor and the parasitic resistance. Determine the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and add the temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor to the simulation model; Based on the simulation model, perform simulation of general analog circuit simulator devices.

2. The method according to claim 1, characterized in that, The establishment of the simulation model of the device under test includes: Determine multiple sampling temperatures T1, T2, ..., T n ; Determine the functional relationship between the resistance of the device under test and a first length at each sampling temperature, where the first length is the length of the device under test on the layout; Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the resistance of the parasitic resistance are determined at each sampling temperature. The resistance value of the contact resistance is determined based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature.

3. The method according to claim 2, characterized in that, Determining the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes: At each sampling temperature, the resistance of the device under test is measured at different first lengths corresponding to the same width, where the width is the width of the device under test on the layout. Plotting the first length as the X-axis and the resistance value as the Y-axis and performing linear fitting, the first function curve corresponding to the resistance value of the device under test and the first length in a preset rectangular coordinate system is determined at each sampling temperature.

4. The method according to claim 3, characterized in that, The step of determining the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the parasitic resistance at each sampling temperature based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes: Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor is determined at each sampling temperature. Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the resistance value of the parasitic resistance at each sampling temperature is determined, wherein the resistance value of the parasitic resistance is independent of the first length; The sheet resistance of the second resistor is determined based on the sheet resistance of the first resistor at each sampling temperature.

5. The method according to claim 4, characterized in that, The step of determining the sheet resistance of the first resistor at each sampling temperature based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature includes: Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The slope K(T) i ), calculate at the sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ): Rs_pure(T i )=K(T i )×W Where W represents the width of the device under test on the layout, and T i ∈ (T1, T2, ..., T) n ).

6. The method according to claim 4, characterized in that, The step of determining the parasitic resistance value at each sampling temperature based on the functional relationship between the resistance value of the device under test and the first length at each sampling temperature includes: Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The intercept B(T) i ), calculate at the sampling temperature T i The parasitic resistance value Rext(T) described below i ): Rext(T i )=B(T i ) / 2 Among them, T i ∈ (T1, T2, ..., T) n ).

7. The method according to claim 4, characterized in that, Determining the sheet resistance of the second resistor at each sampling temperature based on the sheet resistance of the first resistor at each sampling temperature includes: At sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ) is determined to be T at the sampling temperature i The sheet resistance Rs_end(T) of the second resistor i ); Among them, T i ∈ (T1, T2, ..., T) n ).

8. The method according to claim 2, characterized in that, The step of determining the contact resistance value at each sampling temperature based on the sheet resistance and parasitic resistance values ​​of the second resistor at each sampling temperature includes: Calculate T at the sampling temperature as follows: i Below, the resistance value of the contact resistor is Rlicon(T) i ): Rlicon(T i )=Rext(T i )–Rs_end(T i )×L_end / W Among them, Rext(T) i ) indicates that at the sampling temperature T i The parasitic resistance value described below, Rs_end(T i ) indicates that at the sampling temperature T i The second resistor is a sheet resistance, where L_end represents the length of the contact terminal of the device under test on the layout, W represents the width of the device under test on the layout, and T... i ∈ (T1, T2, ..., T) n ).

9. The method according to claim 8, characterized in that, When the number N of the contact plugs on one contact terminal of the device under test is greater than or equal to 2, at the sampling temperature T i The resistance value of the next single contact plug is Rlicon'(T) i )for: Rlicon’(T i )=Rlicon(T i )×N。 10. The method according to claim 8, characterized in that, The temperature coefficient of resistance corresponding to the first resistor shall be determined in the following manner: Based on the sampling temperatures T1, T2, ..., T... n Below, the sheet resistances of the first resistor are Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(T... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T. i The sheet resistance Rs_pure(T) of the first resistor i ) and the reference sampling temperature T j The sheet resistance Rs_pure(T) of the first resistor j Plotting the quotient of ) on the Y-axis and performing linear fitting, we determine the second function curve of the temperature coefficient of resistance of the first resistor versus the ambient temperature, where T j ∈ (T1, T2, ..., T) n ); Based on the second function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the first resistor is determined.

11. The method according to claim 10, characterized in that, The step of determining the temperature coefficient of resistance corresponding to the first resistor based on the second function curve and the ambient temperature to be measured includes: The temperature coefficient of resistance TC_Rpure(t) corresponding to the first resistor is calculated as follows: TC_Rpure(t)=K1×(t-T j )+C1 Where K1 is the slope of the second function curve, t represents the ambient temperature to be measured, and C1 represents the intercept of the second function curve.

12. The method according to claim 11, characterized in that, The temperature coefficient of resistance of the first resistor is the same as that of the second resistor.

13. The method according to claim 8, characterized in that, The temperature coefficient of resistance corresponding to the contact resistance is determined as follows: Based on the sampling temperatures T1, T2, ..., T... n Below, the contact resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(T) are... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T as the reference. i The contact resistance described below is Rlicon(T) i ) and the reference sampling temperature T j The contact resistance described below is Rlicon(T) j Plotting the quotient of ) on the Y-axis and performing linear fitting, the third function curve of the temperature coefficient of resistance of the contact resistance versus ambient temperature is determined, where T j ∈ (T1, T2, ..., T) n ); Based on the third function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the contact resistance is determined.

14. The method according to claim 13, characterized in that, The step of determining the temperature coefficient of resistance corresponding to the contact resistance based on the third function curve and the ambient temperature to be measured includes: The temperature coefficient of resistance TC_Rlicon(t) corresponding to the contact resistance is calculated as follows: TC_Rlicon(t)=K2×(t-T j )+C2 Wherein, K2 is the slope of the third function curve, t represents the ambient temperature to be measured, and C2 is the intercept of the third function curve.

15. A device simulation apparatus, characterized in that, The device includes: The processing module is used to establish a simulation model of the device under test (DUT), which is a resistive device. The DUT includes a first resistor and a parasitic resistance. The parasitic resistance includes a second resistor and a contact resistance. The first resistor is the bulk resistance of the DUT, the second resistor is the terminal resistance of the DUT, and the contact resistance is the equivalent resistance of the contact plug on the DUT. The resistance value of the DUT is related to the resistance value of the first resistor and the resistance value of the parasitic resistance. The resistance value of the contact resistance is related to the resistance value of the second resistor and the resistance value of the parasitic resistance. The calculation module is used to determine the resistance temperature coefficients corresponding to the first resistor, the second resistor, and the contact resistor, and add the resistance temperature coefficients corresponding to the first resistor, the second resistor, and the contact resistor to the simulation model; The simulation module is used to perform simulation of general analog circuit simulator devices based on the simulation model.

16. The apparatus according to claim 15, characterized in that, The processing module is specifically used for: Determine multiple sampling temperatures T1, T2, ..., T n ; Determine the functional relationship between the resistance of the device under test and a first length at each sampling temperature, where the first length is the length of the device under test on the layout; Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor, the sheet resistance of the second resistor, and the resistance of the parasitic resistance are determined at each sampling temperature. The resistance value of the contact resistance is determined based on the sheet resistance of the second resistor and the parasitic resistance at each sampling temperature.

17. The apparatus according to claim 16, characterized in that, The processing module is specifically used for: At each sampling temperature, the resistance of the device under test is measured at different first lengths corresponding to the same width, where the width is the width of the device under test on the layout. Plotting the first length as the X-axis and the resistance value as the Y-axis and performing linear fitting, the first function curve corresponding to the resistance value of the device under test and the first length in a preset rectangular coordinate system is determined at each sampling temperature.

18. The apparatus according to claim 17, characterized in that, The processing module is specifically used for: Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the sheet resistance of the first resistor is determined at each sampling temperature. Based on the functional relationship between the resistance of the device under test and the first length at each sampling temperature, the resistance value of the parasitic resistance at each sampling temperature is determined, wherein the resistance value of the parasitic resistance is independent of the first length; The sheet resistance of the second resistor is determined based on the sheet resistance of the first resistor at each sampling temperature.

19. The apparatus according to claim 18, characterized in that, The processing module is specifically used for: Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The slope K(T) i ), calculate at the sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ): Rs_pure(T i )=K(T i )×W Where W represents the width of the device under test on the layout, and T i ∈ (T1, T2, ..., T) n ).

20. The apparatus according to claim 18, characterized in that, The processing module is specifically used for: Based on the sampling temperature T i Below, the function curve L(T) of the resistance value of the device under test versus the first length in a preset rectangular coordinate system is shown. i The intercept B(T) i ), calculate at the sampling temperature T i The parasitic resistance value Rext(T) described below i ): Rext(T i )=B(T i ) / 2 Among them, T i ∈ (T1, T2, ..., T) n ).

21. The apparatus according to claim 18, characterized in that, The processing module is specifically used for: At sampling temperature T i The sheet resistance Rs_pure(T) of the first resistor i ) is determined to be T at the sampling temperature i The sheet resistance Rs_end(T) of the second resistor i ); Among them, T i ∈ (T1, T2, ..., T) n ).

22. The apparatus according to claim 16, characterized in that, The processing module is specifically used for: Calculate T at the sampling temperature as follows: i Below, the resistance value of the contact resistor is Rlicon(T) i ): Rlicon(T i )=Rext(T i )–Rs_end(T i )×L_end / W Among them, Rext(T) i ) indicates that at the sampling temperature T i The parasitic resistance value described below, Rs_end(T i ) indicates that at the sampling temperature T i The second resistor is a sheet resistance, where L_end represents the length of the contact terminal of the device under test on the layout, W represents the width of the device under test on the layout, and T... i ∈ (T1, T2, ..., T) n ).

23. The apparatus according to claim 22, characterized in that, When the number N of the contact plugs on one contact terminal of the device under test is greater than or equal to 2, at the sampling temperature T i The resistance value of the next single contact plug is Rlicon'(T) i )for: Rlicon’(T i )=Rlicon(T i )×N。 24. The apparatus according to claim 22, characterized in that, The calculation module is specifically used for: The temperature coefficient of resistance corresponding to the first resistor shall be determined in the following manner: Based on the sampling temperatures T1, T2, ..., T... n Below, the sheet resistances of the first resistor are Rs_pure(T1), Rs_pure(T2), ..., Rs_pure(T... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T. i The sheet resistance Rs_pure(T) of the first resistor i ) and the reference sampling temperature T j The sheet resistance Rs_pure(T) of the first resistor j Plotting the quotient of ) on the Y-axis and performing linear fitting, we determine the second function curve of the temperature coefficient of resistance of the first resistor versus the ambient temperature, where T j ∈ (T1, T2, ..., T) n ); Based on the second function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the first resistor is determined.

25. The apparatus according to claim 24, characterized in that, The calculation module is specifically used for: The temperature coefficient of resistance TC_Rpure(t) corresponding to the first resistor is calculated as follows: TC_Rpure(t)=K1×(t-T j )+C1 Where K1 is the slope of the second function curve, t represents the ambient temperature to be measured, and C1 represents the intercept of the second function curve.

26. The apparatus according to claim 25, characterized in that, The temperature coefficient of resistance of the first resistor is the same as that of the second resistor.

27. The apparatus according to claim 22, characterized in that, The calculation module is specifically used for: The temperature coefficient of resistance corresponding to the contact resistance is determined as follows: Based on the sampling temperatures T1, T2, ..., T... n Below, the contact resistances Rlicon(T1), Rlicon(T2), ..., Rlicon(T) are... n ), with sampling temperature T i Compared with the reference sampling temperature T j The difference is taken as the X-axis, with the sampling temperature T as the reference. i The contact resistance described below is Rlicon(T) i ) and the reference sampling temperature T j The contact resistance described below is Rlicon(T) j Plotting the quotient of ) on the Y-axis and performing linear fitting, the third function curve of the temperature coefficient of resistance of the contact resistance versus ambient temperature is determined, where T j ∈ (T1, T2, ..., T) n ); Based on the third function curve and the ambient temperature to be measured, the temperature coefficient of resistance corresponding to the contact resistance is determined.

28. The apparatus according to claim 27, characterized in that, The calculation module is specifically used for: The temperature coefficient of resistance TC_Rlicon(t) corresponding to the contact resistance is calculated as follows: TC_Rlicon(t)=K2×(t-T j )+C2 Wherein, K2 is the slope of the third function curve, t represents the ambient temperature to be measured, and C2 is the intercept of the third function curve.

29. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the device simulation method as described in any one of claims 1 to 14.

30. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the device simulation method as described in any one of claims 1 to 14.

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