A SiC MOSFET board-level package optimization design method

Abstract

The application relates to a SiC MOSFET FOPLP (Field-Effect Power Large Package) optimization design method, which comprises the following steps: designing an orthogonal test, wherein the design variable is the thickness of different structure layers in the SiC MOSFET FOPLP; performing finite element simulation on the SiC MOSFET FOPLP to obtain a comprehensive regression equation of parasitic inductance, thermal strain and thermal resistance and the thickness of different structure layers; based on the comprehensive regression equation, a multi-objective optimization model is established, and the optimal thickness parameters of different structure layers are obtained by solving the multi-objective optimization model. Compared with the prior art, the application can perform multi-objective optimization design on the structure of the SiC MOSFET FOPLP, improve the thermal, mechanical and inductance performance of the device, effectively reduce the data amount required for optimization design, and has the advantages of high efficiency and convenience.

Description

Technical Field

[0001] This invention relates to the field of SiC MOSFET packaging technology, and in particular to a SiC MOSFET board-level packaging optimization design method. Background Technology

[0002] Compared to silicon, silicon carbide (SiC) exhibits superior performance, such as high critical breakdown field strength, high thermal conductivity, and high electron saturation velocity. Therefore, SiC MOSFETs offer advantages over Si-MOSFETs in terms of high switching speed, high junction temperature operation, and low power loss, resulting in significantly increased energy density and reduced weight and size. Currently, SiC MOSFETs are widely used in major industries such as automotive, motorcycles, and energy.

[0003] High-quality packaging is essential for enabling the functionality of SiC MOSFET dies. The package ensures a reliable electrical connection between the chip and the terminals, dissipates heat generated within the chip, and provides mechanical robustness and protection for operation under harsh conditions.

[0004] However, existing SiC MOSFETs are typically packaged using wire-bonded packages developed for Si semiconductor power devices. Wire-bonded packages have inductances as high as 10 nH. High di / dt is generated during high-frequency switching, and voltage overshoot and oscillations caused by this high parasitic inductance can lead to increased power loss, electromagnetic interference, and even thermal breakdown of the chip. Furthermore, the source voltage variation caused by high source parasitic inductance significantly affects the device's drive voltage (gate-source voltage), which can lead to incorrect switching states.

[0005] Most SiC or Si-based devices have junction temperatures between 150°C and 175°C. Theoretically, SiC chip devices can operate stably at temperatures above 320°C. Therefore, low-melting-point solder paste used in Si devices is not suitable for SiC devices. It can be said that SiC MOSFET packaging should meet the following requirements: (1) small package parasitic parameters to ensure switching speed; (2) low package thermal resistance for rapid heat dissipation; (3) high-temperature packaging materials to enable the device to operate at high temperatures; and (4) high fatigue stress resistance to resist periodic temperature changes.

[0006] Existing design methods mainly improve the thermal, mechanical, and inductive performance of SiC MOSFETs by modifying the packaging process of FOPLP (Fan-out Panel Level Package), but it is difficult to improve its thermal, mechanical, and inductive performance simultaneously. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art by providing a SiC MOSFET board-level package optimization design method, which can perform multi-objective optimization design of the SiC MOSFET FOPLP structure and improve the thermal, mechanical and inductive performance of the device.

[0008] The objective of this invention can be achieved through the following technical solution: a SiC MOSFET board-level package optimization design method, comprising the following steps:

[0009] S1. Design an orthogonal experiment, where the design variable is the thickness of different structural layers in the SiC MOSFET FOPLP;

[0010] S2. Finite element simulation of SiC MOSFET FOPLP was performed to obtain the comprehensive regression equations of parasitic inductance, thermal strain and thermal resistance with different structural layer thicknesses.

[0011] S3. Based on the comprehensive regression equation in step S2, establish a multi-objective optimization model. By solving the multi-objective optimization model, obtain the optimal thickness parameters of different structural layers.

[0012] Furthermore, the different structural layers include a substrate, solder, chip, and RDL (Re-Distribution Layer).

[0013] Furthermore, the orthogonal experiment designed in step S1 includes 16 sets of experimental data.

[0014] Furthermore, step S2 specifically includes the following steps:

[0015] S21. Parasitic inductance is extracted by electromagnetic simulation using the finite element method / boundary element method.

[0016] The finite element method was used to simulate thermal strain and thermal resistance through thermal resistance simulation and thermodynamic simulation, respectively.

[0017] S22. Combining 16 sets of experimental data, statistical software was used to obtain the influence curves between different structural layer thicknesses and parasitic inductance, thermal strain, and thermal resistance.

[0018] S23. Based on the influence change curve in step S22, construct a comprehensive regression equation for parasitic inductance, thermal strain, and thermal resistance with different structural layer thicknesses using a quaternion quadratic polynomial function.

[0019] Furthermore, the material parameters set in the electromagnetic simulation in step S21 include the relative permittivity e, the relative permeability μ, and the electrical conductivity σ;

[0020] The parameters set in the thermal resistance simulation in step S21 include the heat power generated inside the mold and the conduction current / resistance.

[0021] The material parameters set in the thermodynamic simulation in step S21 include thermal conductivity k, coefficient of thermal expansion CTE, Young's modulus E, and Poisson's ratio v.

[0022] Furthermore, step S23 specifically includes the following steps:

[0023] S231. Normalize the parasitic inductance, thermal strain, and thermal resistance values. Using quaternion quadratic polynomial functions, establish regression equations for the normalized parasitic inductance, thermal strain, and thermal resistance with respect to different structural layer thicknesses.

[0024] S232. Add the three regression equations obtained in step S231 to obtain the comprehensive regression equation.

[0025] Furthermore, the comprehensive regression equation is specifically as follows:

[0026] I(x1,x2,x3,x4)=L(x1,x2,x3,x4)+ε(x1,x2,x3,x4)+R(x1,x2,x3,x4)

[0027] Where I(x1,x2,x3,x4) is the comprehensive regression function, L(x1,x2,x3,x4) is the normalized parasitic inductance regression function with respect to different structural layer thicknesses, ε(x1,x2,x3,x4) is the normalized thermal strain regression function with respect to different structural layer thicknesses, R(x1,x2,x3,x4) is the normalized thermal resistance regression function with respect to different structural layer thicknesses, and x1,x2,x3,x4 are the thicknesses of the substrate, solder, chip, and RDL, respectively.

[0028] Furthermore, the multi-objective optimization model in step S3 is specifically as follows:

[0029]

[0030] Where, x 1min x 1max These represent the preset minimum and maximum values ​​for the substrate thickness, respectively, x. 2min x 2max These are the preset minimum and maximum values ​​for solder thickness, respectively, x. 3min x 3max These are the preset minimum and maximum values ​​for chip thickness, respectively, x 4min x 4max These are the preset minimum and maximum values ​​for RDL thickness, respectively.

[0031] Furthermore, step S3 specifically involves using a genetic algorithm to solve the multi-objective optimization model.

[0032] Furthermore, the specific process of solving the multi-objective optimization model in step S3 is as follows:

[0033] Set the genetic algorithm parameters, including: code base, number of decimal places, population size, and mutation rate;

[0034] Using a uniform crossover method, the crossover rate is set.

[0035] The optimal solution is obtained by using the absolute parent optimal selection method, which is the optimal thickness value of the substrate, solder, chip and RDL.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] I. This invention uses different structural layer thicknesses as design variables. By designing orthogonal experiments, the amount of data required in the optimization design can be greatly reduced, which has the advantages of high efficiency and convenience. This invention combines orthogonal experimental design data to perform finite element simulation on SiCMOSFET FOPLP. By obtaining the comprehensive regression equations of parasitic inductance, thermal strain, and thermal resistance with different structural layer thicknesses, a multi-objective optimization model is further established. Solving this multi-objective optimization model can obtain the optimal thickness parameters of different structural layers, thereby achieving the goal of simultaneously optimizing the thermal, mechanical, and inductive performance of SiC MOSFET FOPLP.

[0038] Second, this invention normalizes the inductance, thermal strain, and thermal resistance values ​​and establishes regression equations for each normalized inductance, thermal strain, and thermal resistance with respect to different structural layer thicknesses using a quaternary quadratic polynomial function. This allows for a good dynamic description of the normalization performance as a function of influencing factors (inductance, thermal strain, and thermal resistance), thus ensuring the construction of an accurate and effective comprehensive regression equation, which is beneficial for establishing a reliable multi-objective optimization model.

[0039] Third, this invention uses a genetic algorithm to solve a multi-objective optimization model, which further improves the accuracy of the solution results and can obtain the optimal thickness parameters for different structural layers. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0041] Figure 2 This is a schematic diagram illustrating the application process of an example.

[0042] Figure 3 This is a cross-sectional view of a SiC MOSFET FOPLP.

[0043] Figure 4a The curves showing the changes in parasitic inductance, thermal strain, and thermal resistance as a function of substrate thickness in the embodiment are shown.

[0044] Figure 4b The curves showing the effect of solder thickness on parasitic inductance, thermal strain, and thermal resistance in the embodiment are shown.

[0045] Figure 4c The curves showing the changes in parasitic inductance, thermal strain, and thermal resistance due to chip thickness in the embodiment are shown.

[0046] Figure 4d The curves showing the effect of RDL thickness on parasitic inductance, thermal strain, and thermal resistance in the embodiment are shown.

[0047] Figure 5 This is a schematic diagram showing the comparison between the actual normalized value and the predicted normalized value in the example. Detailed Implementation

[0048] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0049] Example

[0050] like Figure 1 As shown, a SiC MOSFET board-level package optimization design method includes the following steps:

[0051] S1. Design an orthogonal experiment, where the design variable is the thickness of different structural layers in the SiC MOSFET FOPLP;

[0052] S2. Finite element simulation of SiC MOSFET FOPLP was performed to obtain the comprehensive regression equations of parasitic inductance, thermal strain and thermal resistance with different structural layer thicknesses.

[0053] S3. Based on the comprehensive regression equation in step S2, establish a multi-objective optimization model. By solving the multi-objective optimization model, obtain the optimal thickness parameters of different structural layers.

[0054] This embodiment applies the above technical solution, and the main application process is as follows: Figure 2 As shown:

[0055] (1) SiC MOSFET FOPLP structure

[0056] Figure 3The structure of the SiC MOSFET FOPLP is demonstrated. The device consists of a substrate (lead frame), solder, a SiC MOSFET chip (1200V / 136A / 12mΩ, 5*5*0.15mm in size, from ROHM SEMICONDUCTOR), an RDL (Relative Thermal Limit), an epoxy molding compound (EMC), and a top heatsink. The substrate and RDL are made of copper. This leadless package uses RDLs instead of bonding wires for chip connection. Both the top heatsink and the solder pads allow heat to dissipate into the environment, achieving double-sided cooling.

[0057] (2) Orthogonal experimental design

[0058] An orthogonal experimental approach was used to evaluate the performance of SiC MOSFET FOPLPs with different layer thicknesses. Four different substrate (x1), solder (x2), chip (x3), and RDL (x4) thicknesses were selected, resulting in 256 different combinations. To reduce the experimental workload, an orthogonal experimental design was employed, requiring only 16 sets of experiments to evaluate these combinations. The L16 orthogonal array (4...) 4 As shown in Table 1.

[0059] Table 1 L16 Orthogonal Experiment Table

[0060]

[0061] (3) Simulation of SiC MOSFET FOPLP performance

[0062] Parasitic inductance (L), thermal strain (ε), and thermal resistance (R) significantly affect the operating capability and reliability of SiC MOSFET FOPOPs. Parasitic inductance was extracted using the finite element method (F / BE). Thermal strain and thermal resistance were simulated using the finite element method. In the thermal resistance simulation, the heat power generated within the mold was set to 58.5 W, and the conduction current / resistance was set to 70 A / 12 mΩ. The material parameters used in the thermodynamic simulation included thermal conductivity (k), coefficient of thermal expansion (CTE), Young's modulus (E), and Poisson's ratio (v) (see Table 2). The material parameters used in the electromagnetic simulation included relative permittivity (e), relative permeability (μ), and conductivity (σ), as shown in Table 3.

[0063] Table 2 Thermal and mechanical parameters of the materials

[0064]

[0065] Table 3 Electrical parameters of materials

[0066]

[0067] (4) Analysis of orthogonal experiment results

[0068] Simulation was used to obtain the L, ε, and R values ​​corresponding to various schemes in the orthogonal array L16. The effects of x1, x2, x3, and x4 on L, ε, and R were analyzed using statistical software (MiniTap). The results are as follows: Figures 4a-4d As shown

[0069] (5) Multi-objective optimization method

[0070] All three parameters (L, ε, and R) significantly affect the FOPLP of SiC MOSFETs. Therefore, this technical solution proposes a multi-objective optimization method combining regression curves and a genetic algorithm, which can simultaneously improve all three performance parameters.

[0071] Assume that L, ε, and R are of equal importance, but their values ​​differ significantly. Therefore, it is necessary to normalize the values ​​of L, ε, and R. Establish functions of each normalized L, ε, and R with respect to x1, x2, x3, and x4. Based on equation (1), a quaternion quadratic polynomial function is proposed as a regression curve to link the three performance parameters with the four factors.

[0072] Quaternion quadratic polynomial function:

[0073] z(x1,x2,x3,x4)=a1x1+a2x2+a3x3+a4x4+a5x1x2

[0074] +a6x1x3+a7x1x4+a8x2x3+a9x2x4+a 10 x3x4+a 11 x1 2

[0075] +a 12 x2 2 +a 13 x3 2 +a 14 x4 2 (1)

[0076] Where z represents each normalized L, ε or R, a1 to a 14 These are the fitting parameters related to the normalized performance. After fitting, the fitting parameter values ​​(a1-a) for each normalized performance are obtained. 14 The fitting results for normalized L, ε, and R are shown in Table 4. It can be noted that each normalized performance fit achieved an R-value higher than 0.99. 2 value.

[0077] Table 4 shows the fitting results of the quaternion quadratic polynomial function to the normalization performance.

[0078] <![CDATA[a1]]> 3.262 10.720 5.222 19.204 <![CDATA[a2]]> 1.068 -5.275 0.377 -3.83 <![CDATA[a3]]> 2.643 3.778 4.020 10.441 <![CDATA[a4]]> -0.250 4.648 -1.544 2.854 <![CDATA[a5]]> -0.434 6.203 1.533 7.302 <![CDATA[a6]]> -0.110 9.494 0.909 10.293 <![CDATA[a7]]> -0.015 2.674 -0.188 2.471 <![CDATA[a8]]> -5.002 -23.923 -11.879 -40.804 <![CDATA[a9]]> 1.938 12.064 6.545 20.547 <![CDATA[a 10 ]]> -0.899 3.060 -0.363 1.798 <![CDATA[a 11 ]]> -4.843 -22.757 -10.325 -37.925 <![CDATA[a 12 ]]> -0.501 11.276 -0.186 10.589 <![CDATA[a 13 ]]> -2.886 -11.306 -6.771 -20.963 <![CDATA[a 14 ]]> 0.542 2.636 1.348 4.526 <![CDATA[R 2 ]]> 0.999 0.995 0.999 /

[0079] Figure 5 The normalized actual and predicted values ​​of L, ε, and R were compared, and the predicted values ​​showed good agreement with the actual values ​​obtained from the orthogonal experiment. This indicates that the quaternary quadratic polynomial function proposed in this technical solution is suitable for dynamically describing the changes in normalization performance with influence factors (L, ε, R).

[0080] Let the sum of the three regression functions [L(x1, x2, x3, x4), ε(x1, x2, x3, x4), R(x1, x2, x3, x4)] be denoted as the comprehensive regression function I(x1, x2, x3, x4) that simultaneously considers L, ε, and R. The formula for calculating the comprehensive regression function is as follows:

[0081] I(x1,x2,x3,x4)=

[0082] L(x1,x2,x3,x4)+ε(x1,x2,x3,x4)+R(x1,x2,x3,x4) (2)

[0083] The parameters of I(x1, x2, x3, x4) are shown in Table 4. By calculating the extreme points of the curves, multi-objective optimization of L, ε, and R was achieved. The mathematical model for multi-objective optimization is expressed as:

[0084]

[0085] Equation (3) was solved using a genetic algorithm. The parameters of the genetic algorithm were set as follows: code base = 10, decimal places = 4, population size = 100, mutation rate = 0.01, uniform crossover method was adopted, crossover rate = 0.85, and absolute parent optimal selection method was adopted. The optimal solution was obtained by the genetic algorithm, that is, x1, x2, x3, and x4 are 0.4, 0.17, 0.1, and 0.2 mm, respectively.

[0086] Table 5 compares the performance of SiC MOSFET FOPLP before and after multi-objective optimization. The results show that the optimal structural parameters can be obtained when L, ε, and R are optimal. After optimization, L, ε, and R are reduced by 14.79%, 8.96%, and 9.28%, respectively.

[0087] Table 5 Performance Comparison Before and After Optimization

[0088]

[0089] In summary, this technical solution, on the one hand, greatly reduces the amount of data required in the optimization design through orthogonal experimental design, and on the other hand, can simultaneously improve the thermal, mechanical and inductive performance of SiC MOSFET FOPLP by constructing and solving a multi-objective optimization model.

Claims

1. A SiC MOSFET board-level package optimization design method, characterized in that, Includes the following steps: S1. Design an orthogonal experiment, where the design variable is the thickness of different structural layers in the SiC MOSFET FOPLP; S2. Finite element simulation of SiC MOSFET FOPLP was performed to obtain the comprehensive regression equations of parasitic inductance, thermal strain and thermal resistance with different structural layer thicknesses. Specifically, the following steps are included: S21. Parasitic inductance is extracted by electromagnetic simulation using the finite element method / boundary element method. The finite element method was used to simulate thermal strain and thermal resistance through thermal resistance simulation and thermodynamic simulation, respectively. S22. Combining 16 sets of experimental data, statistical software was used to obtain the influence curves between different structural layer thicknesses and parasitic inductance, thermal strain, and thermal resistance. S23. Based on the influence change curve in step S22, construct a comprehensive regression equation for parasitic inductance, thermal strain, and thermal resistance with different structural layer thicknesses using a quaternion quadratic polynomial function. Step S23 specifically includes the following steps: S231. Normalize the parasitic inductance, thermal strain, and thermal resistance values. Using quaternion quadratic polynomial functions, establish regression equations for the normalized parasitic inductance, thermal strain, and thermal resistance with respect to different structural layer thicknesses. S232. Add the three regression equations obtained in step S231 to obtain the comprehensive regression equation, which is as follows: in, For the comprehensive regression function, The regression function for normalized parasitic inductance with respect to different structural layer thicknesses is given by... The regression function for normalized thermal strain with respect to different structural layer thicknesses is given by... The normalized thermal resistance is a regression function with respect to different structural layer thicknesses. These are the thicknesses of the substrate, solder, chip, and RDL, respectively. S3. Based on the comprehensive regression equation in step S2, a multi-objective optimization model is established. By solving the multi-objective optimization model, the optimal thickness parameters for different structural layers are obtained. The multi-objective optimization model is as follows: in, , These are the preset minimum and maximum values ​​for the substrate thickness, respectively. , These are the preset minimum and maximum values ​​for solder thickness, respectively. , These are the preset minimum and maximum values ​​for chip thickness, respectively. , These are the preset minimum and maximum values ​​for RDL thickness, respectively.

2. The SiC MOSFET board-level package optimization design method according to claim 1, characterized in that, The different structural layers include a substrate, solder, chip, and RDL.

3. The SiC MOSFET board-level package optimization design method according to claim 2, characterized in that, The orthogonal experiment designed in step S1 includes 16 sets of experimental data.

4. The SiC MOSFET board-level package optimization design method according to claim 1, characterized in that, The material parameters set in the electromagnetic simulation in step S21 include the relative permittivity e, the relative permeability μ, and the electrical conductivity σ. The parameters set in the thermal resistance simulation in step S21 include the heat power generated inside the mold and the conduction current / resistance. The material parameters set in the thermodynamic simulation in step S21 include thermal conductivity k, coefficient of thermal expansion CTE, Young's modulus E, and Poisson's ratio v.

5. The SiC MOSFET board-level package optimization design method according to claim 1, characterized in that, Step S3 specifically involves using a genetic algorithm to solve the multi-objective optimization model.

6. The SiC MOSFET board-level package optimization design method according to claim 5, characterized in that, The specific process of solving the multi-objective optimization model in step S3 is as follows: Set the genetic algorithm parameters, including: code base, number of decimal places, population size, and mutation rate; Using a uniform crossover method, the crossover rate is set. The optimal solution, i.e. the optimal thickness value of different structural layers, is obtained by using the absolute parent optimal selection method.

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