Method to reduce design violations due to ir drop

Abstract

The present disclosure relates to methods of reducing design violations due to IR drop. One method includes identifying a cell in a layout as a violation cell that fails one or more design rules related to IR drop and classifying a root cause of the violation cell with a root cause category. The method also includes determining a search area to search for a safe region candidate and finding a selected cell to move based on the root cause category of the root cause. The method also includes finding a safe region in the search area to move the selected cell and moving the selected cell to the safe region if the safe region is found within the search area.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to methods for reducing design violations caused by IR drop. Background Technology

[0002] Recent trends in integrated circuit (IC) miniaturization have resulted in smaller devices that consume less power and deliver more functionality at higher speeds. Miniaturization processes have also led to more stringent design and manufacturing specifications and challenges in reliability. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits, while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for designing a layout of an integrated circuit is provided, the method comprising: identifying cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; classifying root causes leading to the non-compliant cells using root cause categories; determining a search region to search for safe region candidates; identifying selected cells for movement based on the root cause categories of the root causes; identifying safe regions in the search region to move the selected cells; and moving the selected cells to the safe regions if the safe regions are found in the search region.

[0004] According to one aspect of this disclosure, a system for designing a layout of an integrated circuit is provided, the layout being stored on a non-transitory computer-readable medium. The system includes at least one processor and at least one memory, the at least one memory including computer program code of one or more programs, and wherein the at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform the following operations: identifying cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR drop; classifying root causes leading to the non-compliant cells using root cause categories; determining a search region to search for safe zone candidates; identifying selected cells for movement based on the root cause categories of the root causes; identifying safe zones in the search region to move the selected cells; and moving the selected cells to the safe zone if the safe zone is found in the search region.

[0005] According to one aspect of this disclosure, a method for designing a layout of an integrated circuit is provided, the method comprising: identifying cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR drop; classifying each of the one or more root causes leading to the non-compliant cells using a corresponding root cause category; determining a search region to search for safe region candidates; identifying a safe region in the search region to eliminate a selected root cause; identifying a selected cell for movement based on the corresponding root cause category of the selected root cause; and moving the selected cell to the safe region if the safe region is found in the search region. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a flowchart of a method for classifying the root causes of violations according to some embodiments.

[0008] Figure 2 This is a schematic diagram of the cell locations distributed in the search area according to some embodiments.

[0009] Figure 3 This is a schematic diagram of a search area having multiple analysis zones according to some embodiments.

[0010] Figures 4A to 4B This is a schematic diagram of the cell layout arrangement before and after adjacent cells are moved, according to some embodiments.

[0011] Figures 5A to 5B This is a schematic diagram of the cell layout arrangement before and after adjacent cells are moved into the keep-out area, according to some embodiments.

[0012] Figures 6A to 6B This is a schematic diagram of the cell layout arrangement before and after adjacent cells are moved, according to some embodiments.

[0013] Figures 7A to 7B This is a schematic diagram of the cell layout arrangement before and after adjacent cells are moved into the blocking area, according to some embodiments.

[0014] Figures 8A to 8B This is a schematic diagram of the cell layout arrangement before and after the violation cell and adjacent cells are moved, according to some embodiments.

[0015] Figure 9 This is a flowchart of a method for designing a layout diagram of an integrated circuit according to some embodiments.

[0016] Figure 10 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are also contemplated. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, for ease of description, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to describe the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0020] In some embodiments, when the EDA program finds a cell that fails the IR drop test in the layout diagram, it identifies the failed cell as a non-compliant cell and categorizes the root cause leading to the non-compliant cell. The EDA program also determines a search area for finding safe zones, which are locations in the layout diagram where placing a cell will not result in a design violation due to IR drop. Based on the categorization of the root cause, the EDA program then locates a selected cell for movement. If a safe zone is found within the search area, the EDA program moves the selected cell to that safe zone. Because the EDA program is implemented with mitigation processes to eliminate some of the root causes leading to non-compliant cells, the number of design violations due to IR drop in the layout diagram that require manual user inspection is reduced.

[0021] Figure 1 This is a flowchart of a method 100 for classifying the root causes of violations according to some embodiments. Figure 1 The order in which the operations of method 100 are described is for illustrative purposes only; the operations of method 100 can be performed in a different manner than described above. Figure 1 The described sequence of execution. It should be understood that it is possible to... Figure 1 Other operations are performed before, during, and / or after the method 100 described herein, and only briefly described in this document.

[0022] In operation 110 of method 100, non-compliant cells in the layout diagram are identified. Each identified non-compliant cell fails to comply with one or more design rules associated with IR voltage drop. In some embodiments, each non-compliant cell is located in a power domain having a higher supply voltage VDD and a lower supply voltage VSS. In some embodiments, these non-compliant cells are distributed across two different power domains. Some non-compliant cells are in a first power domain, and some non-compliant cells are in a second power domain. The first power domain has a first higher supply voltage VDD1 and a first lower supply voltage VSS1. The second power domain has a second higher supply voltage VDD2 and a second lower supply voltage VSS2. In some embodiments, the first higher supply voltage VDD1 is different from the second higher supply voltage VDD2, and the first lower supply voltage VSS1 is different from the second lower supply voltage VSS2. In some embodiments, the first lower supply voltage VSS1 is the same as the second lower supply voltage VSS2. In some embodiments, each of the first lower supply voltage VSS1 and the second lower supply voltage VSS2 is equal to ground voltage GND. In some embodiments, non-compliant cells are distributed across three or more different power domains.

[0023] In operations 120, 130, and 140, the root cause leading to the non-compliant unit identified in operation 110 is analyzed. In operation 120 of method 100, the IR resistance value of the non-compliant unit is compared with the reference value (labeled R) in operation 120. high (Diagnosis) is compared. If the IR resistance value is greater than the reference value, the root cause of the faulty cell is the resistivity category, which is marked as high resistivity in operation 125. The process then proceeds to operation 130. In some embodiments, the IR resistance value selected for comparison in operation 120 is the effective resistance R related to the supply voltages VSS and VDD of the power domain used to power the faulty cell. eff The value of . In some embodiments, the effective resistance R eff The ratio between the voltage difference (VDD-VSS) and the current IDD flowing from the power rail of the higher supply voltage VDD into the non-compliant cell is expressed as equation R. eff = (VDD - VSS) / IDD. In some embodiments, the effective resistance R eff The ratio between the voltage difference (VDD-VSS) and the current ISS flowing from the non-compliant cell into the power rail with the lower supply voltage VSS is expressed as equation R. eff = (VDD - VSS) / ISS. In some embodiments, the effective resistance R eff The ratio between the voltage difference (VDD-VSS) and the average values ​​of the currents IDD and ISS is expressed as equation R. eff =2(VDD-VSS) / (IDD+ISS).

[0024] In some embodiments, the effective resistance R eff With critical resistance value R spec Compare. If R eff Greater than R spec The root cause of the non-compliant unit is the resistivity category. Figure 1 Illustration 128 depicts an example cell arrangement when the root cause of the non-compliant cell is resistivity class. In illustration 128, non-compliant cell 101 and three other cells (cell 1, cell 2, and cell 3) are placed in a selected area of ​​the layout diagram. Figure 1 In the middle, the effective resistance R eff The resistance quality factor used in operation 120, and the effective resistance R eff The critical resistance value R spec In comparison, the resistance quality factor is a physical quantity used to determine whether the root cause of a faulty cell is a resistivity-type issue. In some alternative embodiments, the effective conductance G... eff =1 / R eff It is used as the resistance quality factor in operation 120. If the effective conductance Geff Less than the critical conductivity value G spec The root cause of the non-compliant unit is the resistivity category. Other choices of the resistance quality factor are also within the scope of this disclosure.

[0025] In operation 130 of method 100, I is determined near the violating unit. peak Cell density. Used to determine I peak I of unit density peak Each cell is either a violating cell or a neighboring cell adjacent to a violating cell. In some embodiments, whether a given cell is counted as I... peak The cell depends on current IDD and / or current ISS, where current IDD is the current flowing into a given cell from the power rail for the higher supply voltage VDD, and current ISS is the current flowing into a given cell from the power rail for the lower supply voltage VSS. In some embodiments, if the current IDD flowing from the power rail into the selected cell is greater than a critical current value I... spec Then the selected unit is I. peak Unit. In some embodiments, if the current ISS flowing from the selected unit into the power rail is greater than the critical current value I... spec Then the selected unit is I. peak Unit. In some embodiments, if each of the currents IDD and ISS is greater than the critical current value I... spec Then the selected unit is I. peak unit.

[0026] In operation 130, if I peak If the number of units is greater than 1, the root cause of the violation is the cluster class, which was marked as a cluster in operation 135. Then, the processing flow proceeds to operation 140. Figure 1 Illustration 138 depicts the violation unit 101 and two adjacent units 192 and 194 adjacent to the violation unit 101. Because the violation unit 101 has as I peak The two adjacent units of the unit (i.e., 192 and 194) are the root cause of the violation in unit 101, which is the cluster category.

[0027] In operation 140 of method 100, if I peak The number of units is equal to 1 and is unique. peak If the unit is the violating unit itself, then the root cause of the violating unit is the self-induced class, which is marked as self-induced in operation 145. On the other hand, if I peak The number of units is equal to 1 and is unique. peakIf a cell is an adjacent cell to a violating cell, then the root cause of the violating cell is the disturbed class, which is marked as disturbed in operation 155. Figure 1 Illustration 148 depicts as I peak The violating unit 101 in illustration 148 is caused by a self-induced category. Figure 1 Illustration 158 depicts the violation unit 101 and as I peak The neighboring cell 192. The root cause of the violation cell 101 in illustration 158 is the disturbed category.

[0028] exist Figure 1 During the processing flow, the root causes leading to the non-compliant cells identified in operation 110 are categorized into various root cause categories. Possible root cause categories for non-compliant cells include resistivity categories, clustering categories, self-induced categories, and disturbed categories. In some embodiments, the non-compliant cells identified in operation 110 are modified by the EDA program to automatically mitigate design violations associated with IR drop. In some embodiments, the algorithm or method used to correct the IR drop problem in a given non-compliant cell depends on the category of each root cause leading to the IR drop problem in the given non-compliant cell. Different root cause categories specify different algorithms or methods for correcting IR drop problems. The IR drop problem requiring correction is either a dynamic IR (“DIR”) drop problem or a static IR (“SIR”) drop problem. In this disclosure, problems arising from one or more design violations associated with IR drop are generally referred to as DIR / SIR problems.

[0029] The static IR drop is the average voltage drop of the design. It depends on the RC of the power grid connecting the power supply to each standard cell. The average current depends entirely on the time period. Gate-channel leakage current is the primary cause of the static IR drop. The dynamic IR drop is the voltage drop caused by current flow when the circuit switches while performing some function.

[0030] In some embodiments, when the EDA program determines that the root cause category of the faulty cell is resistivity, the EDA program automatically begins searching for a safe area in the search region around the faulty cell. If the EDA program finds a safe area, it moves the faulty cell to the safe area to correct the DIR / SIR problem associated with the faulty cell. Figure 2 This is a schematic diagram of safe zone candidates 211-222 distributed in a search area 200 surrounding the violation unit 101, according to some embodiments. Figure 2In this embodiment, the violation unit 101 is located at the center of the search area 200. In some alternative embodiments, the search area 200 still surrounds the violation unit 101, but the violation unit 101 is not located at the center of the search area 200. In some embodiments, the violation unit 101 is horizontally offset relative to the center of the search area 200. In some embodiments, the violation unit 101 is vertically offset relative to the center of the search area 200. In some embodiments, the violation unit 101 is offset both horizontally and vertically relative to the center of the search area 200.

[0031] exist Figure 2 In the search area 200, the safe zone for moving the violation unit 101 is determined based on the resistance quality factor. Figure 2 In the diagram, the resistance quality factor of the cell used to characterize each candidate safe zone is a relative number, and the relative number used to characterize the non-compliant cell 101 is 100%. The percentage sign "%" in each relative number is not explicitly stated in the diagram. Figure 2 This is clearly shown in the text. For example, the relative number 100% is... Figure 2 The value is displayed as 100. In some embodiments, the resistance quality factor (“RFM”) of the selected cell is the ratio between the effective resistance of the selected cell and the effective resistance of the non-compliant cell 101, denoted as R. eff (Selected unit) / R eff (The non-compliant cell) is multiplied by 100%. Alternatively, the resistive quality factor (“RFM”) of the selected cell is the ratio between the effective conductance of the non-compliant cell 101 and the effective conductance of the selected cell, denoted as G. eff (Violation Unit) / G eff (Selected unit) multiplied by 100%. Figure 2 In the context of the safety zone candidates, the RFM values ​​of the cells at 211, 212, 213, and 214 are 85%, 75%, 75%, and 89%, respectively. The RFM values ​​of the cells at 215, 216, 217, and 218 are 89%, 85%, 89%, and 87%, respectively. The RFM values ​​of the cells at 219, 220, 221, and 222 are 87%, 85%, 85%, and 80%, respectively.

[0032] In some embodiments, after the EDA program classifies the root cause of the non-compliant cell 101 into a resistivity category, a search region 200 is automatically generated by the EDA program, and then safe zone candidates within the search region 200 are determined by the EDA program. The RFM value of the cell at each safe zone candidate is calculated. In some embodiments, one or more safe zone candidates with the minimum RFM value are selected. In some embodiments, when multiple safe zone candidates are found to have the minimum RFM value, a safe zone candidate placed near a high-current cell is rejected. For example, in search region 200, each of safe zone candidates 212 and 213 corresponds to a 75% RFM value. The cell placed at safe zone candidate 213 is close to the high-current cell at safe zone candidate 211. Therefore, only safe zone candidate 212 is found as a safe zone, provided that the cell at safe zone candidate 212 does not suffer from additional DIR / SIR problems. After the EDA program finds the safe zone at candidate safe zone 212, the EDA program moves the violating unit 101 to the safe zone at candidate safe zone 212, such as... Figure 2 As depicted in the text.

[0033] exist Figure 2 In the specific example shown, the search region 200 has a width and height of 10 micrometers. In some embodiments, most cells in the search region 200 have a uniform height “h” extending in the Y direction, and the height of the search region 200 ranges from 10h to 100h. In some embodiments, most cells in the search region 200 include gate conductors extending in the Y direction, which form the gate terminals of various transistors. Two adjacent gate conductors are separated from each other by a spacing distance along the X direction (which is perpendicular to the Y direction), and the spacing distance between two adjacent gate conductors in the search region 200 is typically equal to one CPP (“Contacted Poly Pitch”). In some embodiments, the width of the search region 200 ranges from 50 CPP to 500 CPP. Typically, each of the width and height of the search region 200 needs to be large enough to include safe zone candidates in the same power domain as the power domain of the violating cell 101. For example, if the layout region near the violating cell 101 includes both the core power domain and the I / O power domain, if the violating cell 101 is in the I / O power domain, then safe region candidates in the core power domain are excluded from safe region selection; conversely, if the violating cell 101 is in the core power domain, then safe region candidates in the I / O power domain are excluded from safe region selection. Typically, the speed performance requirements of EDA programs impose upper limits on the width and height of the search region 200, because increasing the size of the search region 200 also increases the time required for the EDA program to find the safe region using some implementations of the algorithm.

[0034] In some embodiments, with improvements to the algorithm, the time required to find the safe zone via the EDA procedure is reduced (even if the size of the search area 200 remains unchanged). Reference Figure 3 One of the improved algorithms for finding safe zones is described. Figure 3 This is a schematic diagram of a search area 200 having multiple analysis zones according to some embodiments. Figure 3 In this search area 200, the violating cell 101 is initially located at the violation point in the center of the search area 200. Before the EDA program begins searching for safe regions in the search area 200, the search area 200 is divided into sixteen analysis regions. These sixteen analysis regions include four analysis regions 311-314 in the first row, four analysis regions 321-324 in the second row, four analysis regions 331-334 in the third row, and four analysis regions 341-344 in the fourth row. In some embodiments, after determining the cell density in each of the sixteen analysis regions, the EDA program first searches for a safe region with the lowest cell density in the analysis region, and then searches for a safe region with the second lowest cell density. The EDA program continues searching analysis regions sequentially in increasing cell density order in each subsequent analysis region until a safe region is found. In some embodiments, after a safe region is found, the EDA program automatically moves the violating cell 101 to the safe region. Figure 3 The search area 200 is provided as an example of a particular embodiment with sixteen analysis regions. In some alternative embodiments, the search area 200 is divided into more than sixteen analysis regions. In some alternative embodiments, the search area 200 is divided into fewer than sixteen analysis regions.

[0035] In some embodiments, when the EDA program determines that the root cause category of the non-compliant cell is a cluster category, the EDA program automatically selects the adjacent cell with the highest peak current as the selected cell for relocation. The EDA program moves the adjacent cell with the highest peak current to a safe area or to a blocking area to correct the DIR / SIR problem. The blocking area for a given cell is an area used to place the given cell, which has a surrounding area that surrounds the given cell to physically separate the given cell from other cells in the layout diagram.

[0036] Figures 4A to 4B This is a schematic diagram of the cell layout before and after adjacent cells are removed from the violating cell, according to some embodiments, when the root cause of the violating cell belongs to the cluster category. Figure 4A In the layout, the non-compliant unit 101 is adjacent to two neighboring units 192 and 194. In some embodiments, after identifying the non-compliant unit 101 in the layout diagram, the peak current I in one or more neighboring units is determined. peak .exist Figure 4A In the middle, the peak current I in two adjacent units 192 and 194 peak Correspondingly, this equals 150uA and 260uA. In some embodiments, the peak current I of the cell... peak The measured current IDD is the current flowing into the cell from the power rail used for the higher supply voltage VDD. In some embodiments, the peak current I of the cell is... peak The measured current ISS is the current flowing from a given cell into the power rail used for the lower supply voltage VSS. In some embodiments, the peak current I of the cell is... peak It is the average of current IDD and current ISS.

[0037] In some embodiments, determining the peak current I in adjacent cells peak Next, the neighboring cell with the highest peak current among all adjacent cells is selected, and this selected neighboring cell is moved from the violating cell to the safe area. Moving the neighboring cell with the highest peak current is more effective in resolving DIR / SIR problems associated with violating cells because a larger peak current results in a larger IR voltage drop in the violating cell. Figure 4A In this process, the adjacent cell 194, with a peak current of 260uA, is moved away from the violating cell 101. The adjacent cell 194 is moved to... Figure 4A or Figure 4B The safety zone is not shown in the diagram. After the adjacent cell 194, with a peak current of 260uA, is removed from the violating cell 101, as... Figure 4B As shown, only one adjacent unit 192 remains adjacent to the violating unit 101.

[0038] In some embodiments, when all neighboring cells near the violating cell are data cells, the neighboring cell with the highest peak current is selected and moved away from the violating cell. In some embodiments, however, when the neighboring cells near the violating cell include both data cells and clock cells, the selection of the neighboring cell to be moved depends on the time effect caused by the change in the position of the clock cell. If the time effect of moving the clock cell is unrestricted, the neighboring cell with the highest peak current is selected and moved away from the violating cell, regardless of whether the neighboring cell with the highest peak current is a data cell or a clock cell. On the other hand, if the time effect of moving the clock cell is restricted, the clock cell is not allowed to be moved, and one of the data cells is selected to move it; under this restriction, the neighboring data cell with the highest peak current among all neighboring data cells is selected for movement, even if the peak current of one or more clock cells is greater than the peak current of the data cell selected for movement.

[0039] In some embodiments, before moving a selected neighboring cell to a safe zone, the EDA program identifies the safe zone by searching a search area around the offending cell. Before moving, the EDA program ensures that the selected neighboring cell being moved to the safe zone will not suffer from DIR / SIR problems and will not be moved to a power domain different from the previous power domain of the selected neighboring cell. For example, the selected neighboring cell placed in the safe zone does not interact with any I... peak The resistance quality factor (e.g., effective resistance R) of selected adjacent cells placed in the safe zone. eff (This does not indicate a design violation.)

[0040] In some embodiments, when the search safe zone in the search area around the offending cell does not return any valid safe zone to move the selected neighboring cell of the offending cell, the EDA procedure places the selected neighboring cell in the blocking area, thereby reducing the contributing effect of the leakage current of the selected neighboring cell on the DIR / SIR problem. Figures 5A to 5B This is a schematic diagram of the cell layout arrangement before and after moving adjacent cells into the blocking area when the root cause of the violation cell belongs to the cluster category, according to some embodiments.

[0041] Figure 5A The layout and arrangement of various units in Figure 4A The same as in. In Figure 4A and Figure 5A Of the two, the violating unit 101 is adjacent to neighboring units 192 and 194. Each of the neighboring units 192 and 194 is I. peak The peak current I in cells 192 and 194, and adjacent cells 192 and 194. peak Correspondingly, this equals 150uA and 260uA. (And...) Figure 5A Compared to the layout in the middle, Figure 5B The positions of the violating unit 101 and the adjacent unit 192 remained unchanged. However, Figure 5B The adjacent cell 194 is moved into the blocking region 510. Because the adjacent cell 194 has the highest peak current among the adjacent cells adjacent to the violating cell 101, the adjacent cell 194 is selected to be moved into the blocking region 510.

[0042] In some embodiments, when the EDA program determines that the root cause category of the violating unit is a disturbed category, the EDA program automatically selects the violating unit or a neighboring unit as the selected unit for movement. In some embodiments, after selecting a neighboring unit for movement, the EDA program also uses it as an I... peak The adjacent cells of the cell are moved to the safe zone or to the blocking zone, thereby correcting the error caused by I. peakThe DIR / SIR problem caused by the cell. In some embodiments, after selecting the offending cell for movement, the EDA procedure moves the offending cell to a safe area, thereby correcting the DIR / SIR problem caused by the cell. peak The unit caused the DIR / SIR problem.

[0043] Figures 6A to 6B This is a schematic diagram of the cell layout arrangement before and after the adjacent cells are removed from the violating cell, according to some embodiments, when the root cause of the violating cell belongs to the disturbance category. Figure 6A The layout includes a non-compliant cell 101 and an adjacent cell 192. The peak current I of the adjacent cell 192 is... peak Equal to 150μA. In some embodiments, the peak current I of the cell is... peak The measured current IDD is the current flowing into the cell from the power rail used for the higher supply voltage VDD. In some embodiments, the peak current I of the cell is... peak The measured current ISS is the current flowing from a given cell into the power rail used for the lower supply voltage VSS. In some embodiments, the peak current I of the cell is... peak It is the average of current IDD and current ISS. When the peak current I of adjacent cell 192 peak Greater than the critical current value I spec At that time, adjacent unit 192 is characterized as I peak Unit. Composed of I peak The DIR / SIR problem caused by the cell was eliminated after the adjacent cell 192 was removed from the offending cell 101. Figure 6B The layout after adjacent unit 192 has been removed is depicted. Figure 6B In the middle, there are no adjacent units near the violating unit 101.

[0044] In some embodiments, the adjacent cell 192 is moved after a safe zone is successfully found in the search area around the violating cell 101. In some embodiments, the adjacent cell 192 is a data cell, and the adjacent cell 192 is allowed to be moved to the safe zone by the EDA program. Examples of data cells include logic gate cells, such as buffer cells, inverter cells, NAND gate cells, NOR gate cells, AOI gate cells, and various flip-flop cells. In some embodiments, the adjacent cell 192 is a clock cell. Examples of clock cells include clock gating cells used in many synchronous circuits to reduce dynamic power consumption by removing the clock signal when the circuit is not in use. If the time impact of moving the adjacent cell 192 as a clock cell is within an acceptable range, the adjacent cell 192 is moved to the safe zone by the EDA program. In some embodiments, if the EDA program does not find a safe zone in the search area around the violating cell 101, the adjacent cell 192 is moved to the blocking area. In some embodiments, even if a safe zone is successfully found in the search area, the adjacent cell 192 is still moved to the blocking area if the time impact of moving the adjacent cell 192 as a clock cell is beyond an acceptable range.

[0045] Figure 7A This is a schematic diagram of the cell layout arrangement before the adjacent cell 192 is moved into the blocking area when the root cause of the violation cell belongs to the disturbance category, according to some embodiments. Figure 6A and Figure 7A The layouts depicted are identical, and each of these layouts includes a violation unit 101 and an adjacent unit 192. Figure 7B This is a schematic diagram of the cell layout arrangement before and after the adjacent cell 192 is moved into the blocking area, according to some embodiments, when the root cause of the violation cell belongs to the disturbance category. Figure 7B In this process, adjacent unit 192 is moved into the blocking region 510. The movement of adjacent unit 192 eliminates the obstruction caused by I peak The unit caused the DIR / SIR problem.

[0046] Figures 8A to 8B This is a schematic diagram of the cell layout arrangement before and after the violation cell 101 is moved away and the adjacent cell 192 is moved into the blocking area when the root cause of the violation cell belongs to the disturbance category, according to some embodiments. Figure 8A The layout shown is similar to Figure 6A or Figure 7A The layout shown is the same. Figure 6A , Figure 7A and Figure 8A Each element in the layout includes a non-compliant unit 101 and an adjacent unit 192. Figure 8BIn the diagram, only adjacent units 192 within the blocking area 510 are depicted, because the violating unit 101 has been moved to the safe zone (not shown in the diagram). Figure 8B (As shown in the diagram). After the offending unit 101 is placed in the safe zone, the adjacent unit 192 no longer induces DIR / SIR problems in the offending unit 101. After the adjacent unit 192 is placed within the blocking region 510, it also prevents the occurrence of problems caused by I... peak The potential DIR / SIR problem in other cells induced by the neighboring cell 192 of the cell.

[0047] Figure 9 This is a flowchart of a method 900 for designing a layout diagram of an integrated circuit according to some embodiments. Figure 9 The order of operations of method 900 described herein is for illustrative purposes only; the operations of method 900 can be performed in a different manner than described herein. Figure 9 The described sequence of execution. It should be understood that it is possible to... Figure 9 Other operations are performed before, during, and / or after the method 900 described herein, and only briefly described in this document.

[0048] In operation 910 of method 900, non-compliant units are identified in the layout diagram because they fail to meet one or more design rules related to IR voltage drop. In operation 920 of method 900, each of the one or more root causes leading to the non-compliant unit is categorized using the corresponding root cause category. Figure 1 In example embodiments, the root causes leading to the violation are tested sequentially in the order of resistivity category, clustering category, self-induced category, and interference category. In some alternative embodiments, the order in which the root cause categories are tested differs. Figure 1 The order of operations. For example, in some embodiments, after tests are performed to determine whether the root cause of a violating unit is a disturbed category, tests are performed to determine whether the root cause of a violating unit is a cluster category.

[0049] In some other embodiments, in operation 910, besides Figure 1 In addition to the four root cause categories (i.e., resistivity category, clustering category, self-induced category, and disturbed category), the root cause leading to the violation cell is tested against one or more other root cause categories. For example, in some embodiments, besides Figure 1In addition to the four root cause categories, there is also a root cause for fan-out class testing that leads to non-compliant cells. One possible root cause of the DIR / SIR problem corresponding to the fan-out class is due to current in the wires connecting the output of the driver to the inputs of a number of receivers (e.g., sixteen receivers). In some embodiments, the EDA program eliminates the DIR / SIR problem by adding buffer drivers between the output of the driver and the inputs of the number of receivers. In the example above involving sixteen receivers, after the layout is modified by the EDA program, in one implementation, the output of the driver is connected to the inputs of four buffer drivers, and the output of each of the four buffer drivers is connected to the inputs of four receivers. In some embodiments, to eliminate the DIR / SIR problem of the fan-out class, M buffers are placed between the drivers and N receivers, where M and N are integers. In method 900, after operation 920, the processing flow proceeds to operation 930.

[0050] In operation 930 of method 900, a search area is determined to search for safe zone candidates. Figure 2 In the example embodiment shown, the search area 200 around the violating unit 101 is determined by the EDA program. Figure 3 In the example embodiment shown, the EDA program determines a search region 200 divided into sixteen analysis areas. After operation 930, the processing flow proceeds to operation 940.

[0051] In operation 940 of method 900, the EDA procedure determines whether a safe area can be found within the search area to eliminate the selected root cause. If no safe area is found within the search area, the process proceeds to operation 960. If a safe area is found within the search area, the process proceeds to operation 952.

[0052] In operation 952 of method 900, the EDA program determines the selected cell to be moved to the safe area based on the category of the selected root cause. In operation 954 of method 900, the selected cell is moved to the safe area. Figures 4A to 4B In the example embodiment shown, when the root cause of the violation belongs to the cluster category, the selected cell to be moved to the safe zone is adjacent cell 194. In such a case... Figures 6A to 6B In the example embodiment shown, when the root cause of the violation is a disturbance category, the selected cell to be moved to the safe zone is adjacent cell 192. In such a case... Figures 8A to 8B In the example embodiment shown, when the root cause of the violation unit belongs to the disturbance category, the selected unit to be moved to the safe zone is the violation unit 101. After operation 952, the processing flow proceeds to operation 960.

[0053] After operation 952, when the selected cell is moved to the safe area, the process flow proceeds to operation 960, or after operation 930, when no safe area is found within the search area, the process flow proceeds to operation 960. In operation 960 of method 900, an adjacent cell is selected to move into the blocking area. Figures 5A to 5B In the example embodiment shown, when the root cause of the violation unit belongs to the cluster category, the selected neighboring unit for moving into the blocking region is neighboring unit 194. In such a case... Figures 7A to 7B and Figures 8A to 8B In the example embodiment shown, when the root cause of the violation unit is a disturbance category, the selected neighboring unit for moving into the blocking area is neighboring unit 192.

[0054] Figure 10 This is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0055] In some embodiments, the EDA system 1000 includes an APR system. According to one or more embodiments, the method described herein for representing a layout diagram of wire routing arrangements can be implemented, for example, using the EDA system 1000 according to some embodiments.

[0056] In some embodiments, the EDA system 1000 is a general-purpose computing device including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. The storage medium 1004 also encodes (i.e. stores) computer program code 1006, i.e., a set of executable instructions. The instructions 1006, executed by the hardware processor 1002, (at least partially) represent an EDA tool that implements part or all of the methods (hereinafter referred to as the processes and / or methods) described herein according to one or more embodiments.

[0057] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014 so that processor 1002 and computer-readable storage medium 1004 can be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004 to make system 1000 available to perform part or all of the process and / or method. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0058] In one or more embodiments, the computer-readable storage medium 1004 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes optical disc read-only memory (CD-ROM), CD-R / W, and / or digital video optical disc (DMD).

[0059] In one or more embodiments, storage medium 1004 stores computer program code 1006 configured to enable system 1000 (where such execution (at least partially) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1004 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 1004 stores a library 1007 of standard units (including such standard units disclosed herein). In one or more embodiments, storage medium 1004 stores one or more layout diagrams 1009 corresponding to one or more layouts disclosed herein.

[0060] EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0061] EDA system 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014, to which one or more other computer systems are connected. Network interface 1012 includes: a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 1000.

[0062] System 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transferred to processor 1002 via bus 1008. EDA system 1000 is configured to receive UI-related information via I / O interface 1010. This information is stored as a user interface (UI) 1042 on computer-readable medium 1004.

[0063] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1000. In some embodiments, software applications such as those available from Cadence Design Systems, Inc. are used. Tools such as those used to generate layout diagrams, or other suitable layout generation tools, can be used to generate layout diagrams that include standard cells.

[0064] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage devices or memory units, such as optical discs (e.g., DMDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs), memory cards, etc.

[0065] Figure 11 This is a block diagram of an integrated circuit (IC) manufacturing system 1100 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 1100 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0066] exist Figure 11In this IC manufacturing system 1100, entities interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1160, such as design room 1120, mask room 1130, and IC manufacturer / fab (“fab”) 1150. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1120, mask room 1130, and IC manufacturer / fab 1150 are owned by a single larger company. In some embodiments, two or more of design room 1120, mask room 1130, and IC manufacturer / fab 1150 coexist in a common facility and use common resources.

[0067] Design studio (or design team) 1120 generates IC design layout 1122. IC design layout 1122 includes various geometric patterns designed for IC device 1160. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 1160 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1122 includes various IC features (e.g., active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads) formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers disposed on the semiconductor substrate. Design studio 1120 implements appropriate design processes to form IC design layout 1122. These design processes include logic design, physical design, or placement and routing, or one or more of these. IC design layout 1122 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1122 may be expressed in GDSII or DFII file format.

[0068] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 uses an IC design layout 1122 to fabricate one or more masks 1145, which are used to fabricate the various layers of an IC device 1160 according to the IC design layout 1122. Mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (“RDF”). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (modulation disk) 1145 or a semiconductor wafer 1153. Mask data preparation 1132 processes the design layout 1122 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / manufacturer 1150. Figure 11 In this embodiment, mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0069] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0070] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1122, which has already been processed in the OPC, to ensure sufficient margin to accommodate variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0071] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC), which simulates the process to be implemented by the IC manufacturer / manufacturer 1150 to manufacture IC device 1160. The LPC simulates the process based on IC design layout 1122 to create a simulated fabricated device, such as IC device 1160. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after the simulated fabricated device is created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0072] It should be understood that, for clarity, the above description of mask data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0073] Following mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 is fabricated based on a modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, a pattern is formed on the mask (photomask or modulation disk) 1145 using a mechanism of electron beams or multiple electron beams based on the modified IC design layout 1122. The mask 1145 is formed using various techniques. In some embodiments, the mask 1145 may be formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1145 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1145, the individual features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1144 are used in various processes. For example, such masks(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1153, and / or in other suitable processes.

[0074] IC manufacturer / manufacturer 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer / manufacturer 1150 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end production line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end production line (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility may provide additional services to the foundry enterprise.

[0075] IC manufacturer / manufacturer 1150 includes manufacturing tools 1152 configured to perform various manufacturing operations on semiconductor wafer 1153 to manufacture IC device 1160 according to one or more masks (e.g., mask 1145). In various embodiments, manufacturing tools 1152 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CMD chamber or LPCMD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0076] IC manufacturer / manufacturer 1150 uses one or more masks 1145 manufactured by mask chamber 1130 to manufacture IC device 1160. Therefore, IC manufacturer / manufacturer 1150 uses IC design layout 1122 at least indirectly to manufacture IC device 1160. In some embodiments, semiconductor wafer 1153 is manufactured by IC manufacturer / manufacturer 1150 using one or more masks 1145 to form IC device 1160. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0077] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 11 Detailed information about the system 1100 and its associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0078] One aspect of this specification relates to a method for designing a layout of an integrated circuit. The method includes: identifying cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; and classifying the root causes leading to the non-compliant cells using root cause categories. The method further includes: determining a search region to search for safe region candidates; and identifying selected cells for movement based on the root cause categories of the root causes. The method also includes: identifying a safe region within the search region to move the selected cell; and if the safe region is found within the search region, moving the selected cell to the safe region.

[0079] Another aspect of this specification relates to a system for designing a layout of an integrated circuit. The layout is stored on a non-transitory computer-readable medium. The system includes at least one processor and at least one memory, the at least one memory including computer program code for one or more programs. The at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform the following operations: identify cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; and classify the root causes leading to the non-compliant cells using root cause categories. The system is also caused to perform the following operations: determine a search area to search for safe zone candidates; and identify selected cells for movement based on the root cause categories of the root causes. The system is also caused to perform the following operations: identify a safe zone in the search area to move the selected cell; and if the safe zone is found in the search area, move the selected cell to the safe zone.

[0080] Another aspect of this specification relates to a method for designing a layout of an integrated circuit. The method includes: identifying cells in the layout as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; and classifying each of the one or more root causes leading to the non-compliant cell using a corresponding root cause category. The method further includes: determining a search region to search for safe region candidates; and identifying a safe region within the search region to eliminate the selected root cause. The method also includes: identifying a selected cell for movement based on the corresponding root cause category of the selected root cause; and moving the selected cell to the safe region if it is found within the search region.

[0081] It will be readily apparent to those skilled in the art that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to implement various modifications, equivalents, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0082] Example 1. A method for designing a layout of an integrated circuit, the method comprising:

[0083] The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop;

[0084] The root causes leading to the violation are classified using root cause categories;

[0085] Define the search area to search for safe zone candidates;

[0086] Based on the root cause category of the root cause, identify the selected unit for movement;

[0087] Locate the safe zone within the search area to move the selected unit; and

[0088] If the safe zone is found within the search area, the selected unit is moved to the safe zone.

[0089] Example 2. According to the method of Example 1, locating the safe zone in the search area includes:

[0090] The search area is divided into multiple analysis zones;

[0091] The safe region is searched within a first analysis region, which has the lowest cell density among the plurality of analysis regions; and

[0092] If no safe region is found in the first analysis region, the safe region is searched in the second analysis region, which has the second lowest cell density among the plurality of analysis regions.

[0093] Example 3. The method according to Example 1, wherein the root cause category is a resistivity category, the method further includes:

[0094] Based on the resistance quality factor, the safe zone is located within the search area; and

[0095] If the safe zone is found within the search area, the violating unit is selected as the selected unit and moved to the safe zone.

[0096] Example 4. The method according to Example 1, wherein the root cause category is a cluster category, the method further includes:

[0097] If the safe zone is found within the search area, the neighboring cell with the highest peak current among all neighboring cells is selected as the selected cell to move to the safe zone, wherein the violating cell is adjacent to all of the neighboring cells.

[0098] Example 5. The method according to Example 1, wherein the root cause category is a cluster category, the method further includes:

[0099] If the safe zone is found within the search area, the neighboring data cell with the highest peak current among all neighboring data cells is selected as the selected cell to move to the safe zone, wherein the violating cell is adjacent to the neighboring data cell and at least one neighboring clock cell.

[0100] Example 6. The method according to Example 1, wherein the root cause category is a cluster category, the method further includes:

[0101] If no safe zone is found within the search area, the neighboring cell with the highest peak current among all neighboring cells is moved to the blocking zone, wherein the violating cell is adjacent to all of the neighboring cells.

[0102] Example 7. The method according to Example 1, wherein the root cause category is a disturbed category, the method further includes:

[0103] If the safe zone is found within the search area, then the adjacent data unit affecting the violating unit is selected as the selected unit and moved to the safe zone; and

[0104] If the safe zone is not found within the search area, the adjacent data unit is moved to the blocking area.

[0105] Example 8. The method according to Example 1, wherein the root cause category is a disturbed category, the method further includes:

[0106] Move the adjacent clock cell that affects the violating cell to the blocking region.

[0107] Example 9. The method according to Example 1, wherein the root cause category is a disturbed category, the method further includes:

[0108] If the safe zone is found within the search area, the violating unit is selected as the selected unit and moved to the safe zone; and

[0109] Before moving the violating unit, a blocking region is added around the adjacent data units that affect the violating unit.

[0110] Example 10. According to the method of Example 1, wherein classifying the root causes leading to the violation unit includes:

[0111] The root cause category sequence is used to examine the root cause that led to the violation.

[0112] Example 11. The method according to Example 10, wherein the root cause category sequence includes resistivity category, cluster category, self-induced category and disturbed category.

[0113] Example 12. The method according to Example 10, wherein the root cause category sequence follows an order including: resistivity category as a first root cause category, cluster category as a second root cause category, self-induced category as a third root cause category, and disturbed category as a fourth root cause category.

[0114] Example 13. The method according to Example 1, wherein the search region is configured to have safe zone candidates in at least two voltage domains.

[0115] Example 14. A system for designing a layout of an integrated circuit, the layout being stored on a non-transitory computer-readable medium, the system comprising at least one processor and at least one memory, the at least one memory including computer program code of one or more programs, wherein the at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform the following operations:

[0116] The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop;

[0117] The root causes leading to the violation are classified using root cause categories;

[0118] Define the search area to search for safe zone candidates;

[0119] Based on the root cause category of the root cause, identify the selected unit for movement;

[0120] Locate the safe zone within the search area to move the selected unit; and

[0121] If the safe zone is found within the search area, the selected unit is moved to the safe zone.

[0122] Example 15. The system according to Example 14, wherein the computer program code configured to cause the system to classify the root cause leading to the violation unit further includes:

[0123] Computer program code configured to enable the system to examine the root cause leading to the violation unit using a root cause category sequence.

[0124] Example 16. The system according to Example 15, wherein the root cause category sequence includes resistivity category, cluster category, self-induced category and disturbed category.

[0125] Example 17. The system according to Example 14, wherein the computer program code configured to cause the system to find the secure area is further configured to cause the system to perform the following operations:

[0126] The search area is divided into multiple analysis zones;

[0127] The safe region is searched within a first analysis region, which has the lowest cell density among the plurality of analysis regions; and

[0128] If no safe region is found in the first analysis region, the safe region is searched in the second analysis region, which has the second lowest cell density among the plurality of analysis regions.

[0129] Example 18. A method for designing a layout of an integrated circuit, the method comprising:

[0130] The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop;

[0131] Each of one or more root causes leading to the violation is classified using the corresponding root cause category;

[0132] Define the search area to search for safe zone candidates;

[0133] Locate the safe zone within the search area to eliminate the selected root cause;

[0134] Based on the corresponding root cause category of the selected root cause, identify the selected unit for movement; and

[0135] If the safe zone is found within the search area, the selected unit is moved to the safe zone.

[0136] Example 19. The method according to Example 18, wherein classifying the one or more root causes leading to the violation unit includes:

[0137] Use a root cause category sequence to examine one or more root causes that led to the violation unit.

[0138] Example 20. The method according to Example 19, wherein the root cause category sequence includes resistivity category, cluster category, self-induced category and disturbed category.

Claims

1. A method for designing a layout of an integrated circuit, the method comprising: The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; The root causes leading to the violation are classified using root cause categories; Determine the search area to search for safe zone candidates, where a safe zone is a location in the layout diagram where placing a unit will not result in a design violation due to IR voltage drop; Based on the root cause category of the root cause, select units are identified for movement, wherein the selected units are the violating units or adjacent to the violating units; Locate the safe zone within the search area to move the selected unit; and If the safe zone is found within the search area, the selected unit is moved to the safe zone.

2. The method according to claim 1, wherein, Locating the safe zone within the search area includes: The search area is divided into multiple analysis zones; The safe region is searched within a first analysis region, which has the lowest cell density among the plurality of analysis regions; and If no safe region is found in the first analysis region, the safe region is searched in the second analysis region, which has the second lowest cell density among the plurality of analysis regions.

3. The method according to claim 1, wherein, The root cause category is resistivity, and the method further includes: Based on the resistance quality factor, the safe zone is located within the search area; and If the safe zone is found within the search area, the violating unit is selected as the selected unit and moved to the safe zone.

4. The method according to claim 1, wherein, The root cause category is a cluster category, and the method further includes: If the safe zone is found within the search area, the neighboring cell with the highest peak current among all neighboring cells is selected as the selected cell to move to the safe zone, wherein the violating cell is adjacent to all of the neighboring cells.

5. The method according to claim 1, wherein, The root cause category is a cluster category, and the method further includes: If the safe zone is found within the search area, the neighboring data cell with the highest peak current among all neighboring data cells is selected as the selected cell to move to the safe zone, wherein the violating cell is adjacent to the neighboring data cell and at least one neighboring clock cell.

6. The method according to claim 1, wherein, The root cause category is a cluster category, and the method further includes: If no safe zone is found within the search area, the neighboring cell with the highest peak current among all neighboring cells is moved into the blocking zone, wherein the violating cell is adjacent to all of the neighboring cells.

7. The method according to claim 1, wherein, The root cause category is the disturbed category, and the method further includes: If the safe zone is found within the search area, then the adjacent data unit affecting the violating unit is selected as the selected unit and moved to the safe zone; and If the safe zone is not found within the search area, the adjacent data unit is moved to the blocking area.

8. The method according to claim 1, wherein, The root cause category is the disturbed category, and the method further includes: Move the adjacent clock cell that affects the violating cell to the blocking region.

9. The method according to claim 1, wherein, The root cause category is the disturbed category, and the method further includes: If the safe zone is found within the search area, the violating unit is selected as the chosen unit and moved to the safe zone; and Before moving the violating unit, a blocking region is added around the adjacent data units that affect the violating unit.

10. The method according to claim 1, wherein, The classification of the root causes leading to the violation includes: The root cause category sequence is used to examine the root cause that led to the violation.

11. The method according to claim 10, wherein, The root cause category sequence includes resistivity category, cluster category, self-induced category, and disturbed category.

12. The method according to claim 10, wherein, The root cause category sequence follows an order including the following: resistivity category as the first root cause category, cluster category as the second root cause category, self-induced category as the third root cause category, and disturbed category as the fourth root cause category.

13. The method according to claim 1, wherein, The search region is configured to have safe zone candidates in at least two voltage domains.

14. A system for designing a layout of an integrated circuit, the layout being stored on a non-transitory computer-readable medium, the system comprising at least one processor and at least one memory, the at least one memory including computer program code of one or more programs, wherein, The at least one memory, the computer program code, and the at least one processor are configured to cause the system to perform the following operations: The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; The root causes leading to the violation are classified using root cause categories; Determine the search area to search for safe zone candidates, where a safe zone is a location in the layout diagram where placing a unit will not result in a design violation due to IR voltage drop; Based on the root cause category of the root cause, select units are identified for movement, wherein the selected units are the violating units or adjacent to the violating units; Locate the safe zone within the search area to move the selected unit; and If the safe zone is found within the search area, the selected unit is moved to the safe zone.

15. The system according to claim 14, wherein, The computer program code configured to cause the system to classify the root causes leading to the violation unit further includes: Computer program code configured to enable the system to examine the root cause leading to the violation unit using a root cause category sequence.

16. The system according to claim 15, wherein, The root cause category sequence includes resistivity category, cluster category, self-induced category, and disturbed category.

17. The system of claim 14, wherein, The computer program code configured to cause the system to locate the secure area is also configured to cause the system to perform the following operations: The search area is divided into multiple analysis zones; The safe region is searched in a first analysis region, which has the lowest cell density among the plurality of analysis regions; as well as If no safe region is found in the first analysis region, the safe region is searched in the second analysis region, which has the second lowest cell density among the plurality of analysis regions.

18. A method for designing a layout of an integrated circuit, the method comprising: The cells in the layout diagram are identified as non-compliant cells that fail to meet one or more design rules related to IR voltage drop; Each of one or more root causes leading to the violation is classified using the corresponding root cause category; Determine the search area to search for safe zone candidates, where a safe zone is a location in the layout diagram where placing a unit will not result in a design violation due to IR voltage drop; Locate the safe zone within the search area to eliminate the selected root cause; Based on the corresponding root cause category of the selected root cause, a selected unit is identified for movement, wherein the selected unit is the violating unit or adjacent to the violating unit; and If the safe zone is found within the search area, the selected unit is moved to the safe zone.

19. The method according to claim 18, wherein, Classifying the one or more root causes leading to the violation includes: Use a root cause category sequence to examine one or more root causes that led to the violation unit.

20. The method according to claim 19, wherein, The root cause category sequence includes resistivity category, cluster category, self-induced category, and disturbed category.

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