Word line driver circuits for random access memory and random access memory

Abstract

This application discloses a word line driving circuit and a random access memory (RAM) for use with random access memory (RAM). The word line driving circuit includes: a first voltage generation module for generating a first voltage, wherein the first voltage is a predetermined driving voltage for the word line; a second voltage generation module for generating a second voltage, wherein the second voltage is greater than the first voltage; and a first selector connected to the first and second voltage generation modules and receiving a control signal to output the second voltage to drive the word line during a first time period based on the control signal, thereby causing the voltage on the word line to reach a stable conduction voltage; and outputting the first voltage to drive the word line during a second time period after the first time period to maintain the conduction of the word line. Through this method, word line establishment can be accelerated, the data read time of the RAM can be reduced, and the operating speed of the RAM can be improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to word line driving circuits and random access memory (RAM). Background Technology

[0002] A memory array consists of multiple word lines (WL), multiple bit lines (BL), and multiple memory cells. Each memory cell is connected to one word line (WL) and one bit line (BL). Typically, a memory cell includes an access switch and a storage capacitor. The word line (WL) controls the access switch to enable or disable reading and writing of the information stored in the capacitor. The bit line (BL) is the only channel for external access to the capacitor; when the access switch is enabled, external access can read from or write to the capacitor via the bit line (BL).

[0003] When reading and writing data in a memory cell, the word line WL needs to be driven to enable the access switch in the memory cell in order to complete the data reading and writing. Therefore, the setup time of the word line WL determines the data reading speed of the entire memory. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a word line driving circuit and a random access memory (RAM) that can accelerate word line creation, reduce the time for data retrieval in the RAM, and improve the operating speed of the RAM.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a word line driving circuit suitable for random access memory, comprising: a first voltage generation module for generating a first voltage, wherein the first voltage is a predetermined driving voltage of the word line; a second voltage generation module for generating a second voltage, wherein the second voltage is greater than the first voltage; a first selector connected to the first voltage generation module and the second voltage generation module, and receiving a control signal to output the second voltage to drive the word line in a first time period based on the control signal, thereby causing the voltage on the word line to reach a stable conduction voltage; and outputting the first voltage to drive the word line in a second time period after the first time period to maintain the conduction of the word line.

[0006] It further includes: a decoding module, connected to the first voltage generation module and the second voltage generation module, receiving a word line address signal, and outputting a working voltage to the first voltage generation module and the second voltage generation module based on the word line address signal, so that the first voltage generation module and the second voltage generation module generate a first voltage and a second voltage respectively based on the working voltage.

[0007] It further includes: a control signal generation module, connected to the first selector, to generate and output a control signal to the first selector, wherein the first time period is determined by the effective pulse width of the control signal.

[0008] The control signal generation module includes multiple delay providing units, each of which provides a preset delay period. The multiple delay providing units are connected in sequence, and a portion of the multiple delay providing units is selected to provide the corresponding preset delay period based on the test signal. The effective pulse width of the control signal is determined by the combination of the preset delay periods provided by the selected delay providing units.

[0009] The control signal generation module includes: a first delay providing unit, which determines whether to provide a first preset delay period based on a first test signal; and a second delay providing unit, which is connected to the first delay providing unit and determines whether to provide a second preset delay period on the output signal provided by the first delay providing unit based on a second test signal, wherein the output signal of the second delay providing unit serves as a control signal.

[0010] The first delay providing unit includes: a first delay circuit for providing a first preset delay period; a second selector, wherein a first input terminal of the second selector receives an initial control signal, a second input terminal of the second selector receives the initial control signal through the first delay circuit, and a control terminal of the second selector receives a first test signal; the second delay providing unit includes: a second delay circuit for providing a second preset delay period; and a third selector, wherein a first input terminal of the third selector is connected to the output terminal of the second selector through the second delay circuit, a second input terminal of the third selector is connected to the output terminal of the second selector, and a control terminal of the third selector receives a second test signal;

[0011] Specifically, in response to both the first and second test signals being 0, the first delay providing unit does not provide a first preset delay period, while the second delay providing unit provides a second preset delay period, and the first time period is the second preset delay period; in response to both the first and second test signals being 1, the first delay providing unit provides a first preset delay period, and the second delay providing unit provides a second preset delay period, and the first time period is the sum of the first and second preset delay periods; in response to both the first and second test signals being 1, the first delay providing unit provides a first preset delay period, while the second delay providing unit does not provide a second preset delay period, and the first time period is the first preset delay period.

[0012] The first time period is determined based on the time required for the voltage on the word line to reach the stable conduction voltage during the test using the second voltage drive. A portion of multiple delay supply units is selected based on the first time period, and the first time period is composed based on the preset delay period provided by the selected delay supply unit. The test signal used to select multiple delay supply units is burned into the electronic fuse of the random access memory so that after the test, the word line drive circuit can read the solidified test signal from the electronic fuse, thereby outputting the second voltage to the word line during the first time period.

[0013] The control signal generation module includes a comparison unit, wherein one input terminal of the comparison unit receives a stable on-state voltage, the other input terminal of the comparison unit is connected to a word line, and the output terminal of the comparison unit is connected to the control terminal of a first selector; wherein, when the voltage feedback from the word line is less than the stable on-state voltage, the control signal output by the comparison unit causes the first selector to select the output of a second voltage to drive the word line; when the voltage feedback from the word line is not less than the stable on-state voltage, the control signal output by the comparison unit causes the first selector to select the output of a first voltage to drive the word line.

[0014] The conduction stabilization voltage is 95% of the second voltage.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a random access memory, which includes the word line driving circuit provided by the above technical solution.

[0016] The beneficial effects of this application's embodiments are as follows: Unlike existing technologies, the word line driving circuit provided in this application includes: a first voltage generation module for generating a first voltage, wherein the first voltage is a predetermined driving voltage for the word line; a second voltage generation module for generating a second voltage, wherein the second voltage is greater than the first voltage; and a first selector connected to the first and second voltage generation modules, receiving a control signal to output the second voltage to drive the word line in a first time period based on the control signal, thereby causing the voltage on the word line to reach a stable conduction voltage; and outputting the first voltage to drive the word line in a second time period after the first time period to maintain the conduction of the word line. Through this method, because the second voltage is greater than the first voltage, the second voltage can be used to quickly bring the voltage on the word line to a stable conduction voltage, accelerating the establishment of the word line. Furthermore, outputting the first voltage to drive the word line in the second time period after the first time period to maintain the conduction of the word line reduces the data read time of the random access memory and improves the operating speed of the random access memory. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic diagram of the storage array structure of the random access memory provided in this application;

[0019] Figure 2 yes Figure 1 A schematic diagram of the structure of the first initialization module;

[0020] Figure 3 yes Figure 1 Schematic diagram of the medium-sensitivity amplification module;

[0021] Figure 4 yes Figure 3 A circuit diagram of an embodiment of a medium-sensitivity amplification module;

[0022] Figure 5 yes Figure 1 A schematic diagram of the middle column selection circuit;

[0023] Figure 6 yes Figure 1 A schematic diagram of the input / output circuit.

[0024] Figure 7 This is a schematic diagram of the potential trend of the random access memory provided in this application;

[0025] Figure 8 This is a schematic diagram of the structure of a first embodiment of a word line driving circuit for random access memory provided in this application;

[0026] Figure 9 This is a schematic diagram of the control signals and word line voltage trends of the word line drive circuit applicable to random access memory provided in this application;

[0027] Figure 10 This is a schematic diagram of the second embodiment of the word line driving circuit for random access memory provided in this application;

[0028] Figure 11 This is a schematic diagram of the third embodiment of the word line driving circuit for random access memory provided in this application;

[0029] Figure 12 This is a schematic diagram of the structure of an embodiment of the control signal generation module provided in this application;

[0030] Figure 13This is a schematic diagram of the fifth embodiment of the word line driving circuit for random access memory provided in this application;

[0031] Figure 14 This is a schematic diagram of the random access memory provided in this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the random access memory array provided in this application. The memory array 100 includes multiple word lines (WL), multiple bit lines (BL), and multiple memory cells 110, wherein each memory cell 110 is connected to a word line WL and a bit line BL.

[0035] In one embodiment where the random access memory is Dynamic Random Access Memory (DRAM), each memory cell 110 includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the amount of charge stored within it, or the voltage difference across its terminals. The on / off state of the access switch determines whether reading and rewriting of the information stored in the storage capacitor is permitted or prohibited.

[0036] Specifically, the word line WL determines whether the access switch is on or off, and the bit line BL is the only channel for external access to the storage capacitor. When the access switch is on, external access can read or write to the storage capacitor through the bit line BL.

[0037] In one embodiment, the common terminal of the storage capacitor is connected to Vcc / 2.

[0038] When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is Vcc, and the charge stored at this time is:

[0039] Q = +Vcc / 2*C.

[0040] When the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0. At this time, the stored charge is:

[0041] Q = -Vcc / 2*C.

[0042] Furthermore, the storage array 100 also includes a first initialization module 120, a sensitive amplification module 130, a column selection circuit 140, and an input / output circuit 150.

[0043] It is worth noting that two adjacent bit lines BL can be used as references to each other, and can be regarded as multiple pairs of complementary bit lines (target bit line BL and complementary bit line BL#). Specifically, the first initialization module 120 is connected to a pair of complementary bit lines (BL / BL#) to charge the target bit line BL and complementary bit line BL# to the initialization potential during the precharge phase. The sensitive amplification module 130 is connected to a pair of complementary bit lines (BL / BL#) to amplify the logic potential on the target bit line BL to a corresponding strong potential when the memory cell 110 connected to the target bit line BL is turned on by the word line (WL). The input / output circuit 150 includes a pair of complementary input / output lines (IO / IO#), and the column selection circuit 140 includes multiple column gating modules 141 and a column gating signal generation circuit 142. Each column gating module 141 is connected to a pair of complementary bit lines to determine whether the current complementary bit line pair is selected with the connected complementary input / output line pair (IO / IO#) based on the corresponding column selection signal generated by the column gating signal generation circuit 142.

[0044] See Figure 2 , Figure 2 yes Figure 1 The schematic diagram of the first initialization module is shown. The first initialization module 120 includes switches T1, T2 and T3. The control terminals of switches T1, T2 and T3 receive the first pre-charge control signal EQ1. The first path terminal of switch T1 is connected to the target bit line BL. The first path terminal of switch T2 is connected to the complementary bit line BL#. The second path terminals of switches T1 and T2 are connected to the initialization potential Vref. The first path terminal of switch T3 is connected to the target bit line BL. The second path terminal of switch T3 is connected to the complementary bit line BL#.

[0045] During the pre-charging phase, the first pre-charging control signal EQ1 controls switches T1 and T2 to turn on, charging the target bit line BL and the complementary bit line BL# with the initialization potential Vref, so that the potentials of the target bit line BL and the complementary bit line BL# are at the initialization potential. Further, the first pre-charging control signal EQ1 controls switch T3 to turn on, ensuring that the potentials of the target bit line BL and the complementary bit line BL# remain consistent.

[0046] Optionally, the switches T1, T2 and T3 mentioned above can be nMOS transistors.

[0047] See Figure 3 , Figure 3 yes Figure 1 A schematic diagram of the structure of the sensitive amplification module 130, which includes a first inverting unit 131 and a second inverting unit 132.

[0048] The first inverting unit 131 is connected between the target bit line BL and the complementary bit line BL#. When the memory cell 110 connected to the target bit line BL is turned on, the target bit line voltage VBL on the target bit line BL is offset from the initial potential Vref according to the logic level stored in the memory cell 110. The first inverting unit 131 flips based on the upward or downward offset target bit line voltage VBL, and pulls the complementary bit line voltage VBL# on the complementary bit line BL# to the strong potential of the first logic.

[0049] The second inverting unit 132 is connected between the complementary bit line BL# and the target bit line BL. When the complementary bit line voltage VBL# on the complementary bit line BL# is pulled to the strong potential of the first logic, the second inverting unit 132 flips based on the complementary bit line voltage VBL# and pulls the target bit line voltage VBL on the target bit line BL to the strong potential of the second logic. The second logic is opposite to the first logic.

[0050] See also Figure 3 and Figure 4 , Figure 4 yes Figure 3 A circuit diagram of an embodiment of the medium-sensitivity amplification module, wherein the first inverting unit 131 includes switches T4 and T5, and the second inverting unit 132 includes switches T6 and T7.

[0051] Optionally, in this embodiment, switches T4 and T6 are nMOS transistors, and switches T5 and T7 are pMOS transistors.

[0052] See Figure 5 , Figure 5 yes Figure 1The schematic diagram of the column selection circuit shows that the column selection circuit 140 includes a column selection signal generation circuit 142 and multiple column selection modules 141. Each column selection module 141 is connected to a pair of complementary bit line pairs (BL / BL#) to determine whether the current complementary bit line pair (BL / BL#) is selected with the connected complementary input / output line pair (IO / IO#) based on the corresponding column selection signal YS generated by the column selection signal generation circuit 142.

[0053] The column gating module 141 includes switches T8 and T9. The control terminals of switches T8 and T9 are connected to the column gating signal generation circuit 142 to receive the corresponding column gating signal YS. The first path terminal of switch T8 is connected to the target bit line BL, and the second path terminal is connected to the target input / output line IO. The first path terminal of switch T9 is connected to the complementary bit line BL#, and the second path terminal is connected to the complementary input / output line IO#.

[0054] Specifically, when the column selection signal YS generated by the column selection signal generation circuit 142 controls the switches T8 and T9 to turn on, the target bit line BL is connected to the target input / output line IO, and the complementary bit line BL# is connected to the complementary input / output line IO#, so as to realize the selection of the complementary bit line pair (BL / BL#) and the complementary input / output line pair (IO / IO#): during the write operation, the complementary bit line pair (BL / BL#) is charged / discharged through the complementary input / output line pair (IO / IO#) to rewrite the voltage on the complementary bit line pair (BL / BL#) by changing the signal on the complementary input / output line pair (IO / IO#); during the read operation, the signal on the complementary bit line pair (BL / BL#) is output to the complementary input / output line pair (IO / IO#).

[0055] Optionally, the switches T8 and T9 mentioned above can be nMOS transistors.

[0056] See Figure 6 , Figure 6 yes Figure 1 The schematic diagram of the input / output circuit is shown. The input / output circuit 150 includes a second initialization module 151.

[0057] The second initialization module 151 includes switches T10, T11, and T12. The control terminals of switches T10, T11, and T12 receive a second pre-charge control signal EQ2. The first path terminal of switch T10 is connected to the target input / output point IO, the first path terminal of switch T11 is connected to the complementary input / output point IO#, the second path terminals of switches T10 and T11 are connected to the reference potential Vcc, the first path terminal of switch T12 is connected to the target input / output point IO, and the second path terminal of switch T12 is connected to the complementary input / output point IO#.

[0058] During the initialization phase of the input / output circuit 150, the second pre-charge control signal EQ2 controls switches T10 and T11 to turn on, charging the target input / output point IO and the complementary input / output point IO# with the reference voltage Vcc, so that the potentials of the target input / output point IO and the complementary input / output point IO# are equal to the reference potential Vcc. Further, the second pre-charge control signal EQ2 controls switch T12 to turn on, ensuring that the potentials of the target input / output point IO and the complementary input / output point IO# remain consistent. After the sensitive amplification module 130 amplifies the logic level stored in the memory cell 110 read from the complementary bit line pair (BL / BL#) and pulls it to a strong "0" or strong "1", the input / output circuit 150 can connect to the complementary bit line pair (BL / BL#) through the complementary input / output line pair (IO / IO#) to complete read / write operations.

[0059] Optionally, the switches T10, T11 and T12 mentioned above can be nMOS transistors.

[0060] In combination with the above Figures 1-6 And see Figure 7 , Figure 7 This is a schematic diagram of the potential trend of a random access memory embodiment provided in this application. The following describes the working process of the dynamic random access memory in this embodiment using the read operation process, which includes the precharge stage, access stage, sense stage and restore stage.

[0061] precharge phase:

[0062] In this stage, the control signal EQ1 first turns on switches T1, T2, and T3, stabilizing the voltage on the target bit line BL and the complementary bit line BL# at Vref, assuming Vref = Vcc / 2. Then, the process proceeds to the next stage.

[0063] Access phase:

[0064] After the precharge phase, the voltages on the target bit line BL and the complementary bit line BL# have stabilized at Vref. At this point, the access switch in memory cell 110 is turned on by controlling the word line WL (by applying voltage to the word line WL via the Active instruction). The positive charge stored in the storage capacitor in memory cell 110 (for example, if memory cell 110 stores "1", the voltage at one common terminal of the capacitor is Vcc / 2, and the voltage at the other terminal is Vcc) flows to the target bit line BL, causing the voltage of the target bit line BL to shift upwards to Vref+. If memory cell 110 stores "0", the voltage of the target bit line BL shifts downwards to Vref-. Then, the process proceeds to the next phase.

[0065] Sense stage:

[0066] Assuming storage cell 110 stores a "1": During the access phase, the voltage of the target bit line BL shifts upward to Vref+, and at this time, SAN is set to a strong logic "0" potential, while SAP is set to a strong logic "1" potential. Because the "1" stored in storage cell 110 pulls the voltage of the target bit line BL up to Vref+, while the voltage of the complementary bit line BL# remains at Vref, therefore... Figure 4 Switch T4 is more conductive than switch T6, and the voltage on the complementary bit line BL# is pulled to a strong logic "0" potential by SAP more quickly due to the conduction of T4. Since the gate of T7 is at a strong "0" and is conducting, the voltage on the target bit line BL is also pulled to a strong logic "1" potential by SAP more quickly due to the conduction of T7. Then switches T4 and T7 enter the conducting state, while switches T5 and T6 enter the cut-off state. Finally, the voltages of the target bit line BL and the complementary bit line BL# both enter a stable state, and the voltage on the target bit line BL correctly represents the information Bit ("1") stored by the storage capacitor in the memory cell 110.

[0067] Assuming memory cell 110 stores "0": During the access phase, the voltage of the target bit line BL shifts downward by Vref-. Since the voltage of the complementary bit line BL# is still Vref at this time, therefore... Figure 4 Switch T5 is more conductive than switch T7, and the voltage on the complementary bit line BL# is pulled to a strong logic "1" potential by SAP more quickly due to the conduction of T5. Since the gate of T6 is at a strong "0" and is conducting, the voltage on the target bit line BL is also pulled to a strong logic "0" potential by SAN more quickly due to the conduction of T6. Then switches T5 and T6 enter the conducting state, while switches T4 and T7 enter the cut-off state. Finally, the voltages of the target bit line BL and the complementary bit line BL# both enter a stable state, and the voltage on the target bit line BL correctly represents the information Bit ("0") stored by the storage capacitor in the memory cell 110.

[0068] Restore phase:

[0069] After the sense phase operation is completed, the target bit line BL is at a stable logic "1" or logic "0" strong potential. At this time, the target bit line BL will charge or discharge the storage capacitor in the storage cell 110. After a certain period of time, the charge of the storage capacitor can be restored to the state before the read operation.

[0070] Finally, as Figure 5As shown, the column strobe signal generation circuit controls the YS signal, causing switches T8 and T9 to enter the conducting state. This outputs a strong "1" or strong "0" signal on the target bit line BL to the IO line, allowing the external system to read the specific information. It is worth noting that the aforementioned restore phase is performed automatically during the word line WL's activation. Therefore, for read operations, the restore operation may also occur after the YS signal is activated.

[0071] The above process describes a complete read operation. The initial flow of a write operation is the same as that of a read operation, executing the precharge, access, sense, and restore phases. The difference lies in that the restore phase includes a write phase, and a write recovery operation is performed afterward, as detailed below:

[0072] like Figure 5 As shown, the column selection signal YS is controlled by the column selection signal generation circuit 142, causing switches T8 and T9 to enter the conducting state. The signal of the input / output line IO will rewrite the target bit line BL. At this time, if "0" is written, the target bit line BL will be pulled to the logic "0" level, and the complementary bit line BL# will be pulled to the logic "1" level; if "1" is written, the target bit line BL will be pulled to the logic "1" level, and the complementary bit line BL# will be pulled to the logic "0" level.

[0073] Then, write recovery is performed: after a specific time (i.e., tWR), when the charge of the storage capacitor in the storage cell 110 is discharged to the "0" state or charged to the "1" state by the voltage on the target bit line BL, the switch in the storage cell 110 can be turned off by controlling the word line WL, and the operation of writing "0" or "1" is completed.

[0074] As transistor sizes shrink, market demands for chip speeds are increasing. Several key parameters affect read / write speeds in random access memory (RAM), one of which is tRCD (RAS to CASDelay). tRCD refers to the minimum time interval between receiving an ACTIVE command (which opens the write lock) and receiving read / write commands. The DDR4 JEDEC standard requires tRCD to be 12.5ns. tRCD includes... Figure 7The diagram shows two parts: the access phase and the sense phase. The access phase is the word line (WL) setup time, and the sense phase is the time it takes for the sensitive amplification module 130 to read the data from the storage unit 110 into the complementary bit line pair BL / BL# and amplify it. This invention proposes a word line drive circuit that uses high voltage drive to reduce the setup time of the access phase WL, thereby reducing the tRCD.

[0075] See Figure 8 , Figure 8 This is a schematic diagram of an embodiment of a word line driving circuit for random access memory provided in this application. The word line driving circuit 90 includes a first voltage generation module 91, a second voltage generation module 92, and a first selector 93.

[0076] The first voltage generation module 91 is used to generate a first voltage VPP, which is a predetermined drive voltage for the word line WL. For example, the DDR4 JEDEC standard specifies a predetermined drive voltage VPP = 2.5V + 0.25V / - 0.125V, while the operating voltage VDD of the random access memory is 1.20V + / - 0.06V.

[0077] The second voltage generation module 92 is used to generate a second voltage VPPH, wherein the second voltage VPPH is greater than the first voltage VPP.

[0078] The first selector 93 is connected to the first voltage generation module 91 and the second voltage generation module 92, and receives the control signal Com. Based on the control signal Com, it outputs the second voltage VPPH to drive the word line WL in the first time period, so that the voltage on the word line WL reaches the turn-on stable voltage. In the second time period after the first time period, it outputs the first voltage VPP to drive the word line WL to maintain the conduction of the word line WL.

[0079] The first time period and the second time period are determined by the control signal Com. For example, the first time period is determined by the effective pulse width of the control signal Com. If the effective level of the control signal Com is high, then the first time period is determined by the high-level pulse width of the control signal Com.

[0080] In one application scenario, combined Figure 8 and Figure 9Explanation: When the enable signal en is triggered by a falling edge, enabling is effective. At this time, when the control terminal C of the first selector 93 receives the control signal Com, the control signal Com is high during the first time period t1. Therefore, the first selector 93 selects to output the second voltage VPPH to drive the word line WL, thereby causing the voltage on the word line WL to quickly reach the stable conduction voltage. That is, the second input terminal S2 of the first selector 93 is connected to the output terminal D. In the second time period t2 after the first time period t1, the control signal Com is low. Therefore, the first selector 93 selects to output the first voltage VPP to drive the word line WL to maintain the conduction of the word line WL. That is, the first input terminal S1 of the first selector 93 is connected to the output terminal D. Then, in... Figure 9 In the middle, the voltage on the word line WL will drop from the second voltage VPPH back to the first voltage VPP.

[0081] Those skilled in the art will understand that, in other embodiments, during the first time period, if the control signal Com is low, the first selector 93 selects to output the second voltage VPPH to the word line WL, thereby causing the voltage on the word line WL to reach the turn-on stable voltage. During the second time period after the first time period, if the control signal Com is high, the first selector 93 selects to output the first voltage VPP to drive the word line WL, thereby maintaining the conduction of the word line WL.

[0082] In this embodiment, since the second voltage VPPH is greater than the first voltage VPP, the second voltage VPPH can be used to make the voltage on the word line WL quickly reach the turn-on stable voltage, accelerate the establishment of the word line WL, and output the first voltage VPP to the word line in the second time period after the first time period to maintain the conduction of the word line WL, thereby reducing the time for random access memory to read data and improving the operating speed of random access memory.

[0083] See Figure 10 , Figure 10 This is a schematic diagram of an embodiment of a word line driving circuit for random access memory provided in this application. The word line driving circuit 90 includes a first voltage generation module 91, a second voltage generation module 92, a first selector 93, and a decoding module 94.

[0084] The first input terminal S1 of the first selector 93 is connected to the first voltage generating module 91, and the second input terminal S2 of the first selector 93 is connected to the second voltage generating module 92. The control terminal C of the first selector 93 is used to receive the control signal Com.

[0085] The decoding module 94 is connected to the first voltage generation module 91 and the second voltage generation module 92, and receives the word line address signal RA. Based on the word line address signal RA, it outputs the working voltage VDD to the first voltage generation module 91 and the second voltage generation module 92, so that the first voltage generation module 91 and the second voltage generation module 92 generate the first voltage VPP and the second voltage VPPH respectively based on the working voltage VDD.

[0086] In some embodiments, the decoding module 94 can determine the target word line WL to be driven based on the word line address signal RA, and can ensure that the bit line WL is driven after the decoding module 94 finishes decoding, thus ensuring the correctness of the timing. Based on the determined target word line WL, the first selector 93 selects to output a second voltage VPPH to the target word line WL in a first time period, so that the voltage on the target word line WL quickly reaches the turn-on stable voltage, accelerating the establishment of the target word line WL; and outputs a first voltage VPP to the target word line WL in a second time period after the first time period to maintain the conduction of the target word line WL, thereby reducing the data reading time of the random access memory and improving the operating speed of the random access memory.

[0087] See Figure 11 , Figure 11 This is a schematic diagram of an embodiment of a word line driving circuit for random access memory provided in this application. The word line driving circuit 90 includes a first voltage generation module 91, a second voltage generation module 92, a first selector 93, and a control signal generation module 95.

[0088] In this configuration, the first input terminal S1 of the first selector 93 is connected to the first voltage generation module 91, and the second input terminal S2 of the first selector 93 is connected to the second voltage generation module 92. The control signal generation module 95 is connected to the control terminal C of the first selector 93 to generate and output a control signal Com to the first selector 93, wherein the first time period is determined by the width of the effective pulse (e.g., a high-level pulse) of the control signal Com.

[0089] In one application scenario, the control signal generation module 95 includes multiple delay providing units (not shown). Each delay providing unit provides a preset delay period. The multiple delay providing units are connected in sequence, and a portion of the multiple delay providing units is selected to provide the corresponding preset delay period based on the test signal. The effective pulse width of the control signal Com is determined by the combination of preset delay periods provided by the selected delay providing units.

[0090] Each delay unit receives a corresponding test signal and determines whether to provide a preset delay period based on the test signal. Therefore, a corresponding number of delay units from multiple delay providing units can be selected to generate the preset delay period, which is then combined into an effective pulse (e.g., a high-level pulse) for the control signal Com.

[0091] In some embodiments, the number of delay provisioning units may be 2, 3, or 4.

[0092] In some embodiments, see Figure 12 To illustrate, the control signal generation module 95 includes two delay providing units as an example: the control signal generation module 95 includes a first delay providing unit 951 and a second delay providing unit 952.

[0093] Among them, the first delay providing unit 951 is based on the first test signal Test <0> And decide whether to provide a first preset delay period (delay 1).

[0094] The second delay providing unit 952 is connected to the first delay providing unit 951 to provide delay based on the second test signal Test. <1> The decision is made on whether to further provide a second preset delay period (delay 2) on the output signal provided by the first delay providing unit 951, wherein the output signal of the second delay providing unit 952 serves as the control signal Com.

[0095] Specifically, the first delay providing unit 951 may include a first delay circuit 9511 and a second selector 9512. The first delay circuit 9511 is used to provide a first preset delay period (delay 1).

[0096] Specifically, the first input terminal S1 of the second selector 9512 receives the initial control signal Cin, the second input terminal S2 of the second selector 9512 receives the initial control signal Cin through the first delay circuit 9511, and the control terminal C of the second selector 9512 receives the first test signal Test. <0> .

[0097] The second delay providing unit 952 may include a second delay circuit 9521 and a third selector 9522. The second delay circuit 9521 is used to provide a second preset delay period (delay 2).

[0098] The first input terminal S1 of the third selector 9522 is connected to the output terminal D of the second selector 9512 via the second delay circuit 9521. The second input terminal S2 of the third selector 9522 is connected to the output terminal D of the second selector 9512. The control terminal C of the third selector 9522 receives the second test signal Test. <1> .

[0099] In one application scenario, in response to the first test signal Test <0> The value is 0, and the second test signal is Test. <1> When the value is 0, the first delay providing unit 951 does not provide the first preset delay period, and the second delay providing unit 952 provides the second preset delay period, with the first time period being the second preset delay period. When the first test signal Test... <0> The value is 0, and the second test signal is Test. <1> When the value is 0, it represents the default state of the electronic fuse.

[0100] That is, in the first test signal Test <0> When the value is 0, the first delay providing unit 951 selects the initial control signal Cin received at the first input terminal S1 of the second selector 9512 and outputs it from the output terminal D of the second selector 9512. In the second test signal Test... <1> When the value is 0, the second delay providing unit 952 selects to output the output signal of the second delay circuit 9521 received at the first input terminal S1 of the third selector 9522 from the output terminal D of the third selector 9522, i.e., output the control signal Com. Since the second delay circuit 9521 is used to provide a second preset delay period (delay 2), the control signal Com includes the second preset delay period (delay 2). That is, Figure 9 The first time period t1 is the second preset delay period (delay 2).

[0101] In another application scenario, in response to the first test signal Test <0> The second test signal is 1. <1> If the value is 0, the first delay providing unit 951 provides a first preset delay period, and the second delay providing unit 952 provides a second preset delay period. The first time period is the sum of the first preset delay period and the second preset delay period.

[0102] That is, in the first test signal Test <0> When the value is 1, the first delay providing unit 951 selects to output the output signal of the first delay circuit 9511 received at the second input terminal S2 of the second selector 9512 from the output terminal D of the second selector 9512. In the second test signal Test... <1> When the value is 0, the output terminal D of the third selector 9522 in the second delay providing unit 952 will be connected to the first input terminal S1 of the third selector 9522. That is, the input signal of the first input terminal S1 of the third selector 9522 will be output as the control signal Com from the output terminal D of the third selector 9522. Since the second delay providing unit 952 receives a signal containing a first preset delay period and, based on the signal it provides for a second preset delay period, combines the signal of the preset delay period and the signal of the second preset delay period, and outputs the combined signal from the output terminal D of the third selector 9522 in the second delay providing unit 952. Figure 9The first time period t1 is the sum of the first preset delay period and the second preset delay period (delay1 + delay2).

[0103] In another application scenario, in response to the first test signal Test <0> The second test signal is 1. <1> If the value is 1, the first delay providing unit 951 provides a first preset delay period, and the second delay providing unit 952 does not provide a second preset delay period. The first time period is the first preset delay period.

[0104] That is, in the first test signal Test <0> When the value is 1, the first delay providing unit 951 selects to output the output signal of the first delay circuit 9511 received at the second input terminal S2 of the second selector 9512 from the output terminal D of the second selector 9512. In the second test signal Test... <1> When the value is 1, the output terminal D of the third selector 9522 in the second delay providing unit 952 will be connected to the second input terminal S2 of the third selector 9522, that is, the input signal of the second input terminal S2 of the third selector 9522 will be output as the control signal Com. That is, the control signal Com only contains the first preset delay period. Figure 9 The first time period t1 is the first preset delay period (delay1).

[0105] In some embodiments, the first time period t1 is determined based on the time required for the voltage on word line WL to reach the turn-on stable voltage using the second voltage VPPH during testing. A portion of multiple delay-providing units are selected based on the first time period t1, and the first time period is composed of preset delay periods provided by the selected delay-providing units. During testing, the criterion for determining that "the voltage on word line WL has reached the turn-on stable voltage" can be that the voltage on WL is driven up to 95%*VPPH by the second voltage VPPH and then the second voltage VPPH driving is stopped. However, the present invention is not limited to this; other methods can be used to determine that "the voltage on word line WL has reached the turn-on stable voltage," for example, the voltage on WL is driven up to 95%*VPP by the second voltage VPPH and does not fall back to 90%*VPP when switched to the first voltage VPP driving.

[0106] Test signals corresponding to multiple (let's say n) delay supply units <0> ~Test <n>The electronic fuses are programmed into the random access memory (RAM) so that after testing, the word line drive circuit 90 reads the solidified test signal from the electronic fuses, thereby outputting a second voltage VPPH to drive the word line WL during the first time period. Each delay unit reads the corresponding test signal during word line driving to determine whether a preset delay period should be provided. Since multiple delay units are connected sequentially, the first time period t1 can be determined based on at least one specifically provided preset delay period.

[0107] Therefore, the first selector 93 can output a second voltage VPPH to drive the word line WL in the first time period, so that the voltage on the word line WL reaches the turn-on stable voltage; and output a first voltage VPP to drive the word line WL in the second time period after the first time period, so as to maintain the conduction of the word line WL.

[0108] See Figure 13 , Figure 13 This is a schematic diagram of an embodiment of a word line driving circuit for random access memory provided in this application. The word line driving circuit 90 includes a first voltage generation module 91, a second voltage generation module 92, a first selector 93, and a control signal generation module (not shown).

[0109] The control signal generation module 95 is connected to the first selector 93 to generate and output control signals to the first selector 93.

[0110] The control signal generation module includes a comparison unit 953.

[0111] The comparator 953 has one input terminal receiving the turn-on stable voltage VPPtarget, another input terminal connected to the word line WL, and an output terminal connected to the control terminal of the first selector 93. When the voltage fed back from the word line WL is less than the turn-on stable voltage VPPtarget, the control signal Com output by the comparator 953 causes the first selector 93 to select and output the second voltage VPPH to drive the word line WL.

[0112] When the voltage feedback of the word line is not less than the turn-on stable voltage VPPtarget, the control signal Com output by the comparator unit 953 causes the first selector 93 to select the first voltage VPP to drive the word line WL.

[0113] The conduction stabilization voltage VPPtarget is 95% of the first voltage VPP. This prevents the comparator unit 953 from oscillating repeatedly when switching back to the first voltage VPP to drive the word line WL. Of course, this invention does not specifically limit the value of VPPtarget, as long as it is a value very close to, but below, the first voltage VPP.

[0114] In this embodiment, a comparator unit 953 is used to monitor the voltage of word line WL, thereby controlling the output voltage of the first selector 93. When the voltage fed back from word line WL is less than the turn-on stable voltage VPPtarget, the first selector 93 selects to output the second voltage VPPH to drive word line WL, so that the voltage on word line WL quickly reaches the turn-on stable voltage, accelerating the establishment of word line WL. When the voltage fed back from word line is not less than the turn-on stable voltage VPPtarget, the first selector 93 selects to output the first voltage VPP to word line WL to maintain the conduction of word line WL, thereby reducing the data read time of random access memory and improving the operating speed of random access memory 900.

[0115] See Figure 14 , Figure 14 This is a schematic diagram of the structure of the random access memory 900 provided in this application, which includes a word line driving circuit 90 as described in any of the above embodiments.

[0116] Optionally, the random access memory 900 in this embodiment is DRAM (Dynamic Random Access Memory). DRAM is a semiconductor memory whose main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is "1" or "0".

[0117] Combining the beneficial effects of the above embodiments, since the second voltage VPPH is greater than the first voltage VPP, the voltage on the word line WL can be driven by the second voltage VPPH to quickly reach the turn-on stable voltage, thereby accelerating the establishment of the word line WL. In the second time period after the first time period, the first voltage VPP is output to drive the word line WL to maintain the conduction of the word line WL, thereby reducing the time for the random access memory to read data and improving the operating speed of the random access memory 900.

[0118] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.< / n>

Claims

1. A word line driving circuit suitable for random access memory, characterized in that, include: A first voltage generation module is used to generate a first voltage, wherein the first voltage is a predetermined driving voltage for a word line; A second voltage generating module is used to generate a second voltage, wherein the second voltage is greater than the first voltage; A first selector connects the first voltage generation module and the second voltage generation module, and receives a control signal to output the second voltage to drive the word line in a first time period based on the control signal, thereby causing the voltage on the word line to reach the turn-on stable voltage; and outputs the first voltage to drive the word line in a second time period after the first time period to maintain the conduction of the word line. A control signal generation module is connected to the first selector to generate and output the control signal to the first selector, wherein the first time period is determined by the effective pulse width of the control signal.

2. The word line driving circuit according to claim 1, characterized in that, Further includes: The decoding module is connected to the first voltage generation module and the second voltage generation module, and receives the word line address signal. Based on the word line address signal, it outputs a working voltage to the first voltage generation module and the second voltage generation module, so that the first voltage generation module and the second voltage generation module generate the first voltage and the second voltage respectively based on the working voltage.

3. The word line driving circuit according to claim 1, characterized in that, The control signal generation module includes: Multiple delay providing units, wherein each delay providing unit is used to provide a preset delay period, the multiple delay providing units are connected together in sequence, and a portion of the multiple delay providing units are selected to provide a corresponding preset delay period based on a test signal, and the effective pulse width of the control signal is determined by the combination of preset delay periods provided by the selected delay providing units.

4. The word line driving circuit according to claim 3, characterized in that, The control signal generation module includes: The first delay providing unit determines whether to provide a first preset delay period based on the first test signal; The second delay providing unit is connected to the first delay providing unit to determine whether to provide a second preset delay period on the output signal provided by the first delay providing unit based on the second test signal, wherein the output signal of the second delay providing unit serves as the control signal.

5. The word line driving circuit according to claim 4, characterized in that, The first delay providing unit includes: A first delay circuit is used to provide the first preset delay period; The second selector, wherein the first input terminal of the second selector receives an initial control signal, the second input terminal of the second selector receives the initial control signal through the first delay circuit, and the control terminal of the second selector receives the first test signal; The second delay providing unit includes: The second delay circuit is used to provide the second preset delay period; A third selector, wherein the first input terminal of the third selector is connected to the output terminal of the second selector through the second delay circuit, the second input terminal of the third selector is connected to the output terminal of the second selector, and the control terminal of the third selector receives the second test signal; In response to the first test signal being 0 and the second test signal being 0, the first delay providing unit does not provide the first preset delay period, and the second delay providing unit provides the second preset delay period, wherein the first time period is the second preset delay period; In response to the first test signal being 1 and the second test signal being 0, the first delay providing unit provides the first preset delay period, and the second delay providing unit provides the second preset delay period, wherein the first time period is the sum of the first preset delay period and the second preset delay period; In response to the first test signal being 1 and the second test signal being 1, the first delay providing unit provides the first preset delay period, and the second delay providing unit does not provide the second preset delay period, wherein the first time period is the first preset delay period.

6. The word line driving circuit according to claim 3, characterized in that, The first time period is determined based on the time required for the voltage on the word line to reach the turn-on stable voltage when the second voltage is used to drive it during the test. A portion of the plurality of delay providing units is selected based on the first time period, and the first time period is composed based on the preset delay period provided by the selected delay providing unit. The test signal used to select the plurality of delay providing units is burned into the electronic fuse of the random access memory so that after the test, the word line driving circuit reads the solidified test signal from the electronic fuse, thereby outputting the second voltage to the word line during the first time period.

7. The word line driving circuit according to claim 1, characterized in that, The control signal generation module includes: A comparison unit, wherein one input terminal of the comparison unit receives the turn-on stable voltage, another input terminal of the comparison unit is connected to the word line, and the output terminal of the comparison unit is connected to the control terminal of the first selector; Specifically, when the voltage fed back by the word line is less than the turn-on stable voltage, the control signal output by the comparator unit causes the first selector to select the output of the second voltage to drive the word line; when the voltage fed back by the word line is not less than the turn-on stable voltage, the control signal output by the comparator unit causes the first selector to select the output of the first voltage to drive the word line.

8. The word line driving circuit according to claim 1, characterized in that, The conduction stabilization voltage is 95% of the second voltage.

9. A random access memory, characterized in that, Includes the word line driving circuit as described in any one of claims 1-8.

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