A method, apparatus and packaging structure for batch reliability testing of semiconductors.

Abstract

This invention discloses a semiconductor batch reliability testing method, apparatus, and its packaging structure, enabling simultaneous testing of the failure reliability of a large batch of bare semiconductor devices using a single device. This packaging structure is highly versatile, requiring only slight adjustments based on the size of the samples under test; it is compact, allowing integration of multiple samples onto the same substrate; the process is mature and easy to implement in engineering; and the measurement terminals are independent, facilitating subsequent operations. By recording the breakdown rate at various time points in real time, monitoring results are obtained; based on these results, a distribution curve is generated to infer process problems, and further, the process can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor conformity testing technology, and in particular to a semiconductor batch reliability testing method, apparatus and its packaging structure. Background Technology

[0002] Reliability estimation of the dielectric layer is a crucial test item in the overall reliability estimation of semiconductor processes. Existing methods for dielectric layer reliability estimation include ramp voltage testing and related dielectric breakdown testing. These tests are used to evaluate the reliability of the dielectric layer. The ramp voltage testing method involves selecting a set of samples and applying a ramp voltage to the dielectric layer until it breaks down. The voltage applied at this point is the breakdown voltage of the dielectric layer. This breakdown voltage is then compared with an industry standard to determine whether the tested dielectric layer is affected by intrinsic factors, such as particulate contamination. If the breakdown voltage is greater than the industry standard, the tested dielectric layer meets the reliability requirements of the ramp voltage test.

[0003] Furthermore, the relevant dielectric breakdown test involves applying a TDDB test voltage to the dielectric layer of the semiconductor device test structure that needs to be tested, and the dielectric layer breaks down after a time t.

[0004] However, the traditional methods described above can only test individual devices separately using specialized instruments, and cannot test batches of semiconductor devices simultaneously. Furthermore, the test results cannot reveal problems in the manufacturing process, which is not conducive to the company's production efficiency. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method, apparatus and packaging structure for semiconductor batch reliability testing, to realize semiconductor batch reliability testing, and to identify errors in the process through the test results.

[0006] To solve the above problems, the technical solution of the present invention is,

[0007] A semiconductor batch reliability testing method, comprising,

[0008] The bare dies of the semiconductor devices in batches are uniformly packaged, and all electrodes of the bare dies of the semiconductor devices are brought out.

[0009] The bare dies of the semiconductor devices in batches are gathered onto a unified packaging substrate, and the packaging substrate is connected to a leakage current data acquisition device.

[0010] The test conditions are obtained by setting the magnitude of the voltage field and the temperature field temperature based on the known conditions.

[0011] Test the packaging substrate based on the test conditions and record the leakage current data of the semiconductor device until all the bare dies of the semiconductor device are broken down;

[0012] By recording the failure rate at each time point in real time, monitoring results are obtained;

[0013] Based on the monitoring results, a distribution curve is generated to infer production process issues.

[0014] Furthermore, the semiconductor device bare-die unified packaging method includes,

[0015] Recesses are etched into the selected substrate to accommodate the power semiconductor device under test.

[0016] The bare dies of the batch of semiconductor devices to be tested are connected to the substrate, and the drain terminals of the bare dies of the power semiconductor devices to be tested are led out through the first layer of the substrate.

[0017] Then, the gate and source terminals of the power semiconductor device under test are brought out through the second layer of traces.

[0018] Furthermore, the method for generating a distribution curve based on the monitoring results to infer production process problems includes:

[0019] Based on the monitoring results, a distribution curve is constructed, including a distribution curve showing the relationship between failure rate and electrical stress and a distribution curve showing the relationship between failure rate and thermal stress.

[0020] The curve showing the relationship between failure rate and electrical stress is shown, where the horizontal axis represents the voltage value and the vertical axis represents the failure rate.

[0021] The curve showing the relationship between failure rate and thermal stress is shown, where the horizontal axis represents temperature and the vertical axis represents failure rate.

[0022] The distribution curve is a broken line composed of several line segments, and each broken line segment corresponds to a process problem that causes failure.

[0023] Furthermore, by comparing the shape of the distribution curves, the reliability gap between different batches of bare dies of semiconductor devices can be obtained.

[0024] A unified mass production packaging structure for bare dies of semiconductor devices, comprising,

[0025] A packaging base plate, the packaging base plate comprising a first packaging base plate and a second packaging base plate;

[0026] The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer;

[0027] The second layer of the packaging substrate is provided with a second copper layer, and the source and gate of the power semiconductor device under test are led out from the second copper layer.

[0028] Furthermore, the first copper-clad layer is disposed inside the first layer of the packaging substrate, and the first copper-clad layer leads out the drain of the power semiconductor device under test through the internal electrical connection of the first layer of the packaging substrate.

[0029] The second copper cladding layer includes an upper copper cladding layer and a lower copper cladding layer. The upper copper cladding layer leads out the gate of the power semiconductor device under test, and the lower copper cladding layer leads out the source of the power semiconductor device under test.

[0030] The copper overlay layer is electrically connected between the first and second packaging substrates to lead out the gate of the power semiconductor device under test.

[0031] The lower copper layer is electrically connected to the drain of the power semiconductor device under test through the bottom of the second layer packaging substrate.

[0032] Furthermore, the first layer of the encapsulation base plate and the second layer of the encapsulation base plate are arranged to overlap vertically;

[0033] The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer;

[0034] The second layer of the package substrate is provided with a second copper layer, which includes an upper copper layer and a lower copper layer. The upper copper layer passes through the second layer of the package substrate to lead out the gate and source of the power semiconductor device under test.

[0035] The lower copper layer is electrically connected to the first copper layer and leads out to the drain of the power semiconductor device under test through the second packaging substrate.

[0036] A semiconductor batch reliability testing device, comprising,

[0037] The host computer further includes a storage module, which is used to save the process problem report and perform feature classification and storage on the process problem report;

[0038] The lower-level machine includes,

[0039] A variable positive electric field generator module, wherein the variable positive electric field generator module receives detection conditions sent by the host computer and provides a variable voltage source that meets the conditions for reliability detection;

[0040] A controllable high-temperature generator module, wherein the controllable high-temperature generator module receives detection conditions from the host computer and provides a temperature environment that meets the conditions for reliability testing;

[0041] Leakage current data acquisition module, which is used to acquire real-time leakage current information of the test device and transmit the real-time leakage current information back to the host computer;

[0042] The host computer receives and records the leakage current information in real time, matches it with the issued detection conditions, and generates a process problem report.

[0043] Furthermore, the leakage current data acquisition module includes a current mirror module, a leakage current amplification module, and a voltage data acquisition module;

[0044] The current mirror module is used to obtain the current value passing through the bare die of the semiconductor device. The current mirror module uses a Wilson current mirror circuit to copy the leakage current passing through the bare die of the semiconductor device. The mirror circuit is constructed using multiple PNP transistors, of which there are three PNP transistors. The measured current is "copied" and exported to the leakage current amplification module.

[0045] The leakage current amplification module is used to amplify the small leakage current in the nanoampere (nA) range generated by the bare die of the semiconductor device under test during accelerated stress testing;

[0046] The voltage data acquisition module is used to input the multi-channel signals amplified by the amplification module into the sampling circuit to complete the voltage value acquisition and automatically calculate the current value according to Ohm's law. The value is then transmitted to the host computer for analysis through the set serial port.

[0047] Furthermore, the variable positive electric field generator includes an AC input module, an AC / DC conversion section, and a voltage adjustment module;

[0048] The AC input module is used to connect to the mains power network for power supply and to transform the input voltage to an appropriate voltage value through a transformer.

[0049] The AC / DC converter module converts AC power into single-pulse DC power through full-bridge rectification, and then rectifies and improves the stability of the voltage output through an LC filter circuit.

[0050] The voltage adjustment module includes a voltage adjustment output circuit, a feedback amplifier circuit, and a reference voltage circuit.

[0051] The voltage adjustment output circuit utilizes the voltage control function of a transistor to achieve voltage adjustment;

[0052] The feedback amplifier circuit uses the output value connected to the input terminal to achieve negative feedback to control the voltage output;

[0053] The reference voltage circuit provides a stable reference voltage, which in turn provides input to the feedback amplifier circuit. Ultimately, the system can output a stable variable electric field.

[0054] Furthermore, the controllable high-temperature generator includes a main control module, a heating control module, a temperature detection module, and a silicone heating module;

[0055] The main control module is a microcontroller that receives control signals from the host computer and forwards them to the heating control module, uploads real-time temperature data, and executes temperature control algorithms.

[0056] The heating control module is used to convert the control signal from the microcontroller into a high current through a power amplifier to control the temperature rise of the silicone heating pad.

[0057] The temperature detection module measures the real-time temperature through a thermocouple contact with an adjustable temperature silicone pad module. It achieves accurate temperature measurement through cold junction compensation, converts the temperature value into a voltage value, and inputs it into the control module.

[0058] The silicone heating module is used to embed a nickel alloy heating wire into a silicone insulating layer to achieve high-efficiency heating.

[0059] The beneficial effects of this invention are as follows: a batch of bare dies of semiconductor devices under test are uniformly packaged, and reliability experiments are conducted on the batch of bare dies of semiconductor devices. By recording the breakdown rate at each time point in real time, monitoring results are obtained. Based on the monitoring results, a distribution curve is generated to infer process problems. Furthermore, the process can be improved to increase the production efficiency of enterprises.

[0060] A large-scale testing packaging structure is proposed, enabling a single device to simultaneously test the failure reliability of several bare semiconductor devices. This packaging structure is highly versatile, requiring only slight adjustments based on the size of the sample under test; it is compact, allowing integration of several samples onto the same substrate; the process is mature and easy to implement in engineering; and the measurement terminals are independent, facilitating subsequent operations.

[0061] In this three-layer PCB structure, each copper layer provides a conductive path from the gate, source, and drain of the power semiconductor device under test to the port under test, thus avoiding the situation where the leads are intertwined and cannot be connected to the port when many power devices under test are integrated on a single substrate.

[0062] The grooves etched on the substrate facilitate the interconnection between the bare die of the semiconductor device under test and the substrate, as well as the lead-out of the gate and source. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the packaging structure according to an embodiment of the present invention;

[0064] Figure 2 This is a system block diagram of an embodiment of the present invention.

[0065] Figure 3This is a schematic diagram of the distribution curve in an embodiment of the present invention;

[0066] Figure 4 This is a flowchart illustrating the functional implementation of the testing device according to an embodiment of the present invention;

[0067] Figure 5 This is a graph showing the relationship between failure rate and electrical stress in an embodiment of the present invention;

[0068] Figure 6 This is a graph showing the relationship between failure rate and thermal stress in an embodiment of the present invention;

[0069] Figure 7 This is a block diagram of the variable positive electric field module according to an embodiment of the present invention;

[0070] Figure 8 This is the controllable high-temperature generator module of this invention embodiment;

[0071] Figure 9 This is a system block diagram of the current data acquisition module according to an embodiment of the present invention;

[0072] Figure 10 This is a schematic diagram of the packaging structure of Embodiment 2 of the present invention;

[0073] Figure 11 This is a schematic diagram of the packaging structure of Embodiment 2 of the present invention from another perspective;

[0074] Figure 12 This is a schematic diagram of the packaging structure of Embodiment 3 of the present invention;

[0075] Figure 13 This is a schematic diagram of the packaging structure of Embodiment 3 of the present invention from another perspective;

[0076] Figure 14 This is a schematic diagram of the equivalent circuit of the packaging structure in an embodiment of the present invention. Detailed Implementation

[0077] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0078] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0079] Example 1

[0080] Please see Figure 1 The present invention provides a detection method, comprising the following steps:

[0081] S1 customizes multiple packages based on the bare die of the semiconductor device under test, and brings out all the electrodes of the semiconductor device;

[0082] Specifically, the packaging substrate includes a ceramic copper-clad laminate (DCB) and a printed circuit board (PCB). The method of leading out all the electrodes of the semiconductor devices includes wire bonding or surface mount bonding. Since the TDDB test needs to be performed under different temperatures and forward voltages, it is necessary to repeat step S1 to make enough bare dies with customized packaging ready for use.

[0083] Specific methods:

[0084] S11 selects several packaging substrates based on the temperature environment required for the relevant dielectric breakdown test;

[0085] Specifically, depending on the temperature environment required for the relevant dielectric breakdown test (TDDB), the packaging substrate should be selected from either a ceramic copper-clad laminate (DCB) suitable for higher temperatures or a printed circuit board (PCB) suitable for lower temperatures.

[0086] S12 performs batch mounting of bare dies on several of the said packaging substrates and brings out the electrodes of all the said semiconductor devices.

[0087] Specifically, the bare die is batch-bonded (Die Bonding) with a batch size of N, and then all the electrodes of the semiconductor devices (such as the gate of a field-effect transistor) are brought out.

[0088] S2 gathers the electrodes of the semiconductor device onto the packaging substrate and connects the packaging substrate to the leakage current data acquisition device;

[0089] Specifically, each semiconductor device can be considered as a 'capacitor', such as a gate MOS structure. Through wire bonding, the two ends of N 'capacitors' can be unified onto the packaging substrate. The leakage current data acquisition device is connected to a variable electric field generator (such as a 0-200V DC regulated voltage source). Alternatively, the packaging substrate can be placed in a 'variable temperature field' (such as a flexible temperature-adjustable silicone plate).

[0090] S3 sets the voltage field magnitude and temperature field temperature based on known conditions to obtain the test conditions;

[0091] Specifically, the known conditions are the conditions required for the relevant dielectric breakdown test, and the voltage field strength applied to the semiconductor device is calculated as 'voltage source output voltage / semiconductor device thickness'.

[0092] S4 tests the packaging substrate based on the test conditions. The leakage current data acquisition device uploads the data to the computer terminal. The computer terminal records the leakage current in real time through a preset program until the semiconductor device is completely broken down.

[0093] Specific methods:

[0094] S41 tests the package substrate under the test conditions to obtain the leakage current;

[0095] Specifically, in this test, N capacitors will generate leakage current after a positive electric field is applied.

[0096] S42 The leakage current data acquisition device collects and amplifies the leakage current and uploads it to the computer terminal;

[0097] Specifically, the leakage current of N channels is amplified by the data acquisition unit, and the real-time leakage current is indirectly obtained by monitoring the voltage of the sampling resistor in real time.

[0098] The computer terminal described in S43 records the leakage current in real time through a preset program until all the semiconductor devices are broken down.

[0099] Specific methods:

[0100] The computer terminal described in S431 records the leakage current value in real time through a preset program. If the leakage current of a certain channel of the packaging substrate suddenly increases beyond the threshold, it is determined that the channel has broken down. The semiconductor device in that channel is recorded as damaged at this time, and the channel is shut down. Other channels continue to operate until all semiconductor devices have broken down.

[0101] S5 records the breakdown rate at each time point in real time through the preset program to obtain the monitoring results;

[0102] Specifically, after completing the specific electric field strength and temperature conditions, steps 3-5 can be repeated to change the electric field strength and / or temperature, and the breakdown rate under each condition can be recorded.

[0103] Specific methods:

[0104] S51 repeatedly changes the electric field strength and temperature of the packaging substrate, records the breakdown rate under various conditions and at various time points, and obtains the monitoring results.

[0105] The preset program described in S6 generates a distribution curve based on the monitoring results to infer process problems.

[0106] Specific methods:

[0107] The preset program in S61 generates a distribution curve based on the monitoring results;

[0108] Specifically, the distribution curve is a time-failure distribution curve.

[0109] S62 analyzes and determines whether the lifespan of the batch of semiconductor devices meets the requirements based on the distribution curve;

[0110] S63 infers problems in the semiconductor device process based on the abnormalities in the distribution curves. The distribution curves include curves showing the relationship between failure rate and electrical stress, and curves showing the relationship between failure rate and thermal stress.

[0111] The curve showing the relationship between failure rate and electrical stress is shown, where the horizontal axis represents the voltage value and the vertical axis represents the failure rate.

[0112] The curve showing the relationship between failure rate and thermal stress is shown, where the horizontal axis represents temperature and the vertical axis represents failure rate.

[0113] The distribution curve is a broken line composed of several line segments, and each broken line segment corresponds to a process problem that causes failure.

[0114] Example 2

[0115] like Figure 10-11 As shown, a packaging structure includes,

[0116] A packaging base plate, the packaging base plate comprising a first packaging base plate and a second packaging base plate;

[0117] The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer; the first copper layer is disposed inside the first layer of the packaging substrate, and the drain of the power semiconductor device under test is led out from the first layer of the packaging substrate through internal electrical connection.

[0118] The second layer of the packaging substrate is provided with a second copper layer, and the second copper layer leads out the source and gate of the power semiconductor device under test; the second copper layer includes an upper copper layer and a lower copper layer, the upper copper layer leads out the gate of the power semiconductor device under test, and the lower copper layer leads out the source of the power semiconductor device under test;

[0119] The upper copper layer leads out the gate of the power semiconductor device under test through an electrical connection between the first and second packaging substrates; the lower copper layer leads out the source of the power semiconductor device under test through an electrical connection at the bottom of the second packaging substrate.

[0120] like Figure 10-11 The packaging substrate uses a three-layer PCB with a TG value of 170. The first and second copper layers of the packaging substrate undergo immersion nickel-palladium-gold (NPG) surface treatment, depositing 3-5 microinches of NPG. The bare die of the power device under test (DUT) is electrically connected to the first copper layer of the packaging substrate via a eutectic bonding process, and then a drain terminal is formed on the first copper layer. The gate of the DUT is connected to the pads of the upper copper layer, which have undergone NPG treatment using ultrasonic bonding, using the same technique. Similarly, the source of the DUT is connected to the pads of the lower copper layer, also treated with the same ultrasonic bonding process using NPG.

[0121] The upper copper layer leads out the gate of the power semiconductor device under test through the electrical connection between the first and second packaging substrates. The gate is finally led out as a gate terminal on the first packaging substrate. The lower copper layer leads out the source of the power semiconductor device under test through the electrical connection at the bottom of the second packaging substrate. The source is finally led out as a source terminal on the first packaging substrate.

[0122] Example 3

[0123] like Figure 12-13 As shown, a packaging structure includes,

[0124] The packaging base plate includes a first packaging base plate and a second packaging base plate; the first packaging base plate and the second packaging base plate are arranged to overlap vertically.

[0125] The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer;

[0126] The second layer of the package substrate is provided with a second copper layer, which includes an upper copper layer and a lower copper layer. The upper copper layer passes through the second layer of the package substrate to lead out the gate and source of the power semiconductor device under test.

[0127] The lower copper layer is electrically connected to the first copper layer and leads out to the drain of the power semiconductor device under test through the second packaging substrate.

[0128] The packaging substrate is a ceramic copper-clad board. The first copper layer of the first packaging substrate is chemically etched to form a groove. Then, the bare core of the power semiconductor device under test is soldered into the groove through a eutectic bonding process. The drain of the MOSFET power semiconductor device under test is connected to the first copper layer. The drain of the power semiconductor device under test is led out from the first copper layer.

[0129] The first copper-clad layer is then connected to the second copper-clad layer via high-temperature conductive silver paste.

[0130] The copper layer on the second-layer package substrate extends through the second-layer package substrate to lead out the gate of the power semiconductor device under test, and the copper layer on the second-layer package substrate extends through the second-layer package substrate to lead out the source of the power semiconductor device under test.

[0131] The gate, source, and drain are ultimately led out to terminals on the upper layer of the second-layer package substrate.

[0132] Example 4

[0133] like Figure 2 , 4 As shown in 7-9

[0134] A semiconductor batch reliability testing device, comprising,

[0135] The host computer repeatedly changes the detection conditions, which are the electric field strength and temperature of the packaging substrate, and records the breakdown rate under each condition and at each time point to obtain the monitoring results.

[0136] The lower-level machine includes,

[0137] A variable positive electric field generator module, wherein the variable positive electric field generator module receives detection conditions sent by the host computer and provides a variable voltage source that meets the conditions for reliability detection; Figure 7 The variable positive electric field generator includes an AC input module, an AC-DC conversion section, and a voltage adjustment module. The AC input module is used to connect to the mains power network and convert the input voltage to an appropriate value via a transformer. The AC-DC conversion module converts the AC power into single-pulse DC power through a full-bridge rectifier, and then further rectifies and improves the stability of the output voltage through an LC filter circuit.

[0138] The voltage regulation section includes a voltage regulation output circuit, a feedback amplifier circuit, and a reference voltage circuit. The voltage output regulation circuit uses the control of the voltage by a transistor to achieve voltage regulation. The feedback amplifier circuit uses the output value connected to the input terminal to achieve negative feedback to control the voltage output. The reference voltage circuit provides a stable reference voltage and provides input to the feedback amplifier circuit. Finally, the system can output a stable variable electric field.

[0139] The controllable high temperature generator module receives the detection conditions sent by the host computer and provides a temperature environment that meets the conditions for reliability testing. The preferred controllable high temperature generator is a flexible adjustable temperature silicone plate, which encapsulates the device under test on the PCB into the adjustable temperature silicone plate to create a temperature chamber environment. Figure 8 As shown, the controllable high-temperature generator module includes a main control module, a heating control module, a temperature detection module, and a silicone heating module. The main control module is a microcontroller, whose main functions are to receive control signals from the host computer and forward them to the heating control module, upload real-time temperature data, and execute temperature control algorithms. Heating control: This mainly converts the microcontroller's control signals into a high-current control for the silicone heating pad's temperature rise through a power amplifier. Temperature detection module: This measures the real-time temperature of the adjustable-temperature silicone pad module through thermocouple contact. Using cold junction compensation, it achieves accurate temperature measurement, converts the temperature value into a voltage value, and inputs it to the control module. Silicone heating module: This module embeds a nickel alloy heating wire into a silicone insulating layer, enabling high-efficiency heating.

[0140] Leakage current data acquisition module, which is used to acquire real-time leakage current information of the test device and transmit the real-time leakage current information back to the host computer; Figure 9 As shown, the leakage current data acquisition module includes a current mirror module, a leakage current amplification module, and a voltage data acquisition module. The current mirror module accurately obtains the current value passing through the MOSFET. It uses a Wilson current mirror circuit to replicate the leakage current through the semiconductor device. The mirror circuit is constructed using three PNP transistors, perfectly "copying" the measured current and exporting it to the leakage current amplification module. The main function of the leakage current amplification module is to amplify the small nanoampere (nA) leakage current generated by the device under test during TDDB accelerated stress testing, facilitating subsequent data acquisition. The main function of the voltage data acquisition module is to connect the amplified multiple signals from the amplification module to a sampling circuit (such as a 120-ohm sampling resistor) to acquire voltage values ​​and automatically calculate the current value according to Ohm's law. The values ​​are then transmitted to the host computer via a serial port for analysis. This part requires the manufacture of multiple single modules to simultaneously connect multiple semiconductor devices under test for parallel testing.

[0141] The host computer receives the leakage current information and matches it with the issued detection conditions to generate a process problem report. The process problem report is obtained by back-calculating the distribution curve based on the monitoring results through a preset program.

[0142] A packaging structure for packaging test devices, wherein the packaging structure is customized with multiple packages based on the bare die of the semiconductor device under test, leading out all terminals of the semiconductor device; the structure includes...

[0143] The packaging substrate, specifically, includes a ceramic copper-clad laminate (DCB) and a printed circuit board (PCB). The method of bringing out all the terminals of the semiconductor devices includes wire bonding or surface mount bonding.

[0144] A copper-clad structure, wherein the copper-clad structure covers the packaging substrate;

[0145] A packaging cover plate is provided with a drain copper-clad structure, a source copper-clad structure and a gate copper-clad structure. The leakage current data acquisition module is connected to the drain copper-clad structure and the source copper-clad structure to acquire the real-time leakage current information of the test device, or the leakage current data acquisition module is connected to the drain copper-clad structure and the gate copper-clad structure to acquire the real-time leakage current information of the test device.

[0146] The source copper-clad structure and the gate copper-clad structure are electrically connected to the test device; the electrical connection can be any one of solder connection, conductive adhesive connection, or eutectic connection.

[0147] The copper-clad drain structure includes a first copper-clad drain structure and a second copper-clad drain structure, both of which are electrically connected to the copper-clad drain structure.

[0148] The host computer also includes a storage module, which is used to save the process problem report and classify the process problem report by feature for easy data retrieval and reference in the future.

[0149] The test device is electrically connected to the copper-clad structure.

[0150] Figure 5-6 As shown, the process problem report is obtained by back-calculating the distribution curve based on the monitoring results through a preset program.

[0151] Three measurement modes were performed, among which (A) and (B) can be used to infer potential problems in the production process;

[0152] Figure 5 The x-axis is E ox (Right now The vertical axis represents the failure rate; Figure 5 This is a graph showing the relationship between failure rate and electrical stress.

[0153] Figure 5 Different colors represent different batches of devices under test, the horizontal axis represents the voltage value, and the temperature of all products is controlled at the current room temperature. Breakdown can be roughly divided into three stages, caused by different mechanisms. Mechanism 1 is caused by doping or the formation of porous oxides due to the manufacturing process; Mechanism 2 is caused by oxide layer thinning. Mechanisms 1 and 2 are caused by external factors. Mechanism 3 is breakdown caused by electrical stress reaching the inherent limits of the device.

[0154] Based on this analysis, M1 may have experienced all external breakdowns, indicating that its manufacturing process is poor. Compared with M3, M2 has more external breakdowns and they occur earlier. M3 has less failure rate increase due to external breakdowns, and the failure mainly occurs due to inherent breakdown represented by mechanism 3. Overall, M2 and M3 have better reliability.

[0155] Figure 6 The horizontal axis represents temperature T, and the vertical axis represents the failure rate. Figure 6 This is a graph showing the relationship between failure rate and thermal stress.

[0156] Similar to applied voltage-accelerated stress, applying thermal-accelerated stress can also cause premature breakdown in products. Since the tested semiconductor device is an unpackaged bare die, temperature transfer and temperature differences at different locations do not need to be considered, allowing for uniform heating of the device. Figure 6 Analysis shows that M1 has poor reliability, with most breakdowns caused by external factors 1 and 2. Similarly, it can be inferred that M2 has better reliability and temperature resistance than M1, but it can still break down due to external factors, with breakdown points mainly occurring above 120℃. M3 has the best reliability and temperature resistance, rarely experiencing an increase in failure rate due to external breakdowns, with breakdown points mainly occurring above 140℃.

[0157] The failure rate is F ti ;in,

[0158]

[0159] In the formula, i is the rank of the failure time (i≤N), and N is the number of samples of the tested MOS. The failure rate at each device failure can be obtained from formula (1). In the case of a small sample size (N<30), or when there is no available median rank table, the optimized F can be calculated using formula (2). ti :

[0160]

[0161] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A semiconductor batch reliability testing method, characterized in that, include, The bare dies of a batch of semiconductor devices are uniformly packaged, and all electrodes of the bare dies of the semiconductor devices are brought out. The bare dies of the semiconductor devices in batches are collected onto a unified packaging substrate, and the unified packaging substrate is connected to a leakage current data acquisition device. The test conditions are obtained by setting the magnitude of the voltage field and the temperature field temperature based on the known conditions. Based on the test conditions, the unified packaging substrate is connected for testing, and the leakage current data of the semiconductor device is collected until all the bare dies of the semiconductor device are broken down. By recording the failure rate at each time point in real time, monitoring results are obtained; Based on the monitoring results, a distribution curve is generated to infer production process issues.

2. The semiconductor batch reliability testing method according to claim 1, characterized in that, The semiconductor device bare die unified packaging method includes, Recesses are etched into the selected substrate to accommodate the power semiconductor device under test. The bare dies of the batch of semiconductor devices to be tested are connected to the substrate, and the drain terminals of the bare dies of the power semiconductor devices to be tested are led out through the first layer of the substrate. Then, the gate and source terminals of the power semiconductor device under test are brought out through the second layer of traces.

3. The semiconductor batch reliability testing method according to claim 1, characterized in that, The method for generating distribution curves based on the monitoring results to infer production process problems includes, Based on the monitoring results, a distribution curve is constructed, including a distribution curve showing the relationship between failure rate and electrical stress and a distribution curve showing the relationship between failure rate and thermal stress. The curve showing the relationship between failure rate and electrical stress is shown, where the horizontal axis represents the voltage value and the vertical axis represents the failure rate. The curve showing the relationship between failure rate and thermal stress is shown, where the horizontal axis represents temperature and the vertical axis represents failure rate. The distribution curve is a broken line composed of several line segments, and each broken line segment corresponds to a process problem that causes failure.

4. The semiconductor batch reliability testing method according to claim 3, characterized in that, The reliability gap between different batches of bare dies of semiconductor devices is obtained by comparing the shape of the distribution curves.

5. The semiconductor batch reliability testing method according to any one of claims 1-4, characterized in that, include A unified packaging structure for bare die batches of semiconductor devices used for batch reliability testing of semiconductors. The semiconductor device bare die mass production unified packaging structure includes: A packaging base plate, the packaging base plate comprising a first packaging base plate and a second packaging base plate; The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer; The second layer of the packaging substrate is provided with a second copper layer, and the source and gate of the power semiconductor device under test are led out from the second copper layer.

6. The semiconductor batch reliability testing method according to claim 5, characterized in that, The first copper layer is disposed inside the first layer of the packaging substrate, and the first copper layer is electrically connected to the drain of the power semiconductor device under test through the internal electrical connection of the first layer of the packaging substrate. The second copper cladding layer includes an upper copper cladding layer and a lower copper cladding layer. The upper copper cladding layer leads out the gate of the power semiconductor device under test, and the lower copper cladding layer leads out the source of the power semiconductor device under test. The copper overlay layer is electrically connected between the first and second packaging substrates to lead out the gate of the power semiconductor device under test. The lower copper layer is electrically connected to the drain of the power semiconductor device under test through the bottom of the second layer packaging substrate.

7. The semiconductor batch reliability testing method according to claim 6, characterized in that, The first layer of the encapsulation base plate and the second layer of the encapsulation base plate are arranged overlapping each other vertically. The first layer of the packaging substrate is provided with a first copper layer, and the drain of the power semiconductor device under test is led out from the first copper layer; The second layer of the package substrate is provided with a second copper layer, which includes an upper copper layer and a lower copper layer. The upper copper layer passes through the second layer of the package substrate to lead out the gate and source of the power semiconductor device under test. The lower copper layer is electrically connected to the first copper layer and leads out to the drain of the power semiconductor device under test through the second packaging substrate.

8. The semiconductor batch reliability testing method according to any one of claims 1-4, characterized in that, include A semiconductor batch reliability testing device for use in semiconductor batch reliability testing. The semiconductor batch reliability testing device includes, The host computer further includes a storage module, which is used to save the process problem report and perform feature classification and storage on the process problem report; The lower-level machine includes, A variable positive electric field generator module, wherein the variable positive electric field generator module receives detection conditions sent by the host computer and provides a variable voltage source that meets the conditions for reliability detection; A controllable high-temperature generator module, wherein the controllable high-temperature generator module receives detection conditions from the host computer and provides a temperature environment that meets the conditions for reliability testing; Leakage current data acquisition module, which is used to acquire real-time leakage current information of the test device and transmit the real-time leakage current information back to the host computer; The host computer receives and records the leakage current information in real time, matches it with the issued detection conditions, and generates a process problem report.

9. The semiconductor batch reliability testing method according to claim 8, characterized in that, The leakage current data acquisition module includes a current mirror module, a leakage current amplification module, and a voltage data acquisition module. The current mirror module is used to obtain the current value passing through the bare die of the semiconductor device. The current mirror module uses a Wilson current mirror circuit to copy the leakage current passing through the bare die of the semiconductor device. The mirror circuit is constructed using multiple PNP transistors and "copies" the current to be measured and outputs it to the leakage current amplification module. The leakage current amplification module is used to amplify the small leakage current in the nanoampere (nA) range generated by the bare die of the semiconductor device under test during accelerated stress testing; The voltage data acquisition module is used to input the multi-channel signals amplified by the amplification module into the sampling circuit to complete the voltage value acquisition and automatically calculate the current value according to Ohm's law. The value is then transmitted to the host computer for analysis through the set serial port.

10. The semiconductor batch reliability testing method according to claim 8, characterized in that, The variable positive electric field generator includes an AC input module, an AC-DC conversion section, and a voltage adjustment module; The AC input module is used to connect to the mains power network for power supply and to transform the input voltage to an appropriate voltage value through a transformer. The AC / DC conversion section converts AC power into single-pulse DC power through full-bridge rectification, and then rectifies and improves the stability of the voltage output through an LC filter circuit. The voltage adjustment module includes a voltage adjustment output circuit, a feedback amplifier circuit, and a reference voltage circuit. The voltage adjustment output circuit utilizes the voltage control function of a transistor to achieve voltage adjustment; The feedback amplifier circuit uses the output value connected to the input terminal to achieve negative feedback to control the voltage output; The reference voltage circuit provides a stable reference voltage, which serves as the input to the feedback amplifier circuit and outputs a stable variable electric field.

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