A power mosfet device with wide safe operating area and its fabrication process
By combining U-MOSFET and VD-MOSFET structures, optimizing the carrier path, extending the safe operating area of power MOSFET devices, solving the failure problem caused by the electro-thermal hybrid effect, and achieving a balance between low on-resistance and high withstand voltage.
CN116454133BActive Publication Date: 2026-07-24WILL SEMICON (SHANGHAI) CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WILL SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2022-12-15
- Publication Date
- 2026-07-24
AI Technical Summary
Technical Problem
Existing power MOSFET devices are prone to failure due to electro-thermal hybrid effects under high voltage and high current conditions, and traditional optimization methods increase cost and chip area.
Method used
By combining U-MOSFET and VD-MOSFET structures, and by paralleling gates with different dynamic switching characteristics inside the device, the carrier path is optimized, the field ionization effect is reduced, and a multi-layer gate and doped region design is adopted to extend the safe operating area.
Benefits of technology
This achieves low on-resistance and high withstand voltage while expanding the safe operating area of the device, reducing the risk of thermal failure, and improving the reliability and efficiency of the device.
✦ Generated by Eureka AI based on patent content.
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Figure CN116454133B_ABST
Abstract
The embodiment of the application provides a power MOSFET device with a wide safe operating area and a preparation process, which comprises a first gate and a second gate connected with each other; an epitaxial layer is arranged on the upper surface of a substrate; a first groove and a second groove are arranged in the epitaxial layer; a gate oxide layer is arranged on the sidewall of the first groove, the sidewall of the second groove and the upper surface of the epitaxial layer; the first groove and the second groove are filled with a first polysilicon to form the first gate; a first doped region is arranged in the epitaxial layer; a second doped region is arranged in the first doped region; the first groove and the second groove are arranged in the first doped region and the second doped region from top to bottom; a second polysilicon is arranged on the upper surface of the epitaxial layer to form the second gate; the second polysilicon is arranged above the region between adjacent first doped regions and on the upper surface of the gate oxide layer; and the application realizes a power MOSFET device with good FBSOA performance and low on-resistance.
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