Low power consumption under-voltage protection circuit based on charge redistribution

Abstract

The present application belongs to the field of analog integrated circuit design, and particularly relates to a low-power consumption under-voltage protection circuit based on charge redistribution. The circuit comprises a clock control circuit, a charge redistribution circuit and a latch circuit. The clock control circuit generates a clock signal required by the under-voltage protection circuit. The charge redistribution circuit is controlled by a Timer timer output signal, an EN enable signal and an ENB enable signal. When the Timer timer output signal is at a low level, the circuit charges a first capacitor C1 and a fourth capacitor C4. When the Timer timer output signal is at a high level, a same-phase input end of the latch circuit is connected to a second capacitor C2, and a charge redistribution occurs at a same-phase input end voltage Vip. When a low level of a clock signal CLK3 arrives, the latch L1 rapidly enters a comparison stage. If an under-voltage occurs at this time, the same-phase end voltage Vip of the latch L1 will be less than Vin, and an under-voltage protection signal UVLO_OK is output at a low level, and other circuit modules of the chip are closed. The circuit does not have static power consumption, and the designed under-voltage protection threshold is 1.622 V.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, specifically relating to a low-power undervoltage protection circuit based on charge redistribution. Background Technology

[0002] With the development of integrated circuit technology, low-power chips are widely used in consumer electronics, industrial automation control, communications, and many other fields. When a chip operates at a power supply voltage below its normal operating range, it may generate logic errors or even be damaged. Adding an undervoltage protection short circuit to the chip ensures that it always operates within a safe power supply voltage range. When an undervoltage occurs, it sends a shutdown signal to the outside, effectively improving system stability. Currently, traditional undervoltage protection circuits use a resistor divider to obtain the power supply sampling voltage. This sampling voltage is compared with a reference threshold voltage by a comparator, and the high or low potential of the undervoltage protection signal is determined based on their magnitude. A small value for the voltage divider resistor will result in excessive power consumption, while a large value will result in an excessively large layout area. Furthermore, in traditional undervoltage protection circuits, the comparator is always active, resulting in significant static power consumption.

[0003] Currently, a mainstream approach to achieving low power consumption in chips is through the enabling control of low-power clocks and timers, enabling the chip to periodically wake up and sleep: in the wake-up state, all internal circuit modules are enabled and operate; in the sleep state, all circuit modules are turned off, with only the built-in low-power clock and timer operating. This reduces the chip's average power consumption.

[0004] In traditional undervoltage protection circuits, using a small voltage divider resistor results in excessive power consumption, while using a large voltage divider resistor leads to an excessively large layout area and significantly increased cost. Furthermore, the comparator in traditional undervoltage protection circuits is always operational, resulting in substantial static power consumption. Therefore, these circuits cannot meet the undervoltage protection requirements of low-power chips. Summary of the Invention

[0005] To address the problems of power consumption and layout area in traditional undervoltage protection circuits, this invention proposes an undervoltage protection circuit for low-power chips.

[0006] The technical solution of this invention is as follows:

[0007] A low-power undervoltage protection circuit based on charge redistribution includes a clock control circuit and a charge redistribution circuit.

[0008] The clock control circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a first NAND gate NAND1, a second NAND gate NAND2, a first voltage level converter LS1, and a first NOR gate NOR1.

[0009] The input of the first inverter INV1 is connected to an external input signal CLK. The output of the first inverter INV1 is connected to the input of the second inverter INV2. The output signal of the first inverter INV1 is named CLK1, and the output signal of the second inverter INV2 is named CLK2. The D terminal of the first D flip-flop DFF1 is connected to the input of the second inverter DFF2. The reset terminals of the first and second D flip-flops, DFF1 and DFF2, are connected to the signal RST. The Clk terminal of the first D flip-flop, DFF1, is connected to the signal CLK1. The Q signal of the first D flip-flop, DFF1, is named D2. The terminal signal is named D2N, and the D terminal of the second D flip-flop DFF2 is connected to the second D flip-flop DFF2. The Q signal of the second D flip-flop DFF2 is named D4. One end of the first NAND gate NAND1 is connected to signal D4, and the other end of the first NAND gate NAND1 is connected to signal D2N. The output of the first NAND gate NAND1 is connected to the D terminal of the third D flip-flop DFF3. The Clk terminal of the third D flip-flop DFF3 is connected to signal CLK2. The Q terminal of the third D flip-flop DFF3 is connected to one end of the first level converter LS1. The other end of the first level converter LS1 is connected to the input of the third inverter INV3. The output signal of the Q terminal of the third D flip-flop DFF3 is named Timer_N. The output signal of the first inverter is named Timer_P, the output signal of the third inverter INV3 is named RST, the output signal of the first voltage level converter LS1 is named Timer, the input of the fourth inverter INV4 is connected to the signal Timer, the output of the fourth inverter INV4 is connected to the input of the fifth inverter INV5, the output of the fifth inverter INV5 is connected to the input of the sixth inverter INV6, the output of the sixth inverter INV6 is connected to the input of the seventh inverter INV7, and the output of the seventh inverter INV7 is connected to one of the second NAND gates NAND2. The first NOR gate is connected to the second NAND gate. The other end of the second NAND gate is connected to the signal Timer. The output of the second NAND gate is connected to the input of the eighth inverter INV8. The output signal of the second NAND gate is named ENB. The output signal of the eighth inverter INV8 is named EN. One input of the first NOR gate is connected to the external clock signal CLK. The other input of the first NOR gate is connected to the signal ENB. The output of the first NOR gate is connected to the input of the ninth inverter INV9. The output signal of the ninth inverter INV9 is named CLK3.

[0010] The charge redistribution circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a latch L1.

[0011] The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to a signal timer. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are all connected to the power supply AVDD. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, one end of the first capacitor C1, one end of the second capacitor C2, and the Vip terminal of latch L1. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, one end of the fourth capacitor C4, and the Vin terminal of latch L1. The drain of the third PMOS transistor MP3 is connected to the first NMOS transistor... The drain of MN1 is connected to the other end of the second capacitor C2. The gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are connected to the signal EN. The source of the first NMOS transistor MN1, the other end of the first capacitor C1, one end of the third capacitor C3 and the other end of the fourth capacitor C4 are connected to the reference ground AGND. The source of the second NMOS transistor MN2 is connected to one end of the first resistor R1 and the other end of the third capacitor C3. The other end of the first resistor R1 is connected to the voltage signal VBG. The clock input of latch L1 is connected to the clock signal CLK3. The output signal of latch L1 is named UVLO_OK.

[0012] The latch L1 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth inverter INV10.

[0013] The gate of the fourth PMOS transistor MP4 is connected to the drain of the fifth PMOS transistor MP5, the drain of the seventh PMOS transistor MP7, the gate of the eleventh PMOS transistor MP11, the gate of the fifth NMOS transistor MN5, the drain of the sixth NMOS transistor MN6, and the gate of the eighth NMOS transistor MN8. The source of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the source of the seventh PMOS transistor MP7, the source of the eighth PMOS transistor MP8, the source of the ninth PMOS transistor MP9, the source of the tenth PMOS transistor MP10, and the gate of the eleventh PMOS transistor MN8. The source of P11 is connected to the power supply AVDD. The drain of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the drain of the sixth PMOS transistor MP6, the gate of the tenth PMOS transistor MP10, the drain of the fifth NMOS transistor MN5, the gate of the sixth NMOS transistor MN6, and the gate of the seventh NMOS transistor MN7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth PMOS transistor MP8. The gate of the seventh PMOS transistor MP7 is connected to the gate of the ninth PMOS transistor MP9. The drain of the eighth PMOS transistor MP8 is connected to the drain of the third NMOS transistor MN3, the drain of the fifth NMOS transistor MP4, and the gate of the ninth NMOS transistor MP5. The source of MOSFET MN5 is connected to the source. The drain of the ninth PMOS transistor MP9 is connected to the drain of the fourth NMOS transistor MN4 and the source of the sixth NMOS transistor MN6. The drain of the tenth PMOS transistor MP10 is connected to the drain of the seventh NMOS transistor MN7. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the eighth NMOS transistor MN8. The gate of the third NMOS transistor MN3 is connected to the signal Vip. The source of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4 and the drain of the ninth NMOS transistor MN9. The gate of the fourth NMOS transistor MN4 is connected to the signal Vin. The seventh NMOS transistor... The source of S-channel transistor MN7, the source of the ninth NMOS transistor MN9, and the source of the eighth NMOS transistor MN8 are all connected to reference ground AGND. The gate of the ninth NMOS transistor MN9 is connected to signal CLK3B. The drain signal of the tenth PMOS transistor MP10 is named Vop. The drain signal of the eleventh PMOS transistor MP11 is named Von. The input terminal of the tenth inverter INV10 is connected to signal CLK3. The output terminal signal of the tenth inverter INV10 is named CLK3B. The drain voltage of the fourth PMOS transistor MP4 is named Vn. The drain voltage of the fifth PMOS transistor MP5 is named Vp.

[0014] In the clock control circuit, the CLK signal is the external input clock signal, and the Timer is the timer output signal, which is inverted and in phase with the ENB signal. CLK3 controls the reset and comparison of latch L1. The clock control circuit generates the critical clock signal required by the undervoltage protection circuit; the key signals generated by the circuit are shown in the attached figure. Figure 2 .

[0015] In the charge redistribution circuit, when the Timer and EN signal are low, the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are turned on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off. At this time, the first PMOS transistor MP1 and the second PMOS transistor MP2 charge the first capacitor C1 and the fourth capacitor C4 respectively, and the input voltage of latch L1 is equal to the power supply voltage AVDD. When the Timer and EN signal are high, the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are turned off, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on. Since VBG is a strong driving source, the voltage across the fourth capacitor C4 is 1.2V, and the voltage signal Vin at the inverting input of latch L1 is 1.2V. Meanwhile, the second capacitor C2 is connected in parallel to the non-inverting input of latch L1, resulting in charge redistribution. The voltage signal Vip at this time is:

[0016] When the clock signal CLK goes low, latch L1 quickly enters the comparison phase. If the voltage signal Vip is less than Vin at this time, the undervoltage protection signal UVLO_OK flips to a low level.

[0017] When CLK3 is high, the latch L1 is in the reset phase, with nodes Vp and Vn reset high, and outputs Vop and Von reset high. When CLK3 is low, the latch is in the comparison phase, determining the charge discharge rate of nodes Vp and Vn based on the magnitudes of the differential input signals Vip and Vin, resulting in a voltage difference between these two nodes. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 form a cross-coupled positive feedback structure. When there is a significant voltage difference between nodes Vp and Vn, a positive feedback response is triggered. Ultimately, one node is accelerated down to AGND, and the other node is accelerated up to AVDD. The output voltages Vop and Von are out of phase with Vin and Vip, respectively, completing the comparison. Throughout the entire process, power consumption only occurs during the comparison phase. Attached Figure Description

[0018] Figure 1 The diagram shown is a schematic diagram of the circuit structure of a low-power undervoltage protection circuit design based on charge redistribution proposed in this invention in an embodiment.

[0019] Figure 2 The figure shown is a waveform diagram of the key clock control signal of a low-power undervoltage protection circuit based on charge redistribution proposed in this invention.

[0020] Figure 3The diagram shows the output signal of a low-power undervoltage protection circuit based on charge redistribution proposed in this invention. Detailed Implementation

[0021] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings: like Figure 1 As shown, the present invention proposes a low-power undervoltage protection circuit based on charge redistribution, which includes a clock control circuit and a charge redistribution circuit.

[0022] The clock control circuit in this invention generates the key clock control signals required by the undervoltage protection circuit, such as... Figure 1 An implementation of an undervoltage protection circuit is given, comprising: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a first NAND gate NAND1, a second NAND gate NAND2, a voltage level converter LS1, and a first NOR gate NOR1.

[0023] The charge redistribution circuit in this invention includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a latch L1. The charge redistribution circuit is controlled by a timer output signal Timer and an enable signal EN, samples the power supply voltage signal, and compares the sampled signal with the bandgap reference voltage VBG.

[0024] The latch L1 in this invention includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth inverter INV10. When CLK3 is high, latch L1 is in the reset phase, and nodes Vp and Vn are reset to high, as are outputs Vop and Von. When CLK3 is low, latch L1 is in the comparison phase, determining the charge discharge rate of nodes Vp and Vn based on the magnitudes of the differential input signals Vip and Vin, resulting in a voltage difference between these two nodes. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 form a cross-coupled positive feedback structure. When there is a significant difference between the node voltages Vp and Vn, a positive feedback response is triggered. Ultimately, one node is accelerated down to AGND, and the other node is accelerated up to AVDD. The output voltages Vop and Von are out of phase with Vn and Vp, respectively, completing the comparison. Throughout the entire process, power consumption only occurs during the comparison phase; there is no static power consumption.

[0025] like Figure 2 As shown, the CLK signal is the external input clock signal, and the Timer is the timer output signal, which is inverted from the ENB signal and in phase with the EN signal. CLK3 controls the reset and comparison of latch L1.

[0026] like Figure 3 As shown, the power supply voltage AVDD increases linearly between 1.5V and 1.7V, with a slope of 20mV / ms. The power supply voltage AVDD corresponding to the first high level of the output signal UVLO_OK is the undervoltage protection threshold. Zooming in on the details of each waveform at the first high level, we can see that the undervoltage protection threshold is 1.622V.

Claims

1. A low-power undervoltage protection circuit based on charge redistribution, characterized in that, Includes clock control circuitry and charge redistribution circuitry; In the clock control circuit, the input terminal of the first inverter INV1 is connected to the external input signal CLK, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2. The output signal of the first inverter INV1 is named CLK1, and the output signal of the second inverter INV2 is named CLK2. The D terminal of the first D flip-flop DFF1 is connected to the input terminal of the second inverter DFF2. The reset terminals of the first and second D flip-flops, DFF1 and DFF2, are connected to the reset signal RST. The Clk terminal of the first D flip-flop, DFF1, is connected to the signal CLK1. The Q signal of the first D flip-flop, DFF1, is named D2. The terminal signal is named D2N; the D terminal of the second D flip-flop DFF2 is connected to the second D flip-flop DFF2. The Q signal of the second D flip-flop DFF2 is named D4; one end of the first NAND gate NAND1 is connected to signal D4, the other end of the first NAND gate NAND1 is connected to signal D2N, and the output of the first NAND gate NAND1 is connected to the D terminal of the third D flip-flop DFF3. The Clk terminal of the third D flip-flop DFF3 is connected to signal CLK2, and the Q terminal of the third D flip-flop DFF3 is connected to one end of the first level converter LS1. The terminal is connected to the other end of the first level converter LS1 and the input terminal of the third inverter INV3; the output signal of the Q terminal of the third D flip-flop DFF3 is named Timer_N. The output signal of the first inverter is named Timer_P, the output signal of the third inverter INV3 is named RST, and the output signal of the first voltage level converter LS1 is named Timer. The input of the fourth inverter INV4 is connected to the signal Timer. The output of the fourth inverter INV4 is connected to the input of the fifth inverter INV5. The output of the fifth inverter INV5 is connected to the input of the sixth inverter INV6. The output of the sixth inverter INV6 is connected to the input of the seventh inverter INV7. The output of the seventh inverter INV7 is connected to the second NAND gate NAND2. One end of the second NAND gate is connected to the clock signal CLK, and the other end of the second NAND gate NAND2 is connected to the signal Timer. The output of the second NAND gate NAND2 is connected to the input of the eighth inverter INV8. The output signal of the second NAND gate NAND2 is named ENB, and the output signal of the eighth inverter INV8 is named EN. One input of the first NOR gate NOR1 is connected to the clock signal CLK, and the other input of the first NOR gate NOR1 is connected to the signal ENB. The output of the first NOR gate NOR1 is connected to the input of the ninth inverter INV9. The output signal of the ninth inverter INV9 is named CLK3. In the charge redistribution circuit, the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to a signal timer. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are all connected to the power supply AVDD. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor, one end of the first capacitor C1, one end of the second capacitor C2, and the Vip terminal of the latch L1. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, one end of the fourth capacitor C4, and the Vin terminal of the latch L1. The drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN2. The drain of the first NMOS transistor MN1 and the other end of the second capacitor C2 are connected together; the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are connected to the signal EN; the source of the first NMOS transistor MN1, the other end of the first capacitor C1, one end of the third capacitor C3 and the other end of the fourth capacitor C4 are connected to the reference ground AGND; the source of the second NMOS transistor MN2 is connected to one end of the first resistor R1 and the other end of the third capacitor C3; the other end of the first resistor R1 is connected to the voltage signal VBG; the clock input of the latch L1 is connected to the clock signal CLK3; the output signal of the latch L1 is named UVLO_OK, which is the undervoltage protection signal.

2. The low-power undervoltage protection circuit based on charge redistribution according to claim 1, characterized in that, In latch L1, the gate of the fourth PMOS transistor MP4 is connected to the drains of the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the eleventh PMOS transistor MP11, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the eighth NMOS transistor MN8. The source of the fourth PMOS transistor MP4 is connected to the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the eleventh PMOS transistor MP11. The drain of transistor 4 is connected to the gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the tenth PMOS transistor MP10, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth PMOS transistor MP8. The gate of the seventh PMOS transistor MP7 is connected to the gate of the ninth PMOS transistor MP9. The drain of the eighth PMOS transistor MP8 is connected to the drain of the third NMOS transistor MN3 and the source of the fifth NMOS transistor MN5. The drain of the ninth PMOS transistor MP9 is connected to the drain of the fourth NMOS transistor MN4 and the source of the sixth NMOS transistor MN6. The tenth PMOS transistor... The drain of MP10 is connected to the drain of the seventh NMOS transistor MN7; the drain of the eleventh PMOS transistor MP11 is connected to the drain of the eighth NMOS transistor MN8; the gate of the third NMOS transistor MN3 is connected to the signal Vip; the source of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4 and the drain of the ninth NMOS transistor MN9; the gate of the fourth NMOS transistor MN4 is connected to the signal Vin; the sources of the seventh NMOS transistor MN7, the ninth NMOS transistor MN9, and the eighth NMOS transistor MN8 are all connected to the reference ground AGND; the input of the tenth inverter INV10 is connected to the signal CLK; the output signal of the tenth inverter INV10 is named CLK3B; the ninth NMOS transistor... The gate of S-channel transistor MN9 is connected to signal CLK3B. The drain signal of the tenth PMOS transistor MP10 is named Vop, the drain signal of the eleventh PMOS transistor MP11 is named Von, the drain signal of the fourth PMOS transistor MP4 is named Vn, and the drain signal of the fifth PMOS transistor MP5 is named Vp. Vop and Von are the two output terminals of the protection circuit. When CLK3 is high, latch L1 is in the reset stage, nodes Vp and Vn are reset to high, and outputs Vop and Von are reset to high. When CLK3 is low, latch L1 is in the comparison stage, and the charge discharge rate of nodes Vp and Vn is determined according to the magnitude of the differential input signals Vip and Vin.

3. The low-power undervoltage protection circuit based on charge redistribution according to claim 1, characterized in that, The first capacitor C1 is a MOS capacitor, MIM capacitor, or MOM capacitor; the second capacitor C2 is a MOS capacitor, MIM capacitor, or MOM capacitor; the third capacitor C3 is a MOS capacitor, MIM capacitor, or MOM capacitor; and the fourth capacitor C4 is a MOS capacitor, MIM capacitor, or MOM capacitor.

4. A low-power undervoltage protection circuit based on charge redistribution according to claim 1, characterized in that, The first resistor R1 is a P-type Poly resistor or a trap resistor.

5. A low-power undervoltage protection circuit based on charge redistribution according to claim 1, characterized in that, The substrates of all NMOS transistors are grounded, and the substrates of all PMOS transistors are connected to the power supply.

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