Pfc current sampling point control method and device, and electronic equipment

Abstract

The application provides a PFC current sampling point control method and device and electronic equipment. The method comprises: obtaining a current sampling value at a current AD sampling time in a current PWM control period; the current sampling value comprises a current input voltage, a current output voltage and a current inductance current in a PFC circuit; predicting an output duty ratio corresponding to a next PWM control period according to the current sampling value; and determining a target AD sampling time in the next PWM control period according to the output duty ratio corresponding to the next PWM control period. The application can avoid sampling at a time close to IGBT conduction or turn-off, thereby avoiding sampling of switching noise, achieving good switching noise immunity, accurately measuring an average input current, and only requiring a small amount of processor operation resources.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a PFC current sampling point control method, device and electronic equipment. Background Technology

[0002] Most power electronic devices use direct current (DC) internally. If they need to be powered from the AC grid, they need to be converted from AC to DC. Single-phase diode rectifiers are widely used in low-power single-phase household appliances such as air conditioners, heat pumps, washing machines, and refrigerators to provide DC power to downstream compressors and fans. If uncontrolled rectifiers are used alone, their AC input current waveforms contain a large number of harmonics, which can cause resonance, power waveform distortion, and thus pollute the power grid. To suppress rectifier input current harmonics, single-phase powered household appliances need to meet the harmonic standards of IEC 61000-3-2 and require the installation of PFC (Power Factor Correction) devices.

[0003] Digital control of a PFC converter requires sampling the input voltage Vac, output voltage Vdc, and inductor current iL (the absolute value of the input current iac). Since the input current contains a significant amount of switching ripple and high-frequency switching noise, the timing of the sampling is crucial. Existing technologies synchronize sampling with PWM (Pulse Width Modulation), achieving average current control by sampling the inductor current at the midpoint of the IGBT (Insulated Gate Bipolar Transistor) turn-on period. While this sampling algorithm successfully suppresses input current ripple, it cannot avoid the influence of high-frequency switching noise present in all sampled signals. Because the PFC output duty cycle is very small during light load or power peak / valley times, switching noise can be sampled. If this switching noise from the IGBT is introduced into the PFC control algorithm's loop, it can degrade the input current waveform, increase harmonic content, and in extreme cases, even cause PFC control failure. Summary of the Invention

[0004] The purpose of this application is to provide a PFC current sampling point control method, device, and electronic device. Based on the sampling value in the current PWM control cycle, the output duty cycle of PFC in the next PWM control cycle is predicted. The sampling time is determined according to the magnitude of the output duty cycle, avoiding sampling when it is close to the IGBT turn-on or turn-off, thereby avoiding sampling of switching noise. It can achieve good switching noise immunity performance, accurately measure the average input current, and requires only a small amount of processor computing resources.

[0005] In a first aspect, embodiments of this application provide a PFC current sampling point control method, which is applied to a controller connected to a PFC circuit; the method includes: obtaining the current sampled value at the current AD sampling moment within the current PWM control cycle; the current sampled value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit; predicting the output duty cycle corresponding to the next PWM control cycle based on the current sampled value; and determining the target AD sampling moment within the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle.

[0006] In a preferred embodiment of this application, the step of predicting the output duty cycle corresponding to the next PWM control cycle based on the current sampled value includes: determining the voltage loop output voltage based on the current output voltage and the preset voltage loop PI controller; determining the current loop output duty cycle based on the voltage loop output voltage, the current input voltage, the current inductor current and the preset current loop PI controller; and determining the output duty cycle corresponding to the next PWM control cycle based on the current loop output duty cycle.

[0007] In a preferred embodiment of this application, the step of determining the voltage loop output voltage based on the current output voltage and a preset voltage loop PI controller includes: determining the voltage error based on the current output voltage and a preset reference voltage; inputting the voltage error to the preset voltage loop PI controller to calculate the voltage loop output voltage.

[0008] In a preferred embodiment of this application, the step of determining the output duty cycle based on the voltage loop output voltage, the current input voltage, the current inductor current, and a preset current loop PI controller includes: using the product of the voltage loop output voltage and the current input voltage as a reference current value; determining the current error based on the current inductor current and the reference current value; and inputting the current error to the preset current loop PI controller to calculate the current loop output duty cycle.

[0009] In a preferred embodiment of this application, the step of determining the output duty cycle corresponding to the next PWM control cycle based on the current loop output duty cycle includes: using the current loop output duty cycle as the output duty cycle corresponding to the next PWM control cycle; or, determining the duty cycle feedforward value based on the current input voltage and the current output voltage, and summing the current loop output duty cycle and the duty cycle feedforward value to obtain the output duty cycle corresponding to the next PWM control cycle.

[0010] In a preferred embodiment of this application, the step of determining the duty cycle feedforward value based on the current input voltage and the current output voltage includes: calculating the duty cycle feedforward value according to the following specified formula:

[0011] DutyFF = 1 - k * Vac / Vdc;

[0012] Where DutyFF is the duty cycle feedforward value; k represents the coefficient; Vac represents the current input voltage; and Vdc represents the current output voltage.

[0013] In a preferred embodiment of this application, the step of determining the target AD sampling time in the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle includes: determining whether the output duty cycle is greater than 0.5; if so, determining the comparison value at which a comparison match occurs based on the output duty cycle; determining half of the comparison value as the target AD sampling time in the next PWM control cycle; if not, determining the target AD sampling time in the next PWM control cycle based on the comparison value and the carrier period.

[0014] In a preferred embodiment of this application, the step of determining the target AD sampling time in the next PWM control cycle based on the comparison value and the carrier period includes: calculating the average value of the comparison value and the carrier period; and determining the average value as the target AD sampling time in the next PWM control cycle.

[0015] Secondly, embodiments of this application also provide a PFC current sampling point control device, which is applied to a controller connected to a PFC circuit; the device includes: a sampling value acquisition module, used to acquire the current sampling value at the current AD sampling moment within the current PWM control cycle; the current sampling value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit; a duty cycle prediction module, used to predict the output duty cycle corresponding to the next PWM control cycle based on the current sampling value; and a sampling moment determination module, used to determine the target AD sampling moment within the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle.

[0016] Thirdly, embodiments of this application also provide an electronic device, including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the method described in the first aspect above.

[0017] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are invoked and executed by a processor, the computer-executable instructions cause the processor to implement the method described in the first aspect above.

[0018] This application provides a PFC current sampling point control method, device, and electronic device. First, the current sampled value at the current AD sampling moment within the current PWM control cycle is obtained. This current sampled value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit. Then, the output duty cycle corresponding to the next PWM control cycle is predicted based on the current sampled value. Finally, the target AD sampling moment within the next PWM control cycle is determined based on the output duty cycle corresponding to the next PWM control cycle. This solution can predict the PFC output duty cycle in the next PWM control cycle based on the sampled value in the current PWM control cycle, and determine the sampling moment based on the magnitude of the output duty cycle. This avoids sampling occurring close to the IGBT's turn-on or turn-off moment, thus avoiding sampling switching noise. It achieves excellent switching noise immunity performance, accurately measures the average input current, and requires only a small amount of processor computing resources. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a PFC main circuit scenario provided in an embodiment of this application;

[0021] Figure 2 A flowchart of a PFC current sampling point control method provided in this application embodiment;

[0022] Figure 3 A flowchart illustrating the duty cycle determination process in a PFC current sampling point control method provided in this application embodiment;

[0023] Figure 4 A schematic diagram illustrating a duty cycle determination process provided in an embodiment of this application;

[0024] Figure 5 A flowchart of another current sampling point control method provided in the embodiments of this application;

[0025] Figure 6 A schematic diagram of a PFC current sampling point control process provided in an embodiment of this application;

[0026] Figure 7 A structural block diagram of a PFC current sampling point control device provided in this application embodiment;

[0027] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] Figure 1 This diagram illustrates the structure of a single-phase Boost PFC main circuit application scenario. The circuit includes a single-phase Boost PFC and a dual-motor control circuit, and is very common in the white goods industry, such as typical household air conditioners and heat pump products. Its rectifier is a Boost PFC, such as... Figure 1 As shown, its main circuit mainly consists of a rectifier bridge, a PFC inductor (L), and switching devices such as IGBTs (e.g., ...). Figure 1 The S in the diagram represents a fast recovery diode (D). The inverter side controls the compressor and fan loads. For the Boost PFC algorithm, it requires sampling the real-time output bus voltage V. dc Inductor current i L and the input voltage V at the back end of the rectifier diode. ac The BoostPFC algorithm mainly consists of two loops: an outer voltage loop and an inner current loop. Its final output is the duty cycle pulse signal that drives the IGBT switching device. Figure 1 The arrow to the left of the S corresponds to the output duty cycle. In existing technologies, sampling is performed at the midpoint of a cycle regardless of the output duty cycle of the IGBT in the PFC circuit. When the duty cycle is extremely low, switching noise is easily sampled, leading to PFC control failure.

[0030] Based on this, embodiments of this application provide a PFC current sampling point control method, device, and electronic device. Based on the sampling value in the current PWM control cycle, the output duty cycle of PFC in the next PWM control cycle is predicted. The sampling time is determined according to the magnitude of the output duty cycle, and a clean current signal is sampled so that the control effect of PFC will not fail due to sampling problems.

[0031] To facilitate understanding of this embodiment, a PFC current sampling point control method disclosed in this application embodiment will first be described in detail.

[0032] Figure 2This application provides a flowchart of a PFC current sampling point control method according to an embodiment of the present application. This method can be applied to a controller connected to a PFC circuit. The control method is a continuously looping control process, and the structure of the PFC circuit is as follows: Figure 1 As shown, the method specifically includes the following steps:

[0033] Step S102: Obtain the current sampled value at the current AD sampling time within the current PWM control cycle; the current sampled value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit.

[0034] If the current PWM control cycle is the first control cycle in the PFC circuit, then the current AD sampling time can be the preset sampling time; if the current PWM control cycle is not the first control cycle in the PFC circuit, then the current sampling time is the target sampling time determined in the previous PWM control cycle. The current input voltage, current output voltage, and current inductor current in the above PFC circuit are respectively as follows: Figure 1 The V shown ac V dc i L .

[0035] Step S104: Predict the output duty cycle corresponding to the next PWM control cycle based on the current sampled value.

[0036] The Boost PFC algorithm mainly has two loops: an outer loop (voltage loop) and an inner loop (current loop). In this embodiment, the PI controllers corresponding to the voltage loop and current loop respectively calculate and control the above sampled values ​​to obtain the output duty cycle corresponding to the next PWM control cycle, which is the duty cycle pulse signal corresponding to the IGBT in the next control cycle.

[0037] Step S106: Determine the target AD sampling time in the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle.

[0038] The target AD sampling time in the next PWM control cycle is adjusted according to the output duty cycle of the next PWM control cycle. This avoids sampling occurring close to the IGBT turn-on or turn-off time, thus avoiding sampling switching noise and sampling a clean current value. This achieves good switching noise immunity performance and can accurately measure the average input current with only a small amount of processor computing resources.

[0039] In a PFC current sampling point control method provided in this application embodiment, the current sampled value at the current AD sampling time within the current PWM control cycle is first obtained. This current sampled value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit. Then, the output duty cycle corresponding to the next PWM control cycle is predicted based on the current sampled value. Finally, the target AD sampling time within the next PWM control cycle is determined based on the output duty cycle corresponding to the next PWM control cycle. This solution can predict the PFC output duty cycle in the next PWM control cycle based on the sampled value in the current PWM control cycle, and determine the sampling time based on the magnitude of the output duty cycle. This avoids sampling occurring close to the IGBT's turn-on or turn-off time, thereby avoiding sampling switching noise. It achieves excellent switching noise immunity performance and can accurately measure the average input current, requiring only a small amount of processor computing resources.

[0040] This application also provides a PFC current sampling point control method, which is implemented based on the previous embodiment. This embodiment focuses on describing the duty cycle prediction process and the sampling time determination process.

[0041] See Figure 3 As shown, the steps described above for predicting the output duty cycle corresponding to the next PWM control cycle based on the current sampled value include:

[0042] Step S302: Determine the voltage loop output voltage based on the current output voltage and the preset voltage loop PI controller.

[0043] See Figure 4 The diagram illustrates a calculation process for the duty cycle (Duty). In practical implementation, this can be based on the current output voltage V. dc With preset reference voltage Determine the voltage error; then input the voltage error to a preset voltage loop PI controller (e.g., Figure 4 The voltage loop output voltage V is calculated using VoltLp. m .

[0044] Step S304: Determine the current loop output duty cycle based on the voltage loop output voltage, the current input voltage, the current inductor current, and the preset current loop PI controller.

[0045] In practical implementation, the voltage loop output voltage V m With the current input voltage V ac The product of these two values ​​is used as the reference current value i. ref According to the current inductor current i L and reference current value i ref Determine the current error; input the current error to the preset current loop PI controller (e.g., Figure 4The current loop output duty cycle is calculated using CurLp (not shown in the figure).

[0046] Step S306: Determine the output duty cycle corresponding to the next PWM control cycle based on the current loop output duty cycle.

[0047] In practice, the current loop output duty cycle can be used as the output duty cycle (Duty) for the next PWM control cycle; or, based on the current input voltage V... ac and the current output voltage V dc Determine the duty cycle feedforward value, that is Figure 4 The FeedForward function in the middle sums the current loop output duty cycle with the duty cycle feedforward value to obtain the output duty cycle (Duty) corresponding to the next PWM control cycle.

[0048] In a preferred embodiment of this application, the step of determining the duty cycle feedforward value based on the current input voltage and the current output voltage includes: calculating the duty cycle feedforward value according to the following specified formula:

[0049] DutyFF = 1 - k * V ac / V dc ;

[0050] Where DutyFF is the duty cycle feedforward value; k represents the coefficient; V ac Indicates the current input voltage; V dc This indicates the current output voltage.

[0051] In this embodiment, the bus voltage is kept constant by introducing output voltage feedback, and the output voltage sample V is obtained after voltage division sampling. dc With voltage reference value Compare, The target boost voltage value for final control is a preset value based on control requirements. The error result of the voltage loop is fed into the voltage loop PI controller, forming the outer voltage loop control, i.e. Figure 4 The output V of the voltage loop is represented by VoltLp. m With input voltage V ac The product of these two values ​​is used as a reference value for the inner current loop CurLp, since V ac It contains phase information of the power supply, enabling the input current to sinusoidally track the input voltage. To reduce the computational burden of the current loop CurLp, and to meet the requirement of tracking instantaneous changes in the power supply, a feedforward loop is introduced, whose input is V. ac and V dc The output is a partial duty cycle, i.e., the duty cycle feedforward value. Ultimately, from the input, the entire load appears to be purely resistive, with a power factor close to 1 and very low current harmonics, thus achieving the effect of power factor correction.

[0052] See Figure 5 As shown, the entire sampling time determination process is as follows: sampling V in the current period. ac V dc i L Then, the VoltLp voltage loop controller performs some calculations to obtain the given current, such as the aforementioned reference current value i. ref Then, the target duty cycle, i.e. the output duty cycle of the next cycle, is output through the CurLp current loop controller and the Feed Forward module.

[0053] Then determine if the output duty cycle is greater than 0.5; if so, determine the comparison value Comp that caused the comparison match based on the output duty cycle; usually, the comparison value can be obtained by multiplying the digital value corresponding to the period register by the output duty cycle; half of the comparison value Comp is determined as the target AD sampling time in the next PWM control cycle, such as TrigVal = Comp / 2.

[0054] If the output duty cycle is less than or equal to 0.5, the target AD sampling time in the next PWM control cycle is determined based on the comparison value Comp and the carrier period Ts. In practice, the average value of the comparison value and the carrier period is calculated, and this average value is used as the target AD sampling time in the next PWM control cycle; for example, TrigVal = (Ts + Comp) / 2. Here, Ts refers to the carrier period, which is the reciprocal of the carrier interruption.

[0055] See Figure 6 As shown in the diagram, this illustration uses a sawtooth carrier wave, with a high-level active signal when a comparison match occurs. It should be noted that this algorithm is applicable to triangular carrier waves, or to all other wave transmission methods and high / low level combinations mentioned above. The only requirement is to adjust the configuration according to the register settings of the selected chip. Figure 6In the process, an interrupt is generated at the peak of each sawtooth wave. The PFC algorithm is executed every time an interrupt is entered, as shown in ①②③④ in the figure. After the PFC control algorithm is executed in interrupt ①, a target duty cycle is output. Based on whether the target duty cycle is greater than 0.5, the corresponding duty cycle is converted into a comparison value Comp that causes a comparison match, and the AD sampling trigger time for the next PWM cycle is determined. The reason why the comparison value buffer CompBuf and trigger value buffer TrigBuf calculated in the current PWM cycle are only updated in the next PWM cycle is that the execution of the interrupt algorithm also requires a short period of time. If the calculation is performed in the current PWM cycle and updated immediately, it will cause disorder between the target value and the calculated value. Therefore, CompBuf_1 and TrigBuf_1 calculated in interrupt ① are updated in the PWM cycles between ② and ③, and CompBuf_2 and TrigBuf_2 calculated in interrupt ② are updated in the PWM cycles between ③ and ④.

[0056] exist Figure 6 In this PWM cycle, since the inductor is an energy storage element, its current increases linearly when the IGBT is on and decreases linearly when the IGBT is off, provided the inductor is not saturated. Furthermore, although the inductor current slopes differ during on and off states, the maximum and minimum values ​​of the inductor current during the decrease (iL-max and iL-min) are exactly the same as those during the increase, and their average value (iL-ave) is also identical.

[0057] Assuming the Duty calculated by interrupt ① is less than 0.5, and since the carrier wave is a sawtooth wave, a high level is active when a comparison match occurs. Therefore, in the PWM cycle between ② and ③, the inductor current's decline time is longer than its rise time. If the current is sampled when the PWM is high, it's possible to sample the switching noise current at the IGBT's turn-on and turn-off times when the duty cycle is extremely small. When Duty < 0.5, the IGBT's turn-off time is long, ensuring a relatively linear current during the iL decline. Triggering sampling at the midpoint of the decline not only samples the iL-ave current but also perfectly avoids sampling the switching noise current.

[0058] Similarly, assuming the Duty calculated by interrupt ② is greater than 0.5, since the carrier wave is a sawtooth wave, a high level is active when a comparison match occurs. Therefore, in the PWM cycle between ③ and ④, the inductor current rises for a longer time than it falls. If the current is sampled when the PWM is low, it is possible to sample the switching noise current at the IGBT turn-on and turn-off times when the duty cycle is extremely large. When Duty > 0.5, the IGBT turn-on time is long, which can ensure that the current is relatively linear during the rise of iL. Triggering sampling at the midpoint of the rise not only samples the iL-ave current but also perfectly avoids sampling the switching noise current. Figure 6 In the diagram, PWM1 represents the high level corresponding to the duty cycle between interrupts ② and ③, and PWM2 represents the high level corresponding to the duty cycle between interrupts ③ and ④.

[0059] like Figure 5 The diagram shows the interrupt procedure flowchart for the duty cycle-based PFC current sampling point predictive control method. Upon entering the interrupt, the bus voltage Vdc, inductor current iL, and input voltage Vac are sampled first. Then, the outer voltage loop calculates the reference current for the inner loop. Since the reference current also requires phase information from the power supply, the output of the outer voltage loop needs to incorporate the phase of the input Vac before it can be used as the reference for the inner loop. The inner loop can be either a current loop control or an external single-cycle control, both ultimately outputting the target duty cycle. To reduce the computational burden on the inner loop and improve the dynamic response of the PFC control system, a portion of the target duty cycle is calculated using a feedforward method to reduce the loop's adjustment burden. After obtaining the final duty cycle, it can be used... Figure 6 The method described in the text is used to predict the AD sampling trigger time.

[0060] The PFC current sampling point control method provided in this application avoids the pitfalls of traditional Boost PFC, which, by forcibly setting a minimum duty cycle to prevent sampling of oscillating current during switching when the duty cycle is extremely low, through PFC current sampling point prediction triggering based on the output duty cycle. This ensures the stability and reliability of PFC control when the duty cycle is extremely low at voltage peaks and troughs. This embodiment predicts the PFC output duty cycle and determines the sampling time based on the predicted duty cycle, avoiding sampling near the IGBT's turn-on or turn-off moment, thus preventing the sampling of switching noise. Using this method, excellent switching noise immunity performance can be achieved, and the average input current can be accurately measured, requiring only a small amount of processor computing resources.

[0061] Based on the above method embodiments, this application also provides a PFC current sampling point control device, which is applied to a controller connected to a PFC circuit; see also Figure 7As shown, the device includes: a sampling value acquisition module 72, used to acquire the current sampling value at the current AD sampling moment within the current PWM control cycle; the current sampling value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit; a duty cycle prediction module 74, used to predict the output duty cycle corresponding to the next PWM control cycle based on the current sampling value; and a sampling moment determination module 76, used to determine the target AD sampling moment within the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle.

[0062] In a preferred embodiment of this application, the duty cycle prediction module 74 is used to determine the voltage loop output voltage based on the current output voltage and the preset voltage loop PI controller; determine the current loop output duty cycle based on the voltage loop output voltage, the current input voltage, the current inductor current and the preset current loop PI controller; and determine the output duty cycle corresponding to the next PWM control cycle based on the current loop output duty cycle.

[0063] In a preferred embodiment of this application, the duty cycle prediction module 74 is used to determine the voltage error based on the current output voltage and the preset reference voltage; input the voltage error to the preset voltage loop PI controller to calculate the voltage loop output voltage.

[0064] In a preferred embodiment of this application, the duty cycle prediction module 74 is used to take the product of the voltage loop output voltage and the current input voltage as a reference current value; determine the current error based on the current inductor current and the reference current value; input the current error to a preset current loop PI controller to calculate the current loop output duty cycle.

[0065] In a preferred embodiment of this application, the duty cycle prediction module 74 is used to take the current loop output duty cycle as the output duty cycle corresponding to the next PWM control cycle; or, based on the current input voltage and the current output voltage, the duty cycle feedforward value is determined, and the current loop output duty cycle and the duty cycle feedforward value are summed to obtain the output duty cycle corresponding to the next PWM control cycle.

[0066] In a preferred embodiment of this application, the duty cycle prediction module 74 is used to calculate the duty cycle feedforward value according to the following specified formula:

[0067] DutyFF = 1 - k * Vac / Vdc;

[0068] Where DutyFF is the duty cycle feedforward value; k represents the coefficient; Vac represents the current input voltage; and Vdc represents the current output voltage.

[0069] In a preferred embodiment of this application, the sampling time determination module 76 is used to determine whether the output duty cycle is greater than 0.5; if so, it determines the comparison value at which a comparison match occurs based on the output duty cycle; and determines half of the comparison value as the target AD sampling time in the next PWM control cycle; if not, it determines the target AD sampling time in the next PWM control cycle based on the comparison value and the carrier period.

[0070] In a preferred embodiment of this application, the sampling time determination module 76 is used to obtain the average value of the comparison value and the carrier period; and to determine the average value as the target AD sampling time in the next PWM control cycle.

[0071] The device provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts of the device embodiment not mentioned can be referred to the corresponding content in the aforementioned method embodiment.

[0072] This application also provides an electronic device, such as... Figure 8 The diagram shows the structure of the electronic device, which includes a processor 81 and a memory 80. The memory 80 stores computer-executable instructions that can be executed by the processor 81, and the processor 81 executes the computer-executable instructions to implement the above-described method.

[0073] exist Figure 8 In the illustrated embodiment, the electronic device further includes a bus 82 and a communication interface 83, wherein the processor 81, the communication interface 83, and the memory 80 are connected via the bus 82.

[0074] The memory 80 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 83 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 82 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 82 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0075] Processor 81 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 81 or by software instructions. The processor 81 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor 81 reads the information in the memory and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0076] This application also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-described method. For specific implementation details, please refer to the foregoing method embodiments, which will not be repeated here.

[0077] The computer program products of the methods, apparatus, and electronic devices provided in the embodiments of this application include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementations, please refer to the method embodiments, which will not be repeated here.

[0078] Unless otherwise specifically stated, the relative steps, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application.

[0079] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0081] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A PFC current sampling point control method, characterized in that, The method is applied to a controller connected to a PFC circuit; the method includes: Obtain the current sampled value at the current AD sampling moment within the current PWM control cycle; the current sampled value includes the current input voltage, current output voltage, and current inductor current in the PFC circuit; Predicting the output duty cycle for the next PWM control cycle based on the current sampled value includes: determining a voltage error based on the current output voltage and a preset reference voltage; inputting the voltage error to a preset voltage loop PI controller to calculate the voltage loop output voltage; using the product of the voltage loop output voltage and the current input voltage as a reference current value; determining a current error based on the current inductor current and the reference current value; inputting the current error to a preset current loop PI controller to calculate the current loop output duty cycle; and using the current loop output duty cycle as the output duty cycle for the next PWM control cycle; or, determining a duty cycle feedforward value based on the current input voltage and the current output voltage, and summing the current loop output duty cycle with the duty cycle feedforward value to obtain the output duty cycle for the next PWM control cycle. Based on the output duty cycle corresponding to the next PWM control cycle, the target AD sampling time within the next PWM control cycle is determined.

2. The method according to claim 1, characterized in that, The step of determining the duty cycle feedforward value based on the current input voltage and the current output voltage includes: Calculate the duty cycle feedforward value according to the following specified formula: ； in, This is the duty cycle feedforward value; Indicates coefficient; Indicates the current input voltage; This indicates the current output voltage.

3. The method according to claim 1, characterized in that, The step of determining the target AD sampling time within the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle includes: Determine whether the output duty cycle is greater than 0.5; If so, determine the comparison value at which a comparison match occurs based on the output duty cycle; determine half of the comparison value as the target AD sampling time in the next PWM control cycle; If not, determine the target AD sampling time within the next PWM control cycle based on the comparison value and the carrier period.

4. The method according to claim 3, characterized in that, The steps for determining the target AD sampling time within the next PWM control cycle based on the comparison value and the carrier period include: Calculate the average of the comparison value and the carrier period; The average value is determined as the target AD sampling time in the next PWM control cycle.

5. A PFC current sampling point control device, characterized in that, The device is used in a controller connected to a PFC circuit; the device includes: The sampling value acquisition module is used to acquire the current sampling value at the current AD sampling moment within the current PWM control cycle; the current sampling value includes the current input voltage, current output voltage and current inductor current in the PFC circuit; The duty cycle prediction module is used to predict the output duty cycle corresponding to the next PWM control cycle based on the current sampled value, including: determining a voltage error based on the current output voltage and a preset reference voltage; inputting the voltage error to a preset voltage loop PI controller to calculate the voltage loop output voltage; using the product of the voltage loop output voltage and the current input voltage as a reference current value; determining a current error based on the current inductor current and the reference current value; inputting the current error to a preset current loop PI controller to calculate the current loop output duty cycle; using the current loop output duty cycle as the output duty cycle corresponding to the next PWM control cycle; or, determining a duty cycle feedforward value based on the current input voltage and the current output voltage, and summing the current loop output duty cycle with the duty cycle feedforward value to obtain the output duty cycle corresponding to the next PWM control cycle; The sampling time determination module is used to determine the target AD sampling time within the next PWM control cycle based on the output duty cycle corresponding to the next PWM control cycle.

6. An electronic device, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the method of any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked and executed by a processor, cause the processor to perform the method described in any one of claims 1 to 4.

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